DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Page 6-7 of Remarks, filed 17 September 2025, with respect to the drawings and claims 14, 17, and 22 and have been fully considered and are persuasive. The objections to the drawings and the 35 USC § 112 rejections of claims 14, 17, and 22 have been withdrawn.
Applicant's arguments filed, see Page 7 of the Remarks with respect to 35 USC § 102 and/or § 103 rejection of claims 1, 11, and 16 has been fully considered but they are not persuasive and upon further consideration, a new ground(s) of rejection is made in view of Teh (US 20140159228 A1) for claims 1 and 16 and in view of Kim (US 20200058567 A1) for claim 11.
Applicant argues on Page 7 of the Remarks that Zhang does not teach a substrate having two redistribution layers and that Zhang does not teach the substrate having a glass core. The examiner respectfully disagrees. Zhang’s bridge substrate 104 (see Fig. 1 and ¶ 0018) has a core 304 (see Fig. 3, ¶ 0023). Zhang’s core 304 is further flanked by two redistribution layers, i.e., the metal layer 308 found in dielectric layers 302 and 306. These are redistribution layers as evidenced by Gu (US 9368450 B1). Hence, Zhang’s Figure 3 is structurally the same as Applicant’s Fig. 7 wherein substrate 710 comprises a core 712 and redistribution layer 514 and 522, with the redistribution layers comprised of metal lines 516 surround by dielectric layers, see paragraph 0029 of the instant application. Although Zhang’s core is not explicitly a glass core, Kim teaches a glass core. Furthermore, Teh teaches the glass core to be glass bridge die, as recited by claims 1 and 16.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 6-7, 10, 16, and 21-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 20190304892 A1) and further in view of Kim (US 20200058567 A1) and Teh (US 20140159228 A1).
Regarding claim 1, Zhang teaches an electronic device comprising:
a substrate (Fig. 1, [0023]: 104) including first (Fig. 3, [0027]-[0028], [0022]: 302; this is a dielectric layer containing interconnect wiring 308 located on the die side S1; hence upper 308 it is a first redistribution layer as evidenced by Gu (US 9368450 B1) Col. 4, Lns 24-49) and second (lower 308 within 306 located on the land side S2; see [0029]) redistribution layers;
a core bridge layer (304 is a core layer of substrate 104; see [0023]; also [0028], [0065]: substrate 102 contains die interconnect region such as a silicon bridge; hence 304 is a core bridge layer) between the first and second redistribution layers (see [0027]), the core bridge layer including electrically conductive interconnect (as shown in Fig. 3 and [0027], 304 contains vias, not labelled, that connects top RDL 302 to bottom RDL 306 and RDL 302 and 306 having interconnects 308; also see in the secondary reference, i.e., Kim, specifically teaching a through-glass via); and
a first integrated circuit (IC) die (Fig. 1, [0018]: 102a) and at least a second IC die (Fig. 1, [0018]: 102b) arranged on a surface (top surface of 104) of the substrate and electrically coupled (Figs. 1 & 3 and [0028]-[0029]: substrate 104 has a die side S1 and a land side S2, with the die side having a bridge to connect two dies 102a and 102b and the land side connected to circuit board 122; ) to the interconnect of the core bridge layer (the unmarked conductive interconnect electrically couples the first and second redistribution layers together; see also secondary reference Kim).
However, Zhang does not teach the core bridge layer to be made of glass and Zhang does not explicitly teach the core bridge layer including electrically conductive interconnect.
Kim, in the same field of invention, teaches a core bridge layer (Fig. 1, [0030]: 14; alternatively, Fig. 5, [0055]: 304) made of glass ([0030] or alternatively [0055]) and the core bridge layer including electrically conductive interconnect (47).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Zhang into the device of Kim to provide a glass bridge layer as a core bridge layer in an electronic device at least comprising of a substrate having a first and a second redistribution layers, with the glass bridge layer located between the first and second redistribution layers and having electrically conductive interconnect, a first integrated circuit die and a second integrated circuit die on a surface of the substrate. The ordinary artisan would have been motivated to modify Zhang in the manner set forth above for at least the purpose of substituting the unknown material of the core layer of Zhang with the glass material of Kim for the predictable result of providing an insulated mounting material on which the IC dies can be mounted (Kim [0030]) and for the further purpose of using the glass bridge die as part of a reconstituted wafer packaging process (Kim [0005]) that further produces thinner and smaller electronic packages (Kim [0005], [0026]) and reduced manufacturing costs (Kim [0026]). Furthermore, the ordinary artisan would have been motivated to use the electrically conductive interconnect to electrically connect the second redistribution layer to the first redistribution layer (Kim [0043], [0045] and Fig 1: 47 connects 34 to 28).
However, Zhang in view of Kim does not teach the glass bridge layer to be a glass bridge die.
Teh, in the same field of invention, teaches a glass bridge layer (114, see Fig. 2 and [0018] wherein 114 is a core layer of a bridge having at least one redistribution layer 116B/116A) to be a glass bridge die (see [0074]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Teh into the device of Zhang in view of Kim to have the glass bridge layer to be comprised of a glass bridge die. The ordinary artisan would have been motivated to modify Zhang in view of Kim in the manner set forth above for at least the purpose of providing various ways (Teh [0074]) of enabling a high-density interconnect element that electrically bridges at least two dies that can be further embedded in another substrate (Teh [0011]) for the further purpose of increasing device density and reducing manufacturing cost (Teh [0013]-[0015]).
Regarding claim 6, the electronic device of claim 1, wherein the glass bridge die includes a uniform glass layer (Kim Fig. 1 shows 14 is not composed of multiple layers; hence, using BRI, it is a uniform glass layer).
Regarding claim 7, the electronic device of claim 1, wherein the glass bridge die includes a through glass via (TGV) (Kim Fig. 1, [0043]: 47 is a TGV since it is a via inside the glass core 14) extending from a first surface (Kim Fig. 1: top surface of 14;) of the glass bridge die to a second surface (Kim Fig. 1: bottom surface of 14;) of the glass bridge die.
Regarding claim 10, the electronic device of claim 1, wherein the first IC die and the at least the second IC die include multiple chiplets (Zhang [0017], [0021]: SOC; “chiplets” as defined by Applicant in [0017] are discrete chips such as an SOC)
Regarding claim 16, Zhang teaches the packaged electronic system, the system comprising:
a substrate (Fig. 1, [0023]: 104) including first (Fig. 3, [0027]-[0028], [0022]: 302; this is a dielectric layer containing interconnect wiring 308 located on the die side S1; hence upper 308 it is a first redistribution layer as evidenced by Gu (US 9368450 B1) Col. 4, Lns 24-49) and second (lower 308 within 306 located on the land side S2; see [0029]) redistribution layers;
a core bridge layer (304 is a core layer of substrate 104; see [0023]; also [0028], [0065]: substrate 102 contains die interconnect region such as a silicon bridge; hence 304 is a core bridge layer), between the first and second redistribution layers (see [0027]), the glass bridge die including electrically conductive interconnect (as shown in Fig. 3 and [0027], 304 contains via, not labelled, that connects top RDL 302 to bottom RDL 306 and RDL 302 and 306 having interconnects 308; also see in the secondary reference, i.e., Kim, specifically teaching a through-glass via);
multiple chiplets (Fig. 1, [0018], [0021]: 102a & 102b; [0017]: SOC; “chiplets” as defined by Applicant in [0017] are discrete chips such as an SOC) disposed on a surface (top surface of 104) of the substrate wherein at least two chiplets are electrically coupled (Fig. 1 shows die interconnect region 116 connecting the two dies 102a and 102b to 104; also, [0028]-[0029]: substrate 104 has a die side S1 and a land side S2, with the die side having a bridge to connect two dies 102a and 102b and the land side connected to circuit board 122) to the electrically conductive interconnect of the core bridge layer (the unmarked conductive interconnect electrically couples the first and second redistribution layers together; see also secondary reference Kim).
However, Zhang does not teach the core bridge layer to be made of glass Zhang does not explicitly teach the core bridge layer including electrically conductive interconnect.
Kim, in the same field of invention, teaches a core bridge layer (Fig. 1, [0030]: 14; alternatively, Fig. 5, [0055]: 304) made of glass ([0030] or alternatively [0055]) and the core bridge layer including electrically conductive interconnect (47).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Zhang into the device of Kim to provide a glass bridge layer as a core bridge layer in an electronic system at least comprising of a substrate having a first and a second redistribution layers, with the glass bridge die between the first and the second redistribution layers and having an electrically conductive interconnect, and a plurality of chiplets electrically coupled to the conductive interconnect. The ordinary artisan would have been motivated to modify Zhang in the manner set forth above for at least the purpose of substituting the unknown material of the core layer of Zhang with the glass material of Kim for the predictable result of providing an insulated mounting material on which the IC dies can be mounted (Kim [0030]) and for the further purpose of using the glass bridge die as part of a reconstituted wafer packaging process (Kim [0005]) that further produces thinner and smaller electronic packages (Kim [0005], [0026]) and reduced manufacturing costs (Kim [0026]). Furthermore, the ordinary artisan would have been motivated to use the electrically conductive interconnect to electrically connect the second redistribution layer to the first redistribution layer (Kim [0043], [0045] and Fig 1: 47 connects 34 to 28).
However, Zhang in view of Kim does not teach an antenna operatively coupled to at least one of the chiplets.
Kim, through another embodiment, teaches an electronic device (Fig. 4, [0072]: 200) having antenna ([0072]) operatively coupled to at least one of the components ([0072]: 204).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of another embodiment of Kim into the device of Zhang in view of Kim to couple an antenna to at least one of a plurality of chiplets in an electronic system at least comprising of a substrate having an organic material, a glass bridge die in the substrate and having an electrically conductive interconnect, and the said plurality of chiplets disposed on a surface of the substrate. The ordinary artisan would have been motivated to modify Zhang in the manner set forth above for at least the purpose of producing various devices such as IMD, ICD, IPG, insertable cardiac monitor, implantable diagnostic monitor, deep brain stimulator, implantable neurostimulator, injectable neurostimulator, implantable ventricular assist device, etc. that requires an antenna to be connected to one of the chiplets (Kim [0072]).
However, Zhang in view of Kim does not teach the glass bridge layer to be a glass bridge die.
Teh, in the same field of invention, teaches a glass bridge layer (114, see Fig. 2 and [0018] wherein 114 is a core layer of a bridge having at least one redistribution layer 116B/116A) to be a glass bridge die (see [0074]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Teh into the device of Zhang in view of Kim to have the glass bridge layer to be comprised of a glass bridge die. The ordinary artisan would have been motivated to modify Zhang in view of Kim in the manner set forth above for at least the purpose of providing various ways (Teh [0074]) of enabling a high-density interconnect element that electrically bridges at least two dies that can be further embedded in another substrate (Teh [0011]) for the further purpose of increasing device density and reducing manufacturing cost (Teh [0013]-[0015]).
Regarding claim 21, the system of claim 16, wherein the glass bridge die includes a uniform glass layer (Kim Fig. 1 shows 14 is not composed of multiple layers; hence, using BRI, it is a uniform glass layer).
Regarding claim 22, the system of claim 16 wherein the glass bridge die includes a through glass via (TGV) (Kim Fig. 1, [0043]: 47 is a TGV since it is a via inside the glass core 14) extending from a first surface (Kim Fig. 1: top surface of 14; see Drawings Objection) of the glass bridge to a second surface (Kim Fig. 1: bottom surface of 14; see Drawings Objection) of the glass bridge die.
Claim(s) 2-5, and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 20190304892 A1) in view of Kim (US 20200058567 A1) and Teh (US 20140159228 A1) as applied to claim 1 and/or claim 16 above, and further in view of Krol (US 20120192928 A1).
Regarding claim 2, Zhang in view of Kim and Teh teaches the electronic device of claim 1, but does not teach wherein the glass bridge die includes multiple glass layers bonded together.
Krol, in the same field of invention, teaches a device, wherein a glass package (Fig. 3, [0028]: 300) includes multiple glass layers (¶ [0030]-[0031]: 24 & 10 & 11) bonded together ([0031]-[0032]: 20).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Krol into the device of Zhang in view of Kim and Teh to include multiple glass layers bonded together in a glass bridge die in an electronic device at least comprising of a substrate having an organic material, the glass bridge die in the substrate having electrically conductive interconnect, a first integrated circuit die and a second integrated circuit die on a surface of the substrate. The ordinary artisan would have been motivated to modify Zhang in view of Kim and Teh in the manner set forth above for at least the purpose of minimizing or eliminating the bowing (Krol Fig 2A-2B, [0026]) resulting from the lamination when using specialty glasses while also improving the mechanical robustness of the electronic device (Krol [0007]).
Regarding claim 3, the electronic device of claim 2, wherein a first glass layer (Krol Fig. 3, [0031]: 24) of the multiple glass layers has a different coefficient of thermal expansion ([0032]: “CTE of the glass substrate layer may be different from the CTE of the protective glass layers”) than an other glass layer (Krol Fig. 3, [0030]: 10 or 11).
Regarding claim 4, the electronic device of claim 3, wherein the interconnect of the glass bridge die includes at least one conductive trace (Kim Fig. 1, [0043]: 47 is a TGV since it is a via inside the glass core 14; BRI: a via is a conductive trace since it conducts electricity between one end of the substrate to another end of the substrate) between the first glass layer and the other glass layer (Zhang in view of Kim and Krol teaches the via penetrating through the multiple glass layers).
Regarding claim 5, the electronic device of claim 4, wherein the interconnect of the glass bridge die includes a via (Kim Fig. 1, [0043]: 47 is a TGV since it is a via inside the glass core 14) extending from a surface (Kim Fig. 1: bottom surface of 14 or alternatively, bottom surface of 20; see Drawings Objections) of the glass bridge to the at least one conductive trace (Kim Fig. 1, [0040]: 46).
Regarding claim 17, Zhang in view of Kim teaches the system of claim 16, but does not teach wherein the glass bridge die includes multiple glass layers bonded together.
Krol, in the same field of invention, teaches a device, wherein a glass package (Fig. 3, [0028]: 300) includes multiple glass layers (¶ [0030]-[0031]: 24 & 10 & 11) bonded together ([0031]-[0032]: 20).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Krol into the device of Zhang in view of Kim to include multiple glass layers bonded together in a glass bridge die in an electronic system at least comprising of a substrate having an organic material, the glass bridge die in the substrate and having an electrically conductive interconnect, and a plurality of chiplets disposed on a surface of the substrate. The ordinary artisan would have been motivated to modify Zhang in the manner set forth above for at least the purpose of minimizing or eliminating the bowing (Krol Fig 2A-2B, [0026]) resulting from the lamination when using specialty glasses while also improving the mechanical robustness of the electronic device (Krol [0007]).
Regarding claim 18, the system of claim 17, wherein a first glass layer (Krol Fig. 3, [0031]: 24) of the multiple glass layers has a different coefficient of thermal expansion ([0032]: “CTE of the glass substrate layer may be different from the CTE of the protective glass layers”) than an other glass layer (Krol Fig. 3, [0030]: 10 or 11).
Regarding claim 19, the system of claim 18, wherein the interconnect of the glass bridge die includes at least one conductive trace (Kim Fig. 1, [0043]: 47 is a TGV since it is a via inside the glass core 14; BRI: a via is a conductive trace since it conducts electricity between one end of the substrate to another end of the substrate) between the first glass layer and the other glass layer (Zhang in view of Kim and Krol teaches the via penetrating through the multiple glass layers).
Regarding claim 20, the system of claim 19, wherein the interconnect of the glass bridge die includes a via (Kim Fig. 1, [0043]: 47 is a TGV since it is a via inside the glass core 14) extending from a surface (Kim Fig. 1: bottom surface of 14 or alternatively, bottom surface of 20; see Drawings Objections) of the glass bridge to the at least one conductive trace (Kim Fig. 1, [0040]: 46).
Claim(s) 11 and 14-15 is/are rejected under 35 U.S.C. 102 (a)(1) and (a)(2) as being unpatentable over Zhang (US 20190304892 A1) in further view of Kim (US 20200058567 A1).
Regarding claim 11, electronic device comprising:
an interconnect bridge substrate (Fig. 1, [0023]: 104 is a bridge substrate since it contains interconnect regions 116 to connect dies 102a and 102b), the bridge substrate comprising a core (Fig. 3, ¶ [0023]: 304);
at least one redistribution layer (Fig. 3, [0027], [0022]: 302; this is a dielectric layer containing interconnect wiring 308; hence it is a redistribution layer as evidenced by Gu (US 9368450 B1) Col. 4, Lns 24-49) on the core of the bridge substrate, the layer including an organic material ([0027]: epoxy-based resin; epoxies are known in the art as organic materials, i.e., carbon linked with hydrogen, oxygen, or nitrogen), the layer including an electrically conductive trace ([0027]: 308) having a first end (top left end of 308 under top left 326) and a second end (top right end of 308 under top right 326);
a first integrated circuit (IC) die (Fig. 1, [0022]: 102da), the first IC die electrically coupled (see [0022]: 108 is a die bond pad that connects 102a to interconnects) to the first end of the trace (as explained in Fig. 3, [0035]: 326 is a die bond pad, i.e., second surface finish; also shown as 108 in Fig. 1 and [0022]; Fig. 3 also shows 326 found at the top left end of 308); and
a second IC die (Fig. 1, [0022]: 102b), the second IC die electrically coupled (see [0022]: 108 is a die bond pad that connects 102b to interconnects) to the second end of the trace (as explained in Fig. 3, [0035]: 326 is a die bond pad, i.e., second surface finish; also shown as 108 in Fig. 1 and [0022]; Fig. 3 also shows 326 found at the top right end of 308).
Zhang further teaches the substrate to be made of glass (par. [0023]). However, Zhang does not explicitly teach the interconnect bridge substrate comprising a glass core layer.
Kim, in the same field of invention, teaches an interconnect bridge substrate (12) having the glass core layer (14; par. [0030]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Kim into the device of Zhang to have the core layer of an interconnect bridge substrate to be comprised of glass. The ordinary artisan would have been motivated to modify Kim in the manner set forth above for at least the purpose of improving the dielectric properties of the substrate for the further purpose of improving warpage resistance and wiring density (Kim [0027]).
Regarding claim 14, the electronic device of claim 11,
wherein the electrically conductive trace comprises a first electrically conductive trace (Fig. 3, [0027]: 308 as found in bottom RDL 306),
the electronic device further comprising a second electrically conductive trace (Fig. 3, [0027]: 308 found on the top RDL 302) in or on the bridge substrate, the second trace having a first end (top left of 308 labelled as 326; [0035]: 326 is a second surface finish) and a second end (top right of 308 labelled as 326; [0035]: 326 is a second surface finish),
wherein the first IC die is electrically coupled to the first end of the second trace (Fig. 1 shows 102a connected to top left 108; [0022] explains that 108 has the second surface finish; see 112b rejection ), and wherein the second IC die is electrically coupled to the second end of the second trace (Fig. 1 shows 102b connected to top right 108; [0022] explains that 108 has the second surface finish; see 112b rejection).
Regarding claim 15, Zhang the electronic device of claim 11, further comprising a vertical interconnect (Fig. 3: not labelled but shown within core layer 304, see [0023], [0027]) extending from a first surface (top surface of 304) of the core to a second surface (bottom surface of 304) of the core. However, Zhang did not explicitly teach the vertical interconnect to be a through glass via (TGV).
Kim, in the same field of invention, teaches the glass core (14) further comprises a through glass via (TGV) (Fig. 1, [0043], [0030], [0062]: 47 extends around glass core 14; hence, using BRI, 47 is a through glass via ) extending from a first surface (top surface of 14) of the glass core to a second surface (bottom surface of 14) of the glass core.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Kim into the device of Zhang to add a through glass via (TGV) extending from a first surface of a glass core to a second surface of a glass core in an electronic device at least comprising of an interconnect bridge substrate the bridge substrate comprising the glass core, at least one organic layer on the bridge substrate having electrically conductive trace that has a first end and a second end, a first IC die electrically coupled to the first end of the trace, a second IC die electrically coupled to the second end of the trace. The ordinary artisan would have been motivated to modify Zhang in the manner set forth above for at least the purpose of using the TGV to electrically connect the pads (Kim Fig. 1, [0028]: 36) from the bottom end of the substrate to a plurality of chips (Kim Fig. 1, [0047]: 30a and 30b) on the other end of the substrate and for the further purpose of producing thinner and smaller electronic packages (Kim [0005]) with reduced current density and power loss (Kim [0026]).
Claim(s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 20190304892 A1) in view of Kim (US 20200058567 A1) as applied to claim 11 above, and further in view of Krol (US 20120192928 A1).
Regarding claim 12, Zhang in view of Kim teaches the electronic device of claim 11, but does not teach wherein the glass core includes two glass layers.
Krol, in the same field of invention, teaches a device, wherein a glass package (Fig. 3, [0028]: 300) includes two layer glass layers (BRI: ¶ [0030]-[0031]: 24 & 10 or 24 &11 or 10 & 11). Hence Zhang in view of Kim and Krol teaches the glass core of Zhang to include two glass layers.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Krol into the device of Zhang in view of Kim to include two glass layers in an interconnect bridge substrate in an electronic device at least comprising of the interconnect bridge substrate comprising of glass; at least one layer on the bridge substrate, with the layer including an organic material and with the layer including an electrically conductive trace having a first end and second end; a first IC die coupled to the first end of the trace; and a second IC die coupled to the second end of the trace. The ordinary artisan would have been motivated to modify Zhang in view of Kim in the manner set forth above for at least the purpose of minimizing or eliminating the bowing (Krol Fig 2A-2B, [0026]) resulting from the lamination when using specialty glasses while also improving the mechanical robustness of the electronic device (Krol [0007]).
Regarding claim 13, the electronic device of claim 12, wherein the electrically conductive trace (Kim Fig. 1, [0043]: 47 is a TGV since it is a via inside the glass core 14; BRI: a via is a conductive trace since it conducts electricity between one end of the substrate to another end of the substrate) is located between the glass layers (Zhang in view of Kim and Krol teaches the via penetrating through the two glass layers).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899