DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant argues that the Examiner has not shown how Norihiko (JP2011114137A) resolves the alleged deficiencies of Takaku (US20180076146A1) and therefore has failed to establish a prima facie case of obviousness. This argument is not persuasive.
Takaku disclosed a semiconductor device employing ribbon bonding for electrical connection. Norihiko recognizes that thermal cycling may generate peeling-direction forces at a ribbon bond joint and teaches providing a deformation portion to reduce bending rigidity and improve joint reliability. A person having ordinary skill in the art would have reasonably understood that incorporating the bonding configuration of Norihiko into Takaku would predictably improve bonding reliability under thermal stress conditions. Accordingly, the Examiner maintains the rejection under 35 U.S.C. 103.
Regarding the applicant’s arguments on pages 11-12, Norihiko (JP2011114137A) teaches the respective ones of the plurality of vertical ribbon bond connections include: a first portion with a width dimension greater than a thickness dimension and oriented such that the width dimension lies within a plane that is orthogonal to a major plane of the substrate (Fig. 1(b), twisting unit 1D, in the middle portion 1W, are those twisted θD=90° around the longitudinal direction of the ribbon bond 1, end portion 1jA, 1jB surface of semiconductor element 3s and the circuit board in a portion 5. Twisting unit 1D has greater width dimension than a thickness dimension as shown in Fig. 1(c)).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, 23-26, and 30-32 are rejected under 35 U.S.C. 103 as being unpatentable over Takaku (US20180076146A1), and further in view of Norihiko (JP2011114137A).
Regarding claim 1, Takaku teaches
an electronic device (Para [0029], semiconductor device), comprising:
a die coupled to a substrate (Para [0031], semiconductor chip 4 is mounted on the substrate 1);
one or more wire bond connections from the die to the substrate (Para [0032], bonding wire 5 is connected to the substrate 1 and to semiconductor chip 4); and
a plurality of vertical ribbon bond connections from the die to the substrate (Para [0022] and Fig. 8A, shielding ribbon wire 11 is connected to the substrate 1 and to semiconductor chip 4).
But Takaku fails to teach the respective ones of the plurality of vertical ribbon bond connections include: a first portion with a width dimension greater than a thickness dimension and oriented such that the width dimension lies within a plane that is orthogonal to a major plane of the substrate; an end portion attached to the substrate; and a twist portion that transitions the vertical ribbon bond connection between the end portion and the first portion.
However, Norihiko teaches the respective ones of the plurality of vertical ribbon bond connections include:
a first portion with a width dimension greater than a thickness dimension and oriented such that the width dimension lies within a plane that is orthogonal to a major plane of the substrate (Fig. 1(b), twisting unit 1D, in the middle portion 1W, are those twisted θD = 90° around the longitudinal direction of the ribbon bond 1, end portion 1jA, 1jB surface of semiconductor element 3s and the circuit board in a portion 5. Twisting unit 1D has greater width dimension than a thickness dimension as shown in Fig. 1(c));
an end portion attached to the substrate (end portion 1jA); and
a twist portion that transitions the vertical ribbon bond connection between the end portion and the first portion (loop portion 1W).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the invention, to modify a ribbon bond structure of Takaku (US20180076146A1) to include the deformation portion taught by Norihiko in order to improve bonding reliability under thermal stress conditions. Such modification represents a predictable application of a known ribbon bonding technique to improve device reliability, as described in Fig. 1 of Norihiko.
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Regarding claim 2, Takaku in view of Norihiko teaches the electronic device of claim 1, wherein the respective ones of the plurality of vertical ribbon bond connections are coupled to a ground voltage when the electronic device is in operation (Para [0035], shielding wire 11 is electrically grounded via ground layer 1a).
Regarding claim 4, Takaku in view of Norihiko teaches the electronic device of claim 1, wherein the respective ones of the plurality of vertical ribbon bond connections are interspersed within a row of wire bond connections from the die to the substrate (Para [0032] and Fig. 8B, bonding wire 5 and shielding wire 11 are connected to the substrate 1 and to the semiconductor chips 4 on the side of the first or second lateral face S1 or S2).
Regarding claim 5, Takaku in view of Norihiko teaches the electronic device of claim 1, wherein the respective ones of the plurality of vertical ribbon bond connections are included alternating between wires that are to carry data signals within a row of wire bond connections from the die to the substrate (Para [0031] and Fig. 8B, shielding wire 11 is positioned among the bonding wire 5 in the same plane, thereby alternating between signal-carrying bonding wires).
Regarding claim 23, Takaku teaches an apparatus (Para [0029], semiconductor device), comprising:
a die coupled to a substrate (Para [0031], semiconductor chip 4 is mounted on the substrate 1);
one or more wire bond connections from the die to the substrate (Para [0032], bonding wire 5 is connected to the substrate 1 and to semiconductor chip 4); and
a plurality of vertical ribbon bond connections from the die to the substrate (Para [0022] and Fig. 8A, shielding ribbon wire 11 is connected to the substrate 1 and to semiconductor chip 4).
But Takaku fails to teach the plurality of vertical ribbon bond connections including respective vertical ribbon bond connections, wherein a respective vertical ribbon bond connection includes: an intermediate portion with a width dimension greater than a thickness dimension and oriented such that the width dimension lies within a plane that is orthogonal to a major plane of the substrate; a first end portion attached to the substrate; a second end portion attached to the die; a first twist that transitions the respective vertical ribbon bond connection between the first end portion and the intermediate portion; and a second twist between the intermediate portion and the second end portion.
However, Norihiko teaches the plurality of vertical ribbon bond connections including respective vertical ribbon bond connections, wherein a respective vertical ribbon bond connection includes:
an intermediate portion with a width dimension greater than a thickness dimension and oriented such that the width dimension lies within a plane that is orthogonal to a major plane of the substrate (Fig. 1(b), twisting unit 1D, in the middle portion 1W, are those twisted θD = 90° around the longitudinal direction of the ribbon bond 1, end portion 1jA, 1jB surface of semiconductor element 3s and the circuit board in a portion 5. Twisting unit 1D has greater width dimension than a thickness dimension as shown in Fig. 1(c));
a first end portion attached to the substrate (end portion 1jB);
a second end portion attached to the die (end portion 1jA);
a first twist that transitions the respective vertical ribbon bond connection between the first end portion and the intermediate portion (loop portion 1W); and
a second twist between the intermediate portion and the second end portion (loop portion 1W).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the invention, to modify a ribbon bond structure of Takaku (US20180076146A1) to include the deformation portion taught by Norihiko in order to improve bonding reliability under thermal stress conditions. Such modification represents a predictable application of a known ribbon bonding technique to improve device reliability, as described in Fig. 1 of Norihiko.
Regarding claim 24, Takaku in view of Norihiko teaches the apparatus of claim 23, wherein the respective vertical ribbon bond connection is configured to be electrically coupled to ground in operation (Para [0035], shielding wire 11 is electrically grounded via ground layer 1a).
Regarding claim 25, Takaku in view of Norihiko teaches the apparatus of claim 23, wherein the respective vertical ribbon bond connections are interspersed within a row of wire bond connections from the die to the substrate (Para [0032] and Fig. 8B, bonding wire 5 and shielding wire 11 are connected to the substrate 1 and to the semiconductor chips 4 on the side of the first or second lateral face S1 or S2).
Regarding claim 26, Takaku in view of Norihiko teaches the apparatus of claim 23, wherein the respective vertical ribbon bond connections are included alternating between wires that are to carry data signals within a row of wire bond connections from the die to the substrate (Para [0031] and Fig. 8B, shielding wire 11 is positioned among the bonding wire 5 in the same plane, thereby alternating between signal-carrying bonding wires).
Regarding claim 30, Takaku in view of Norihiko teaches the apparatus of claim 23, wherein the first end portion has a second width dimension that is generally parallel to the major plane of the substrate (Fig. 1(c), The bonded end portions 1jA and 1jB are formed by bonding similar to ordinary ribbon bonding, and are parallel to the xy plane as well as the electrode surface 3 s of the semiconductor element 3 and the surface of the terminal 8).
Regarding claim 31, Takaku in view of Norihiko teaches the apparatus of claim 23, wherein the intermediate portion of the respective vertical ribbon bond connection is positioned laterally between adjacent wire bond connections (Para [0031] and Fig. 8B, shielding wire 11 is positioned among the bonding wire 5 in the same plane, thereby alternating between signal-carrying bonding wire).
Regarding claim 32, Takaku in view of Norihiko teaches the electronic device of claim 1, wherein the end portion has a second width dimension that is generally parallel to the major plane of the substrate (Fig. 1(c), the bonded end portions 1jA and 1jB are formed by bonding similar to ordinary ribbon bonding, and are parallel to the xy plane as well as the electrode surface 3s of the semiconductor element 3 and the surface of the terminal 8).
Claims 6-8 and 27-29 are rejected under 35 U.S.C. 103 as being unpatentable over Takaku (US20180076146A1) as applied to claims 1 and 23 above, and further in view of Camacho (US20100140763A1).
Regarding claims 6 and 27, Takaku in view of Norihiko teaches electronic device of claims 1 and 23 respectively, but does not specify the die includes a memory die.
However, Comacho teaches the die includes a memory die (Para [0029 & 0035], the stack integrated circuit 106 and 118 can represent a memory chip).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the invention, to modify a semiconductor device of Takaku (US20180076146A1) by further integrating an IC packaging system that employs an alternative memory stacked structure as disclosed by Camacho (US20100140763A1). The combination of these familiar elements can improve the reliability, as described in paragraph [0005] of Camacho.
Regarding claims 7 and 28, Takaku in view of Norihiko teaches electronic device of claims 1 and 23 respectively, but does not specify the die is a memory die included within a stack of memory dies.
However, Comacho teaches the memory die included within a stack of memory dies (Para [0029 & 0035], the stack integrated circuit 106 and 118 can represent a memory chip).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the invention, to modify a semiconductor device of Takaku (US20180076146A1) by further integrating an IC packaging system that employs an alternative memory stacked structure as disclosed by Camacho (US20100140763A1). The combination of these familiar elements can improve the reliability, as described in paragraph [0005] of Camacho.
Regarding claims 8 and 29, Takaku in view of Norihiko teaches the electronic device of claims 7 and 23 respectively, wherein vertical ribbon bond connections are included alternating between wires that are to carry data signals within multiple rows of wire bond connections between different level dies in the stack of memory dies and the substrate.
However, Comacho the vertical ribbon bond connections are included alternating between wires to carry data signals within multiple rows of wire bond connections between different level dies in the stack of memory dies and the substrate (Para [0042], interconnects 130, such as bond wires or ribbon bon wires, functioning as I/O signals between stacked dies and the base die/substrate).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAHAE KIM whose telephone number is (571)270-1844. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at (571) 271-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JAHAE KIM/ Examiner, Art Unit 2897