DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5, and 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pagaila et al. (U.S 2011/0024888 A1) (of record).
As to claim 1, Pagaila et al. disclose in Fig. 10 an electronic system comprising: a printed circuit board (comprising “substrate material” 122, “insulating layers” 124, 126, “conductive layers” 128, 130) (Fig. 10, para. [0040]-[0042]); a substrate (“semiconductor die”/“component”/“interposer” 274) having a top side (top surface) and a bottom side (bottom side), at least a portion of the bottom side (bottom surface) coupled to the printed circuit board (comprising “substrate material” 122, “insulating layers” 124, 126, “conductive layers” 128, 130) (Fig. 10, para. [0066]-[0068]); at least one memory unit (“semiconductor die”/“component” 286 can be “memory” circuit, para. [0069]) connected to the bottom side (bottom surface) of the substrate (“semiconductor die”/“component”/“interposer” 274) (Fig. 10, para. [0069]); at least one processor (“semiconductor die”/“component” 296 can be “signal processing circuit”, para. [0071]) connected to the top side (top surface) of the substrate (“semiconductor die”/“component”/“interposer” 274) (Fig. 10, para. [0071]); and wherein the at least one memory unit (“semiconductor die”/“component” 286) is connected with the processor (“semiconductor die”/“component” 296) through the substrate (“semiconductor die”/“component”/“interposer” 274) (Fig. 10, para. [0067], [0069], [0071]).
As to claim 5, as applied to claim 1 above, Pagaila et al. disclose in Fig. 10 all claimed limitations including the electronic system further comprising: a cavity (see a cavity having a die 286, Fig. 10) in the printed circuit board (comprising “substrate material” 122, “insulating layers” 124, 126, “conductive layers” 128, 130) (see Fig. 10); the at least one memory unit (“semiconductor die”/“component” 286) is within the cavity (see a cavity having a die 286, Fig. 10) in the printed circuit board (comprising “substrate material” 122, “insulating layers” 124, 126, “conductive layers” 128, 130) (see Fig. 10, para. [0069]); and the at least one memory unit (“semiconductor die”/“component” 286) is connected to the bottom side (bottom surface) of the substrate (“semiconductor die”/“component”/“interposer” 274) with solder (“bump” 288) (Fig. 10, para. [0069]).
As to claim 7, as applied to claim 1 above, Pagaila et al. disclose in Fig. 10 all claimed limitations including the limitation: wherein the at least one memory unit (“semiconductor die”/“component” 286) is a packaged memory (see Fig. 10, para. [0069]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pagaila et al. (U.S 2011/0024888 A1) (of record) in view of Li (U.S 2012/0187578 A1) (of record).
As to claim 3, as applied to claim 1 above, Pagaila et al. disclose in Fig. 10 all claimed limitations except for the limitation: wherein the printed circuit board is coupled to the substrate with solder.
Li discloses in Fig. 1 an electronic package/system comprising: the printed circuit board (180) is coupled to the substrate (102) with solder (“solder pad array” 124) (see Fig. 1, para. [0012]-[0013]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify reference of Pagaila et al. by having a printed circuit board coupled to the substrate with solder, as taught by Li, in order to provide high-density connections, reduce component damage from heat, and improve thermal dissipation, so as to improve high-performance electronic package/system.
As to claim 6, as applied to claim 1 above, Pagaila et al. disclose in Fig. 10 all claimed limitations except for the limitation: wherein a heat spreader is disposed on the top side of the substrate and covering the processor.
Li discloses in Fig. 1 an electronic package/system comprising: a heat spreader (“air-cooled heatsink” 168) is disposed on the top side (top surface) of the substrate (“multi-layered substrate” 102) and covering the processor (“logic circuitry” 160 can be a “host processor”, para. [0029]) (Fig. 1, para. [0011]-[0012], [0029], [0030]). Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify reference of Pagaila et al. by providing a heat spreader which is disposed on the top side of the substrate and covering the processor, as taught by Li, in order to release heat from the top of the electronic package/system, that may toward the printed circuit board (PCB) (see para. [0030] in Li).
Response to Arguments
Applicant's arguments filed on 11/28/2025 have been fully considered but they are not persuasive.
Applicant argued that the substrate 122 in Pagaila is not a printed circuit board (PCB).
In response, Applicant’s argument is respectfully traversed because one skilled in the art would have known that Fig. 10 of Pagaila clearly discloses that a package substrate (comprising “substrate material” 122, “insulating layers” 124, 126, and “conductive layers” 128, 130) can be considered a type of a printed circuit board (PCB) because it has at least electrical traces or electrical connections (“conductive layers” 128, 130). Therefore, Applicant’s argument is deemed to be unpersuasive.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817 March 7, 2026