DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/13/2026 has been entered.
Claim Objections
Claims 25-27 are objected to because of the following informalities:
Claim 25 is not clear because it recites the limitation “wherein the memory unit comprises packaged memory” (emphasis added). For the purpose of examination, the Examiner assumes the above limitation of “wherein the memory unit comprises packaged memory” (as recited in claim 25) is:
“wherein the memory unit comprises a packaged memory” (emphasis added).
Claim 26 is not clear because it recites the limitation “wherein the memory unit comprises stacked memory” (emphasis added). For the purpose of examination, the Examiner assumes the above limitation of “wherein the memory unit comprises stacked memory” (as recited in claim 26) is:
“wherein the memory unit comprises a stacked memory” (emphasis added).
Claim 27 is not clear because it recites the limitation “wherein the memory unit comprises exposed silicon memory” (emphasis added). For the purpose of examination, the Examiner assumes the above limitation of “wherein the memory unit comprises exposed silicon memory” (as recited in claim 27) is:
“wherein an memory unit comprises an exposed silicon memory” (emphasis added).
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 22-26, and 29-35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S 2022/0068814 A1) in view of JUNG et al. (U.S 2017/0179078 A1).
As to claims 22, 30, 31, 32, and 34, Kim et al. disclose in Fig. 29 an electronic system, comprising: a printed circuit board (PCB) (comprising “core substrate” 100 & “redistribution wiring layer” 300) (Fig. 29, para. [0027]-[0028]), wherein the PCB (comprising “core substrate” 100 & “redistribution wiring layer” 300) comprises a cavity (106) (Fig. 29, para. [0027], [0029]); a memory unit (“semiconductor chip” 200 may be “a memory chip” disposed “in the cavity 106 of the core substrate 100”, para. [0029]) within the cavity (106) of the PCB (comprising “core substrate” 100 & “redistribution wiring layer” 300) (Fig. 29, para. [0027], [0029]); a substrate (“upper insulation layer” 350) extending across the cavity (106) of the PCB (comprising “core substrate” 100 & “redistribution wiring layer” 300), the substrate (“upper insulation layer” 350) comprising conductive wires (see conductive wires/wirings in layer 350) within resin (“the upper insulation layer 350 may include an insulation material such as epoxy resin”, para. [0074]) and having a top side (top surface) and a bottom side (bottom surface) (Fig. 29, para. [0073]-[0074]), wherein the PCB (comprising “core substrate” 100 & “redistribution wiring layer” 300) and the memory unit (“semiconductor chip” 200) are electrically coupled to the bottom side (bottom surface) of the substrate (“upper insulation layer” 350) (Fig. 29, para. [0029], [0086], [0104], [0177]); and a semiconductor chip (620/630) electrically coupled to the top side (top surface) of the substrate (“upper insulation layer” 350) (Fig. 29, para. [0176], [0178]); wherein the memory unit (“semiconductor chip” 200) and the semiconductor chip (620/630) are electrically coupled to each other through the substrate (“upper insulation layer” 350) (Fig. 29, para. [0177]);
wherein the memory unit (200) and the semiconductor chip (620/630) are disposed on opposing sides of the substrate (“upper insulation layer” 350) (see Fig. 29);
wherein the memory unit (200) is positioned below the semiconductor chip (620/630) (see Fig. 29);
wherein at least a portion of the semiconductor chip (620/630) overlaps the cavity (106) in plan view (see Fig. 29); and
the electronic system (Fig. 29) further comprising: a plurality of semiconductor packages (comprising chip 200, layers 140, 350, 610, chip 620; and chip 630, “molding member” 642) attached and electrically coupled to the PCB (comprising “core substrate” 100 & “redistribution wiring layer” 300), wherein the semiconductor packages (comprising chip 200, layers 140, 350, 610, chip 620; and “chip” 630, “molding member” 642) include a first semiconductor package (comprising chip 200, layers 140, 350, 610, and chip 620) and a second semiconductor package (comprising “chip” 630, and “molding member” 642), wherein the first semiconductor package (comprising chip 200, layers 140, 350, 610, and chip 620) comprises the substrate (“upper insulation layer” 350), the memory unit (200), and the semiconductor chip (620/630) (see Fig. 29, [0177]).
Kim et al. are silent to disclose a semiconductor chip is a processor.
JUNG et al. disclose in Fig. 1 an electronic system comprising: a PCB (“package substrate” 500) (Fig. 1, para. [0033]-[0034]), a substrate (“interconnection structure layer” 100) (Fig. 1, para. [0030]-[0031]), and a processor (“first die” 200 may be “a microprocessor” or “a high performance central processing unit”, para. [0032]) electrically coupled to the top side (top surface) of the substrate (“interconnection structure layer” 100) (Fig. 1, para. [0030]-[0032]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify Kim’s structure by integrating a processor, or to replace Kim’s semiconductor chip with a processor as taught by JUNG et al., in order to provide localized data processing, instruction execution, real-time signal analysis, and power management functionalities in the packaged device.
As to claims 23 and 24, as applied to claim 22 above, Kim et al. disclose in Fig. 29 all claimed limitations including the limitation: wherein the PCB (comprising “core substrate” 100 & “redistribution wiring layer” 300) is electrically coupled to the bottom side (bottom surface) of the substrate (“upper insulation layer” 350), and wherein the memory unit (200) is electrically coupled to the bottom side (bottom surface) of the substrate (“upper insulation layer” 350) (Fig. 29).
Kim et al. do not disclose the PCB is electrically coupled to the bottom side of the substrate by solder balls, and the memory unit is electrically coupled to the bottom side of the substrate by solder balls.
JUNG et al. disclose in Fig. 1 an electronic system comprising: a PCB (“package substrate” 500) is electrically coupled to the bottom side (bottom surface) of the substrate (“interconnection structure layer” 100) by solder balls (“ first connectors” 330) (Fig. 1, para. [0033]-[0034], [0037]), and the memory unit (each “second die” 400 includes a memory device, para. [0032]) is electrically coupled to the bottom side (bottom surface) of the substrate (100) by solder balls (“second connectors” 320) (Fig. 1, para. [0039]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify Kim’s structure by electrically coupling a PCB and a memory unit to the bottom side of the substrate using solder balls as taught by JUNG et al., in order to facilitate simplified component bonding, minimize manufacturing steps, and enhance electrical connectivity through self-aligned interconnects.
As to claim 25, as applied to claim 22 above, Kim et al. and JUNG et al. disclose all claimed limitations including the limitation: wherein the memory unit (“semiconductor chip” 200) comprises a packaged memory (see Fig. 29 in Kim et al., a memory unit 200 is included in a package).
As to claim 26, as applied to claim 22 above, Kim et al. and JUNG et al. disclose all claimed limitations including the limitation: wherein the memory unit (“semiconductor chip” 200) comprises a stacked memory (see Fig. 29 in Kim et al., the memory unit 200 is capable of being stacked on a PCB or other element).
As to claim 29, as applied to claim 22 above, Kim et al. and JUNG et al. disclose all claimed limitations including the limitation: wherein the PCB (comprising “core substrate” 100 & “redistribution wiring layer” 300) has a top side (top surface) facing the substrate (“upper insulation layer” 350), wherein the memory unit (200) does not extend above the top side of the PCB (comprising “core substrate” 100 & “redistribution wiring layer” 300) such that the memory unit (200) does not add height to the electronic system (see Fig. 29 in Kim et al.).
As to claim 33, as applied to claim 22 above, Kim et al. and JUNG et al. disclose all claimed limitations including the limitation: wherein the PCB (comprising “core substrate” 100 & “redistribution wiring layer” 300) is configured to support a plurality of semiconductor packages (comprising chip 200, layers 140, 350, 610, chip 620; and “chip” 630, “molding member” 642) (see Fig. 29 in Kim et al.).
As to claim 35, as applied to claim 22 above, Kim et al. and JUNG et al. disclose all claimed limitations including the limitation: wherein the PCB (comprising “core substrate” 100 & “redistribution wiring layer” 300) is a system-level PCB (Fig. 29 in Kim et al.).
Claim(s) 28 and 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S 2022/0068814 A1) in view of JUNG et al. (U.S 2017/0179078 A1) as applied to claim 22 above, and further in view of Li (U.S 2012/0187578 A1).
As to claim 28, as applied to claim 22 above, Kim et al. and JUNG et al. disclose all claimed limitations except for the electronic system further comprising a heat spreader disposed over the processor.
Li discloses in Fig. 1 an electronic system/package comprising a heat spreader (comprising “metallic hollowed bracket” 164 & “heatsink” 168) disposed over the processor (160) (Fig. 1, para. [0030], [0032]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify Kim’s structure (in view of JUNG et al.) by having a heat spreader disposed over the processor as taught by Li, in order to dissipate heat from the processor and/or the system, thereby improving overall device reliability.
As to claim 36, as applied to claim 22 above, Kim et al. and JUNG et al. disclose all claimed limitations including the limitation: wherein the PCB (comprising “core substrate” 100 & “redistribution wiring layer” 300) has a top side (top surface) and a bottom side (bottom surface), wherein the top side (top surface) of the PCB (comprising “core substrate” 100 & “redistribution wiring layer” 300) is electrically coupled to the substrate (“upper insulation layer” 350) (Fig. 29, para. [0028]).
Kim et al. in view of JUNG et al. do not disclose the bottom side of the PCB is not configured to be electrically coupled to another electronic component.
Li discloses in Fig. 1 an electronic system/package comprising: a PCB (180), wherein the bottom side (bottom surface) of the PCB (180) is not configured to be electrically coupled to another electronic component (see Fig. 1, para. [0012]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify Kim’s structure in view of JUNG et al. by providing a PCB and its bottom side is not configured to be electrically coupled to another electronic component as taught by Li, in order to implement a single-sided wiring PCB within the package, which advantageously simplifies trace routing, reduces overall manufacturing costs, and minimizes the thickness of the package device.
Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S 2022/0068814 A1) in view of JUNG et al. (U.S 2017/0179078 A1) as applied to claim 22 above, and further in view of MUTHUR SRINATH et al. (U.S 2019/0043772 A1).
As to claim 27, as applied to claim 22 above, Kim et al. and JUNG et al. disclose all claimed limitations except for the limitation: wherein the memory unit comprises an exposed silicon memory.
MUTHUR SRINATH et al. disclose in Fig. 1B an electronic package comprising: an memory unit (120) comprises an exposed silicon memory (“functional silicon die”, para. [0039]-[0040]) (Fig. 1B, para. [0039]-[0040]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify Kim’s structure in view of JUNG et al. by having a memory unit that comprises an exposed silicon memory as taught by MUTHUR SRINATH et al., in order to provide an unencapsulated thermal path that drastically minimizes thermal resistance. A person of ordinary skill in the art would have been motivated to implement this configuration to facilitate direct-contact cooling and reduce the overall package profile, thereby preventing thermal throttling and enhancing the operational reliability of the memory unit.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Proschwitz et al. (U.S 2023/0300975 A1), Yu et al. (U.S 2015/0206866 A1), KIM et al. (U.S 2022/0077007 A1), and Lin (U.S 2015/0001708 A1).
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817
July 24, 2026
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