YDETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/3/2026 has been entered.
Response to Arguments
Claim Rejections – 35 USC 101
Applicant's arguments filed 6/3/2026 have been fully considered but they are not persuasive.
Applicant asserts that, as in Diehr, the claims do not seek to patent a mathematical formula; they recite a specific process and specific hardware architecture for performing Montgomery multiplication with reduced computational interdependencies.
Examiner respectfully disagrees. The claims of Diehr include steps that are additional elements relating to the operating of a rubber molding press. Applicant’s claims are more similar to the claims in Gottschalk v. Benson than in Diehr. Additionally, the Examiner amends “mathematical process” in the rejections to one of the abstract idea groupings listed in 2106.04(a)(2)(I) for clarity.
Applicant asserts the claims are integrated into a practical application because the claims recite a particular technical solution to the technical problem of computational interdependencies in Montgomery multiplication hardware, wherein the ordered combination recited in the claims reflects the particular solution for reducing computational interdependencies.
Examiner respectfully disagrees. Applicant’s specification [0011] discloses “interdependencies caused by addition of carries”, which means reducing interdependencies in Montgomery multiplication is a mathematical problem because the interdependencies are a result of mathematical calculation. Thus, a Montgomery multiplication method that removes interdependencies is a mathematical solution to a mathematical problem. Reducing processing cycles is a consequence of applying the Montgomery multiplication method removing interdependencies rather than a result of a technical solution. In other words, reducing processing cycles is a result of using the mathematical calculation of the Montgomery multiplication method then applying it onto hardware instead of being a result of the hardware itself.
Applicant asserts the specification identifies concrete technical improvements that are reflected in the claims and are directed to how the processing device itself operates and not mere consequences of performing mathematical operations wherein the amended claims now expressly incorporate the n+4 sets of concurrent multiplication operations limitations which directly links the claimed subject matter to the disclosed technical improvements.
Examiner respectfully disagrees. As discussed above, the Montgomery multiplication limitations show a mathematical solution to a mathematical problem. Furthermore, the Examiner notes “the n+4 sets of concurrent multiplication operations” (emphasis added) as recited are further limiting the mathematical concepts and do not reflect limitations of the device itself.
Applicant asserts paragraph [0025] and arguments of general-purpose GPU parallelism with the specific claimed architecture are not dispositive of patentability of the claims, which are not directed to pure software operations.
Examiner respectfully disagrees. Applicant’s paragraph [0020] discloses “the accelerator circuit may be capable of performing other operations, in addition to the Montgomery multiplication”. Paragraph [0020] further discloses “accelerator circuit 130 (accelerator co-processor, accelerator engine, etc.)” (emphasis added). These passages guide the interpretation of the scope of the “accelerator circuit” recited in the claims. Hence, it is understood that the scope of an accelerator circuit includes operations in addition to Montgomery multiplication and thus includes circuits that are not exclusively performing Montgomery multiplication. Furthermore, it is known that GPUs are commonplace as modern coprocessors (Wikipedia page for coprocessors: section Modern coprocessors), which include Nvidia GPUs (Wikipedia: “In 2008, Khronos Group released the OpenCL with the aim to support general-purpose CPUs, ATI/AMD and Nvidia GPUs (and other accelerators) with a single common language for compute kernels.”). Applicant’s paragraph [0025] further discloses the example operations may be implemented by a combination of CPU and accelerator circuit, further evidence of the scope of the accelerator circuit including being a coprocessor. Therefore, the scope of the currently recited “accelerator circuit” has not fully excluded a GPU functioning as a coprocessor to the CPU to perform Montgomery multiplication.
Applicant asserts even though an operation can be implemented in software, it does not mean that a more efficient hardware implementation cannot constitute an improvement to the functioning of a computer, nor does the existence of processors capable of parallel processing automatically render abstract any specific improvements made to how such computations are structured and performed.
Examiner respectfully disagrees. The judicial exception alone cannot provide the improvement. See MPEP 2106.05(a). The analysis for eligibility of software is to “look at whether the added elements integrate the exception into a practical application or provide significantly more than the judicial exception.” See MPEP 2106.05(b)(I). However, the currently amended claims do not have such additional elements even when viewing the claims as a whole.
Applicant asserts as the claims do not recite generic parallel processing, but a specific ordered combination which are further specified that the Montgomery multiplication product is obtained using exactly n+4 sets of concurrent multiplication operations – a concrete numerical constraint that reflects the specific architecture that reduces computational interdependencies in a way a general-purpose GPU does not.
Examiner respectfully disagrees. Applicant’s assertion of the n+4 sets of concurrent multiplication operations as a concrete numerical constraint furthers the rationale that the recitation of the accelerator circuit is the equivalent of reciting “apply it” to the judicial exception because the n+4 sets of concurrent multiplication operations mathematically limits the mathematical concepts and does not reflect a specific architecture, particularly when the architecture is merely recited at a high level of generality as merely “performed by the accelerator circuit”.
Applicant asserts the Examiner has done what Desjardins warns against by dismissing the specific multiplication circuit architecture as generic because GPUs also have parallel cores, without adequately considering whether the claimed combination confers to a technological improvement.
Examiner respectfully disagrees. The Examiner applied the Alice/Mayo test, and further explanations for the rationale of the analysis are discussed in the other paragraphs of this section.
Applicant asserts the mathematical operations of Montgomery multiplication are integrated into a specific hardware architecture with parallel multiplication circuits, structured iterative stages, and accumulator-based quotient determination that sufficiently limits the use of the mathematical concepts to the practical application of efficient cryptographic computation with reduced interdependencies.
Examiner respectfully disagrees. Applicant’s current claims are not similar to USPTO Subject Matter Eligibility Example 41 because the claim in Example 41 shows a combination of additional elements “receiving the plaintext word signal at the first computer terminal, transforming the plaintext word signal to one or message block word signals MA, and transmitting the encoded ciphertext word signal CA to the second computer terminal over a communication channel” in the method for establishing cryptographic communications, such that the method integrates the mathematical concepts into a practical application. Applicant’s claims do not recite limitations that show the Montgomery multiplication results used in a practical application. Furthermore, as discussed above, the “accelerator circuit” is recited at a high level of generality that is the equivalent of reciting “apply it”.
Applicant asserts Claims 10 and 19 are specific machines with defined architectures with a level of structural specificity that identifies as particular machines and not “any and all machines”, as the accelerator circuit’s components are not merely invoked as tools to perform the math, but integrally implement the method. Furthermore, Examiner’s assertion that the circuits are “merely recited to perform functions of the abstract idea” is circular reasoning as it would render all hardware processor patents ineligible because any dedicated circuit that performs a computation could be characterized as “merely performing the function of the abstract idea”.
Examiner respectfully disagrees. The understood scope of “accelerator circuit” is discussed above. Additionally, any dedicated circuit that performs a computation are not characterized as “merely performing the function of the abstract idea” when “the degree to which the machine in the claim can be specifically identified” (MPEP 2106.05(b)(I)). Applicant’s current claims recite an “accelerator circuit” comprising an accumulator/addition circuits that are updated with multiplication product results computed by a plurality of multiplication circuits, in other words, the accumulator/addition circuits and multiplication circuits perform addition and multiplication, respectively, and are not imposing meaningful limits on practicing the abstract idea. Thus, the current recitation of the “accelerator circuit” does not amount to significantly more than a recitation of the words “apply it” because the circuitry, alone and in combination, is recited at a high level of generality.
Applicant asserts the specific ordered combination recited in the claims represents significantly more than the alleged abstract idea and is not merely “apply it” on a generic computer, but a specific technological solution to the technological problem of computational interdependencies in Montgomery multiplication hardware.
Examiner respectfully disagrees for the reasons discussed above.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 1, at Step 1, the claim is directed to a method, which is a statutory category of invention (Process).
At Step 2A Prong 1, Examiner notes that the claims are directed towards an abstract idea. The claim language has been reproduced below:
A method to operate an accelerator circuit to compute a Montgomery multiplication product, modulo a modulus number, of a first number and a second number, the method comprising: accessing, by the accelerator circuit, a first plurality of auxiliary numbers associated with the modulus number and a Montgomery radix value (mental process, mathematical relationship);
performing, by the accelerator circuit, a first plurality of iterations, each of the first plurality of iterations comprising: updating an accumulator with multiplication products of a respective word of a plurality of words of the first number and each of a plurality of words of the second number (mental process, mathematical calculation), wherein the multiplication products of the respective word of the first number and each of the plurality of words of the second number are computed in parallel (mathematical calculation) using a corresponding plurality of multiplication circuits of the processing device;
and determining, by the accelerator circuit and based on the updated accumulator, a respective quotient value of a plurality of quotient values (mental process, mathematical calculation);
performing, by the accelerator circuit, a second plurality of iterations, each of the second plurality of iterations comprising: updating the accumulator using multiplication products of a quotient value of the plurality of quotient values (mental process, mathematical calculation) and each of a plurality of words of a respective auxiliary number of the first plurality of auxiliary numbers (mental process, mathematical calculation);
and obtaining, by the accelerator circuit, the Montgomery multiplication product of the first number and the second number using the updated accumulator (mental process, mathematical calculation), wherein a number of words from the first number comprises n words, and wherein the Montgomery multiplication product of the first number and the second number is obtained using n+4 sets of concurrent multiplication operations (mathematical relationship) performed by the accelerator circuit.
At Step 2A Prong 2, the additional elements are bolded above. The additional elements do not integrate the abstract ideas into a practical application because the computer elements, which are recited at a high level of generality, provide conventional computer functions that do not impose any meaningful limits on practicing the abstract ideas. See MPEP 2106.05(f). The limitation of “accessing a first plurality of auxiliary numbers” is an insignificant extra-solution activity of mere data gathering. The limitation of “updating the accumulator” is merely applying the mathematical concepts of accumulating, equivalent to instructions to apply the mathematical concepts. The limitations of “accelerator circuit” and “corresponding plurality of multiplication circuits of the processing device” are generic computer components recited at a high level of generality. Even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application and the claim is directed to the judicial exception.
At Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception. As set forth in step 2A prong 2 analysis, the function of “accessing a first plurality of auxiliary numbers” is recognized by the courts as well-understood routine and conventional. See MPEP 2106.05(d)(II). Furthermore, the “updating the accumulator”, “accelerator circuit”, and “corresponding plurality of multiplication circuits of the processing device” are the equivalent of adding the words “apply it” to the judicial exception and are mere instructions to implement the abstract idea on a computer. Even when considered in combination, these additional elements represent mere instructions to apply an exception and insignificant extra-solution activity, which do not provide an inventive concept. The claim is not eligible.
Regarding claim 2, it is directed to the mathematical concept and/or mental process of obtaining a final quotient value using a sum of multiplication products of each quotient value of the plurality of quotient values and a respective auxiliary number of the second plurality of auxiliary numbers.
Under Step 2A Prong 2, the claim recites the additional element of “accessing a second plurality of auxiliary numbers”. The additional element does not integrate the abstract ideas into a practical application because it is an insignificant extra-solution activity of mere data gathering and does not impose any meaningful limits on practicing the abstract idea.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 3, it is directed to the mathematical concept and/or mental process of obtaining the Montgomery multiplication product of the first number and the second number comprises: computing multiplication products of the final quotient value and each of a plurality of words of the modulus number.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 4, it is directed to the mathematical concept and/or mental process of wherein each of the second plurality of auxiliary numbers is a modular multiplication product of a negative inverse of the modulus number and a respective auxiliary number of the first plurality of auxiliary numbers.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 5, it is directed to the mathematical concept and/or mental process of obtaining the final quotient value comprises performing a third plurality of iterations, wherein each of the third plurality of iterations is performed concurrently with an iteration of the first plurality of iterations or an iteration of the second plurality of iterations, and wherein each of the third plurality of iterations comprises computing a multiplication product of a quotient value of the plurality of quotient values and a respective auxiliary number of the second plurality of auxiliary numbers.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 6, it is directed to the mathematical concept and/or mental process of determining a first quotient value of the plurality of quotient values comprises: identifying a least significant word of the accumulator as the first quotient value.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 7, it is directed to the mathematical concept and/or mental process of determining a second quotient value of the plurality of quotient values comprises: eliminating the least significant word of the accumulator; and identifying a least significant word of the updated accumulator as the second quotient value.
Under Step 2A Prong 2, the claim recites the additional element “updating the accumulator with additional multiplication products”. The additional element does not integrate the abstract ideas into a practical application because the accumulator is recited at a high level of generality and do not impose any meaningful limits on practicing the abstract idea by merely applying the operation of accumulating.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 8, it is directed to the mathematical concept and/or mental process of wherein each of the n+4 sets of the concurrent multiplication operations comprises n or n+1 concurrent multiplication operations.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 9, it is directed to the mathematical concept and/or mental process of wherein a number of words of the first number comprises n words, wherein n is greater than four, the method further comprising: performing a plurality of preliminary iterations, each of the plurality of preliminary iterations comprising: determining a preliminary quotient value based on the accumulator; and
Under Step 2A Prong 2, the claim recites the additional element “updating the accumulator”. The additional element does not integrate the abstract ideas into a practical application because the accumulator is recited at a high level of generality and do not impose any meaningful limits on practicing the abstract idea by merely applying the operation of accumulating.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claims 10-18, the claims are directed to a system that implements the same or similar features as the method of claims 1-9, respectively, and is therefore rejected for at least the same reasons therein. Furthermore, the additional elements of “memory device” and “accelerator circuit” are recited at a high level of generality, which provide conventional computer functions that do not impose any meaningful limits on practicing the abstract ideas, and thus do not integrate the abstract ideas into a practical application.
Regarding claim 19, at Step 1, the claim is directed to an accelerator, which is a statutory category of invention (Machine).
At Step 2A Prong 1, Examiner notes that the claims are directed towards an abstract idea. The claim language has been reproduced below:
one or more registers to store a first set of auxiliary numbers and a second set of auxiliary numbers, wherein each auxiliary number of the first set of auxiliary numbers and each auxiliary number of the second set of auxiliary numbers are associated with a modulus number and a Montgomery radix value (mathematical relationship, mental process);
and a plurality of multiplication circuits to: compute a first set of multiplication products comprising multiplication products of each word of a first number and each word of a second number (mathematical calculation, mental process), wherein the plurality of multiplication circuits computes the multiplication products of an individual word of the first number and each of the plurality of words of the second number in parallel (mathematical calculation);
and one or more addition circuits to: determine, using the first set of multiplication products, a set of quotient values (mathematical calculation, mental process);
and wherein the plurality of multiplication circuits is further to: compute a second set of multiplication products comprising multiplication products of each quotient value of the set of quotient values and each word of a corresponding auxiliary number of the first set of auxiliary numbers (mathematical calculation, mental process);
wherein the accelerator circuit further comprises: an additional multiplication circuit to: compute a third set of multiplication products comprising multiplication products of each quotient value of the set of quotient values and a corresponding auxiliary number of the second set of auxiliary numbers (mathematical calculation, mental process);
wherein the one or more addition circuits are further to: determine, using the third set of multiplication products, a final quotient value (mathematical calculation, mental process);
wherein the plurality of multiplication circuits is further to: compute a fourth set of multiplication products comprising multiplication products of the final quotient value and each word of the modulus number (mathematical calculation, mental process);
and wherein the one or more addition circuits are further to: obtain, using the third set of multiplication products and a fourth set of multiplication products, a Montgomery multiplication product of the first number and the second number (mathematical calculation, mental process), wherein a number of words of the first number comprises n words, and wherein the Montgomery multiplication product of the first number and the second number is obtained using n+4 sets of concurrent multiplication operations (mathematical relationship).
At Step 2A Prong 2, the additional elements are bolded above. The additional elements do not integrate the abstract ideas into a practical application because the computer elements, which are recited at a high level of generality, are merely applying the mathematical concepts and do not impose any meaningful limits on practicing the abstract ideas. See MPEP 2106.05(f). The limitation “one or more registers” is merely recited to store data which is a high level of generality. The limitations of the “plurality of multiplier circuits”, “one or more addition circuits”, and “additional multiplier circuits” are merely recited to perform functions of the abstract idea, and thus simply applying the abstract idea. Additionally, the plurality of circuits follows from, or is a consequence of, the use of Montgomery multiplication, as Montgomery multiplication used in cryptography requires breaking down a large word into several smaller segments. Even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application and the claim is directed to the judicial exception.
At Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception. As set forth in step 2A prong 2 analysis, the “plurality of multiplier circuits”, “one or more addition circuits”, and “additional multiplier circuits” are the equivalent of adding the words “apply it” to the judicial exception and are mere instructions to implement the abstract idea on a computer. Even when considered in combination, these additional elements represent mere instructions to apply an exception, which does not provide an inventive concept. The claim is not eligible.
Conclusion
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/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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