DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Claim Rejections – 35 USC 101
Applicant's arguments filed 12/18/2025 have been fully considered but they are not persuasive.
Applicant asserts the claim is not merely applying a mathematical concept using generic computer components, but recites a specific hardware architecture where multiple multiplication circuits operate in parallel to compute word-level multiplication products simultaneously. Examiner respectfully disagrees. Applicant’s specification [0025] states “In some embodiments, example operations 200 may be implemented… purely by software executed by CPU 112 (GPU 116).” Thus, claimed hardware architecture must be particular compared to architecture in a CPU or GPU to be considered as not generic. NVIDIA Tesla V100 GPU Architecture, hereinafter “NVIDIA”, discloses architecture for the GPU with multiple cores (pg. 8; Fig. 5) that can be processed in parallel (pgs. 2, 7). Hence, computing in parallel using a corresponding plurality of multiplication circuits is not a sufficiently specific hardware architecture and is still using generic computer components. Therefore, the claim is still applying a mathematical concept using generic computer components.
Applicant asserts the claimed parallel architecture achieves a concrete technical improvement by facilitating fast and efficient Montgomery multiplication operations, high hardware circuitry utilization rate, and an optimal number of multiplication circuits needed to perform the disclosed techniques. Examiner respectfully disagrees. As discussed above, generic computer components may have parallel multiplication circuits, and thus utilizing an optimal number of multiplication circuits, as recited in the claim, is merely instructions to apply the exception. Thus, fast and efficient Montgomery multiplication is a consequence of the judicial exception rather than specific circuitry, however, the judicial exception alone cannot provide the improvement. See MPEP 2106.05(a). Therefore, the claim does not seem to have a concrete technical improvement as the improvements are merely instructions to apply the judicial exception or a consequence of the judicial exception.
Applicant asserts the specific combination of “a corresponding plurality of multiplication circuits” computing multiplication products “in parallel”, combined with the iterative updating of an accumulator and determination of quotient values, represents an unconventional arrangement of hardware components that provides a technical improvement. Examiner respectfully disagrees. As discussed above, GPUs are capable of computing multiplication products in parallel using a corresponding plurality of multiplication circuits, and may use additional cores for other computations such as accumulating and determination of quotient values. In reference to the specification paragraph [0025], software run on GPUs are not unconventional hardware, wherein the corresponding arrangement is mere instructions to couple corresponding cores for the judicial exception. Therefore, the claim does not seem to describe an unconventional hardware arrangement.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 1, at Step 1, the claim is directed to a method, which is a statutory category of invention (Process).
At Step 2A Prong 1, Examiner notes that the claims are directed towards an abstract idea. The claim language has been reproduced below:
A method to operate a processing device to compute a Montgomery multiplication product, modulo a modulus number, of a first number and a second number, the method comprising: accessing, by the processing device, a first plurality of auxiliary numbers associated with the modulus number and a Montgomery radix value (mental process, mathematical process);
performing, by the processing device, a first plurality of iterations, each of the first plurality of iterations comprising: updating an accumulator with multiplication products of a respective word of a plurality of words of the first number and each of a plurality of words of the second number (mental process, mathematical process), wherein the multiplication products of the respective word of the first number and each of the plurality of words of the second number are computed in parallel (mathematical process) using a corresponding plurality of multiplication circuits of the processing device;
and determining, by the processing device and based on the updated accumulator, a respective quotient value of a plurality of quotient values (mental process, mathematical process);
performing, by the processing device, a second plurality of iterations, each of the second plurality of iterations comprising: updating the accumulator using multiplication products of a quotient value of the plurality of quotient values (mental process, mathematical process) and each of a plurality of words of a respective auxiliary number of the first plurality of auxiliary numbers (mental process, mathematical process);
and obtaining, by the processing device, the Montgomery multiplication product of the first number and the second number using the updated accumulator (mental process, mathematical process).
At Step 2A Prong 2, the additional elements are bolded above. The additional elements do not integrate the abstract ideas into a practical application because the computer elements, which are recited at a high level of generality, provide conventional computer functions that do not impose any meaningful limits on practicing the abstract ideas. See MPEP 2106.05(f). The limitation of “accessing a first plurality of auxiliary numbers” is an insignificant extra-solution activity of mere data gathering. The limitations of “updating the accumulator” are merely applying the mathematical process of accumulating, equivalent to instructions to apply the mathematical process. The limitations of “the processing device” and “corresponding plurality of multiplication circuits of the processing device” are generic computer components recited at a high level of generality. Even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application and the claim is directed to the judicial exception.
At Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception. As set forth in step 2A prong 2 analysis, the function of “accessing a first plurality of auxiliary numbers” is recognized by the courts as well-understood routine and conventional. See MPEP 2106.05(d)(II). Furthermore, the “updating the accumulator”, “the processing device”, and “corresponding plurality of multiplication circuits of the processing device” are the equivalent of adding the words “apply it” to the judicial exception and are mere instructions to implement the abstract idea on a computer. Even when considered in combination, these additional elements represent mere instructions to apply an exception and insignificant extra-solution activity, which do not provide an inventive concept. The claim is not eligible.
Regarding claim 2, it is directed to the mathematical concept and/or mental process of obtaining a final quotient value using a sum of multiplication products of each quotient value of the plurality of quotient values and a respective auxiliary number of the second plurality of auxiliary numbers.
Under Step 2A Prong 2, the claim recites the additional element of “accessing a second plurality of auxiliary numbers”. The additional element does not integrate the abstract ideas into a practical application because it is an insignificant extra-solution activity of mere data gathering and does not impose any meaningful limits on practicing the abstract idea.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 3, it is directed to the mathematical concept and/or mental process of obtaining the Montgomery multiplication product of the first number and the second number comprises: computing multiplication products of the final quotient value and each of a plurality of words of the modulus number.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 4, it is directed to the mathematical concept and/or mental process of wherein each of the second plurality of auxiliary numbers is a modular multiplication product of a negative inverse of the modulus number and a respective auxiliary number of the first plurality of auxiliary numbers.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 5, it is directed to the mathematical concept and/or mental process of obtaining the final quotient value comprises performing a third plurality of iterations, wherein each of the third plurality of iterations is performed concurrently with an iteration of the first plurality of iterations or an iteration of the second plurality of iterations, and wherein each of the third plurality of iterations comprises computing a multiplication product of a quotient value of the plurality of quotient values and a respective auxiliary number of the second plurality of auxiliary numbers.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 6, it is directed to the mathematical concept and/or mental process of determining a first quotient value of the plurality of quotient values comprises: identifying a least significant word of the accumulator as the first quotient value.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 7, it is directed to the mathematical concept and/or mental process of determining a second quotient value of the plurality of quotient values comprises: eliminating the least significant word of the accumulator; and identifying a least significant word of the updated accumulator as the second quotient value.
Under Step 2A Prong 2, the claim recites the additional element “updating the accumulator with additional multiplication products”. The additional element does not integrate the abstract ideas into a practical application because the accumulator is recited at a high level of generality and do not impose any meaningful limits on practicing the abstract idea by merely applying the operation of accumulating.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 8, it is directed to the mathematical concept and/or mental process of wherein a number of words of the first number comprises n words, and wherein the Montgomery multiplication product of the first number and the second number is obtained using n+4 sets of concurrent multiplication operations, each of the n+4 sets comprising n or n+1 concurrent multiplication operations.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 9, it is directed to the mathematical concept and/or mental process of wherein a number of words of the first number comprises n words, wherein n is greater than four, the method further comprising: performing a plurality of preliminary iterations, each of the plurality of preliminary iterations comprising: determining a preliminary quotient value based on the accumulator; and
Under Step 2A Prong 2, the claim recites the additional element “updating the accumulator”. The additional element does not integrate the abstract ideas into a practical application because the accumulator is recited at a high level of generality and do not impose any meaningful limits on practicing the abstract idea by merely applying the operation of accumulating.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claims 10-18, the claims are directed to a system that implements the same or similar features as the method of claims 1-9, respectively, and is therefore rejected for at least the same reasons therein. Furthermore, the additional elements of “a memory device” and “processing device” are recited at a high level of generality, which provide conventional computer functions that do not impose any meaningful limits on practicing the abstract ideas, and thus do not integrate the abstract ideas into a practical application.
Regarding claim 19, at Step 1, the claim is directed to an accelerator, which is a statutory category of invention (Machine).
At Step 2A Prong 1, Examiner notes that the claims are directed towards an abstract idea. The claim language has been reproduced below:
one or more registers to store a first set of auxiliary numbers and a second set of auxiliary numbers, wherein each auxiliary number of the first set of auxiliary numbers and each auxiliary number of the second set of auxiliary numbers are associated with a modulus number and a Montgomery radix value (mathematical process, mental process);
and a plurality of multiplication circuits to: compute a first set of multiplication products comprising multiplication products of each word of a first number and each word of a second number (mathematical process, mental process), wherein the plurality of multiplication circuits computes the multiplication products of an individual word of the first number and each of the plurality of words of the second number in parallel (mathematical process);
and one or more addition circuits to: determine, using the first set of multiplication products, a set of quotient values (mathematical process, mental process);
and wherein the plurality of multiplication circuits is further to: compute a second set of multiplication products comprising multiplication products of each quotient value of the set of quotient values and each word of a corresponding auxiliary number of the first set of auxiliary numbers (mathematical process, mental process);
wherein the accelerator circuit further comprises: an additional multiplication circuit to: compute a third set of multiplication products comprising multiplication products of each quotient value of the set of quotient values and a corresponding auxiliary number of the second set of auxiliary numbers (mathematical process, mental process);
wherein the one or more addition circuits are further to: determine, using the third set of multiplication products, a final quotient value (mathematical process, mental process);
wherein the plurality of multiplication circuits is further to: compute a fourth set of multiplication products comprising multiplication products of the final quotient value and each word of the modulus number (mathematical process, mental process);
and wherein the one or more addition circuits are further to: obtain, using the third set of multiplication products and a fourth set of multiplication products, a Montgomery multiplication product of the first number and the second number (mathematical process, mental process).
At Step 2A Prong 2, the additional elements are bolded above. The additional elements do not integrate the abstract ideas into a practical application because the computer elements, which are recited at a high level of generality, are merely applying the mathematical process and do not impose any meaningful limits on practicing the abstract ideas. See MPEP 2106.05(f). The limitation “one or more registers” is merely recited to store data which is a high level of generality. The limitations of the “plurality of multiplier circuits”, “one or more addition circuits”, and “additional multiplier circuits” are merely recited to perform functions of the abstract idea, and thus simply applying the abstract idea. Additionally, the plurality of circuits follows from the use of Montgomery multiplication, as Montgomery multiplication used in cryptography requires breaking down a large word into several smaller segments. Even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application and the claim is directed to the judicial exception.
At Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception. As set forth in step 2A prong 2 analysis, the “plurality of multiplier circuits”, “one or more addition circuits”, and “additional multiplier circuits” are the equivalent of adding the words “apply it” to the judicial exception and are mere instructions to implement the abstract idea on a computer. Even when considered in combination, these additional elements represent mere instructions to apply an exception, which does not provide an inventive concept. The claim is not eligible.
Regarding claim 20, under Step 2A Prong 2, the claim recites additional element “wherein the plurality of multiplication circuits contains four multiplication circuits”. The additional element does not integrate the abstract ideas into a practical application because the multiplication circuits are recited at a high level of generality and do not impose any meaningful limits on practicing the abstract idea. Specifying four multiplication circuits is merely applying the abstract idea, as the abstract idea of the claim recites computing four sets of multiplication products.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHAT N LE whose telephone number is (571)272-0546. The examiner can normally be reached Monday-Friday 8:30AM-5PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew T Caldwell can be reached at (571) 272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182