Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 10 objected to because of the following informalities:
an insulating pattern disposed on the redistribution layer pattern; …
wherein the alignment mark protection pattern offsets a height difference between the alignment mark pattern and the insulating pattern. It is unclear that it refers to either first or second insulating pattern.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (Pub. No.: US 20210398942) (hereinafter Wang).
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Re claim 1, Wang teaches a semiconductor chip comprising:
a chip body (300);
a redistribution layer pattern ([RLP], FIG. 1U [as shown above]) disposed on a surface of the chip body;
an alignment mark pattern [AM1P] disposed to be spaced apart from the redistribution layer pattern [RLP] on the surface of the chip body;
a first insulating pattern [FIP] disposed to contact a side surface of the redistribution layer pattern [RLP] and a side surface of the alignment mark pattern [AM1P] on the surface of the chip body;
a second insulating pattern [SIP] disposed on the redistribution layer pattern [RLP] to protect the redistribution layer pattern; and
an alignment mark protection pattern [AMP] disposed on the alignment mark pattern [AM1P],
wherein the alignment mark protection pattern [AMP] and the second insulating pattern [SIP] are disposed to be separate from each other, and
wherein the redistribution layer pattern consists of conductive materials [RLP],
wherein the second insulating pattern [SIP] is vertically aligned with and disposed directly over the redistribution layer pattern [RLP], and
wherein the second insulating pattern [SIP] directly contacts and covers an upper surface of the redistribution layer pattern [RLP].
Re claim 2, Wang, FIG. 1U teaches the semiconductor chip of claim 1, wherein each of the alignment mark pattern ([AM1P] includes AM1=510b/520b, FIG. 1R, [0024]) and the alignment mark protection pattern [AMP] includes a metal material (AM2, note that the alignment mark protection is including 512b/540b/522b, FIG. 1R, [0042]).
Re claim 3, Wang, FIG. 1U teaches the semiconductor chip of claim 1, wherein the alignment mark protection pattern [AMP] is disposed to cover the alignment mark pattern [AM1P].
Re claim 4, Wang teaches the semiconductor chip of claim 1, wherein the alignment mark protection pattern includes a metal plating layer, and wherein the metal plating layer includes at least one selected from copper (Cu), tin (Sn), and gold (Au) (512b/540b/522b, FIG. 1R, [0042]).
Re claim 5, Wang, FIG. 1U teaches the semiconductor chip of claim 1, wherein the alignment mark protection pattern [AMP] offsets a height difference between an upper surface of the alignment mark pattern [AM1P] and an upper surface of the second insulating pattern [SIP].
Re claim 6, Wang, FIG. 1U teaches the semiconductor chip of claim 1, wherein an upper surface of the alignment mark protection pattern [AMP] is positioned at substantially the same level as an upper surface of the second insulating pattern [SIP].
Re claim 7, Wang, FIG. 1U teaches the semiconductor chip of claim 1, wherein the redistribution layer pattern [RLP] and the alignment mark pattern [AM1P] have substantially the same thickness, and wherein the second insulating pattern [SIP] and the alignment mark protection pattern [AMP] have substantially the same thickness.
Re claim 8, Wang, FIG. 1U teaches the semiconductor chip of claim 1, wherein the first insulating pattern [FIP] is disposed to surround the alignment mark pattern [AM1P].
Re claim 9, Wang, FIG. 1U teaches the semiconductor chip of claim 1, wherein the alignment mark pattern [AM1P] and the alignment mark protection pattern [AMP] are disposed in an edge region on the surface of the chip body (300).
Re claim 10, Wang, FIG. 1U teaches a semiconductor chip comprising:
a chip body (300);
a redistribution layer pattern [RLP] and an alignment mark pattern [AM1P] that are disposed to be spaced apart from each other on a surface of the chip body;
an insulating pattern [SIP] disposed on the redistribution layer pattern [RLP]; and
an alignment mark protection pattern [AMP] disposed on the alignment mark pattern [AM1P],
wherein the alignment mark protection pattern [AMP] includes a metal material (AM2, note that the alignment mark protection is including 512b/540b/522b, FIG. 1R, [0042]), and
wherein the alignment mark protection pattern [AMP] offsets a height difference between the alignment mark pattern [AM1P] and the insulating pattern [SIP],
wherein the alignment mark protection pattern [AMP] and the second insulating pattern [SIP] are disposed to be separate from each other (separated by the metal via) and
wherein the redistribution layer pattern consists of conductive materials [RLP],
wherein the second insulating pattern [SIP] is vertically aligned with and disposed directly over the redistribution layer pattern [RLP], and
wherein the second insulating pattern [SIP] directly contacts and covers an upper surface of the redistribution layer pattern [RLP].
Re claim 11, Wang, FIG. 1U teaches the semiconductor chip of claim 10, wherein the alignment mark protection pattern [AMP] is a metal plating layer, and wherein the metal plating layer includes at least one selected from copper (Cu), tin (Sn), and gold (Au) ([AM1] is 512b/540b/522b, FIG. 1R, [0042] in this instant case).
Re claim 12, Wang teaches the semiconductor chip of claim 10, wherein the redistribution layer pattern ([RLP]= 510a/520a, FIG. 1R) and the alignment mark pattern ([AM1P] includes AM1=510b=520b) include the same metal material (copper, [0042]).
Re claim 13, Wang, FIG. 1U teaches the semiconductor chip of claim 10, wherein an upper surface of the alignment mark protection pattern [AMP] is positioned at substantially the same level as an upper surface of the insulating pattern [SIP].
Re claim 14, Wang, FIG. 1U teaches the semiconductor chip of claim 10, wherein the alignment mark protection pattern [AMP] is disposed to cover the alignment mark pattern [AM1P] on the surface of the chip body (300).
Re claim 15, Wang, FIG. 1U teaches the semiconductor chip of claim 10, wherein the alignment mark pattern [AM1P] and the alignment mark protection pattern [AMP] are disposed in an edge region on the surface of the chip body (300).
Response to Arguments
Applicant's arguments with respect to claims 1 and 10 on the remarks filed on 09/04/2025 have been considered but moot due to a new ground of matching elements, please see the details of rejection as listed above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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/TONY TRAN/Primary Examiner, Art Unit 2893