DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-18 are rejected under 35 U.S.C. 103 as being unpatentable over Woychik et al. (“Woychik” US 2016/0049383) and Kim et al. (“Kim” US 2022/0068835).
Regarding claim 1, Woychik discloses a microelectronics package (Figure 7E) comprising:
a substrate (120);
a first die stack (leftmost stack of dies 130 including the two top dies 130, see labeled below in annotated Figure 7E) electrically coupled to the substrate (120, para. [0024]);
a second die stack (right side stack of three dies 130, see annotated Figure 7E below) electrically coupled to the substrate (120, para. [0024]) and adjacent to the first die stack (leftmost stack, Figure 7E shows the die stacks are laterally adjacent and proximate to each other);
a metal pillar (metal pillar 410 extending from the lowermost die upon which the first die stack and second die stack is mounted [later mapped to the claimed “host die”] to the heat sink 450, see annotated Figure 7E below) between the first and second die stacks (see Figure 7E).
Woychik does not explicitly disclose a metal layer adjacent to a first sidewall of the first die stack and adjacent to a second sidewall of the second die stack; and wherein the metal layer is between the metal pillar and each of the first and second die stacks.
However, Kim discloses in Figure 2 a metal layer (400, top and lateral portions covering the top and lateral sidewalls of the package/chip 1) over a die (package 1 which can be considered as a chip/die, which can include a stack of chips, as para. [0027] of Kim discloses the semiconductor component 200 may be a DRAM, which is known in the art as comprising a plurality of stacked chips) which can be incorporated directly onto both the first and second die stacks of Woychik (see Figure 7E, the die stacks being analogous to the die/package 1 of Kim because Kim’s die 1 comprises die stacks 200, see above), which would result in the configuration of the incorporated metal layer (top and lateral portions of 400 of Kim) being between the metal pillars 410 and each of the die stacks of Woychik.
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Kim above into the teachings of Woychik for the purpose of providing a metal layer onto die stacks which provides electromagnetic shielding (Kim, para. [0038]), thereby reducing electrical interference between adjacent components of a package.
Regarding claim 2, Woychik further discloses a third die stack (stack of dies 130 in the central region of the device, see Figure 7E and annotated Figure 7E) connected to the substrate (120) and adjacent to the second die stack (right side stack, see Figure 7E), wherein:
a second metal pillar (metal pillar 410 extending from the substrate 120 to the heat sink 450 directly next to the third, central die stack 130, see Figure 7E and annotated Figure 7E) is between the second and third die stacks (right and central die stacks 130, respectively, see Figure 7E and annotated Figure 7E).
Woychik does not disclose the metal layer is adjacent to a third sidewall of the third die stack; and the metal layer is between the second metal pillar and the third die stack.
However, Kim discloses in Figure 2 a metal layer (top and lateral portions of shield 400) adjacent to a sidewall of a die (sidewalls of the package/die 1) which can further be incorporated to be on the third die stack of Woychik, in addition to the first and second die stacks, thereby arriving at the claimed configuration of the metal layer (400, top and lateral portions, as taught by Kim) between the second metal pillar (metal pillar 410 directly adjacent to the central, third die stack) and the third die stack (central die stack) because the metal layer is disposed directly on the outer surfaces of the dies as taught by Kim, see Figure 2 of Kim which shows the metal layer disposed directly on top and on side surfaces of the die/die stack 1.
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Kim above into the teachings of Woychik for the purpose of providing an additional metal layer onto another die stack which provides electromagnetic shielding (Kim, para. [0038]), thereby reducing electrical interference between adjacent components of a package.
Regarding claim 3, the combination of Woychik and Kim discloses a portion of the metal layer (top and lateral portions of shield 400 of Kim) is over a top of each of the first and second die stacks (incorporated to cover top and lateral sides of each die stack of Woychik); and the metal pillar (410, directly adjacent to the first die stack of Woychik) is coplanar with, or extends above, the portion of the metal layer that is over the top of each of the first and second die stacks (because the metal layer 400 of Kim is directly disposed on the top and side layers of the die 1 which comprises a die stack, and the heights of the die stacks of Woychik are below the top surfaces of the metal pillars 410, then incorporating this feature into Woychik would result in the claimed configuration of the metal pillar 410 extending above the metal layer on the die stacks).
Regarding claim 4, Woychik discloses the first die stack (leftmost die stack 130) comprises an upper die on a lower die (two dies stacked, upper and lower dies 130) with a plurality of electrical bumps therebetween (see electrical bumps on lower sides of each upper and lower dies in Figure 7E and para. [0024] describing electrical connection between different dies 130).
Woychik does not disclose that the upper die further comprises a metal plate through which the electrical bumps pass, and wherein the metal layer is in direct contact with the metal plate.
However, Kim discloses a metal plate (lower portions of 400 directly contacting the lower surface of the die 1) on the upper die (since Kim’s die 1 comprises an upper die of the stack 200, the metal plate is considered as being on the upper die) through which the electrical bumps (155) pass (see Figure 2), and wherein the metal layer (top and lateral portions of shield 400) is in direct contact with the metal plate (lower portion of 400, see the portions directly contacting by being integral with each other, see Figure 2).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Kim above into the teachings of Woychik. The claimed elements were known in the prior art, and one having ordinary skill in the art could combine the elements with no change in their respective functions with the predictable result of further providing electromagnetic shielding and protection to a lower surface of the die and electrical connections thereon. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 5, the combination of Woychik and Kim discloses wherein the first die stack (leftmost stack of two dies 130) further comprises an underfill material (encapsulant material 440, portion surrounding the electrical contacts on the lower surface of each die in the first die stack, which is made of an electrically insulating material, and electrically insulating material serves as an underfill to insulate interconnections on the dies) between the upper and lower dies (see Figure 7E) and surrounding the electrical bumps (see Figure 7E, the portion of the encapsulant 400 surrounding the electrical connections of the first die stack is considered the underfill), the underfill material (440, portion surrounding the electrical contacts on the lower surface of each die in the first die stack) in direct contact with the metal plate (lower portion of 400 of Kim, as taught by Kim, the metal plate covers and is in direct physical contact with the lower surface of the die 1, and the encapsulant of Woychik covers the lower surface of the dies 130 of the first die stack, thus the incorporation of the metal plate from Kim would result in the claimed configuration of the underfill 440 of Woychik being in direct contact with the metal plate as incorporated by Kim).
Regarding claim 6, Woychik discloses a heat spreader (450) over a top of the first and second die stacks (see Figure 7E); and
a thermal interface material (portions of encapsulant 440 that surround the metal pillars and the lateral sidewalls of the die stacks) between the heat spreader (450) and each of the metal pillar (410 directly adjacent to the first die stack), the first die stack, and the second die stack (see Figure 7E, and encapsulant 440 is interpreted as a thermal interface material, as electrically insulating material such as epoxy, which is used for the encapsulant 440 see para. [0066] has a thermal conductivity, thus aids in thermal dissipation in the package).
Regarding claim 7, the combination of Woychik and Kim discloses wherein a portion of the metal layer (400, top and lateral portions, of Kim) is over a top of each of the first and second die stacks (see the metal layer is over at least the top surface of the die 1); and the metal pillar (metal pillar 410 next to first die stack, see annotated Figure 7E) extends beyond the top of each of the first and second die stacks (see Figure 7E) and is embedded within a thickness of the thermal interface material (portion of encapsulant 440, see Figure 7E which shows the metal pillar embedded in the encapsulant/thermal interface material 440).
Regarding claim 8, Woychik discloses the first die stack (left two dies 130 stacked, see annotated Figure 7E) and the second die stack (right side die stack of three dies 130, see annotated Figure 7E) are each electrically coupled to a first side of a host die (upper side of the lowermost, largest dies 130 on the substrate 120, see Figure 7E and labeled in annotated Figure 7E);
a second side of the host die (lower side of the host die) is electrically coupled to the substrate (120, para. [0024]); and the metal pillar (metal pillar 410 directly adjacent to the first die stack, see labeled in Figure 7E) extends between the first side of the host die (upper side of the host die) and the thermal interface material (portion of encapsulant 440 surrounding the metal pillars 410 and the die stacks, the metal pillar extends in a region between the host die and the thermal interface material which is the encapsulant surrounding the die stacks and the metal pillars).
Regarding claim 9, Woychik discloses wherein the first metal pillar comprises copper (410 directly adjacent to the first die stack, see para. [0062] which discloses the pillars 410 comprise copper).
Regarding claim 10, Woychik discloses wherein the metal pillar (410 directly adjacent to the first die stack) does not form an electrical pathway through the microelectronics package (para. [0062] discloses that the metal pillars 410 may not be connected to an electrically active pad or pathway in any of the dies 130 or substrate 120).
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Regarding claim 11, Woychik discloses a microelectronics package (Figure 7E) comprising:
a substrate (120);
a plurality of die stacks (see stacks of dies 130) on the substrate (120), each of the die stacks (130) comprising an upper die over a lower die with electrical bumps therebetween (see stacks of dies 130, where interconnection bumps are between each stacked upper and lower dies 130);
a heat spreader (450) over the plurality of die stacks (130, see Figure 7E), opposite the substrate (120, see Figure 7E); and
a plurality of metal pillars (410) [between the metal layer over each of the die stacks], wherein individual ones of the plurality of metal pillars (410) fill a gap between adjacent ones of the die stacks (stacks of dies 130, the metal pillars 410 at least partially fill the gaps between the adjacent die stacks 130).
Woychik does not disclose a metal layer adjacent to a sidewall of at least one die in each of the die stacks; and wherein the metal layer is between individual ones of the metal pillars and individual ones of the die stacks.
However, Kim discloses in Figure 4 a metal layer (400, top and lateral portions directly contacting and covering the top and lateral sidewalls of the package/chip 1) over a die (package 1 which can be considered as a chip/die, which can include a stack of chips, as para. [0027] of Kim discloses the semiconductor component 200 may be a DRAM, which is known in the art as comprising a plurality of stacked chips) which can be incorporated onto at least one of the dies in the die stacks of Woychik (see Figure 7E), which would result in the configuration of the incorporated metal layer (top and lateral portions of 400 of Kim which are directly physically contacting the die 1) being between some of the individual the metal pillars (410, individual metal pillars being those pillars between die stacks) and each of the die stacks (stacks of dies 130) of Woychik.
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Kim above into the teachings of Woychik for the purpose of providing a metal layer onto at least of the dies of the die stacks which provides electromagnetic shielding (Kim, para. [0038]), thereby reducing electrical interference between adjacent components of a package.
Regarding claim 12, Woychik discloses wherein the plurality of metal pillars (410) are thermally coupled to the heat spreader (450, see para. [0063]) through an intervening thermal interface material (encapsulant 440 is interpreted as a thermal interface material, as electrically insulating material such as epoxy, which is used for the encapsulant 440 see para. [0066] has a thermal conductivity, thus aids in thermal dissipation in the package), and wherein the thermal interface material (440) is in direct contact with the metal pillars (410, see Figure 7E).
Regarding claim 13, Woychik does not disclose wherein the upper die within each of the die stacks comprises a metal plate and wherein each metal plate is in direct contact with the metal layer.
However, Kim discloses in Figure 4 an upper die (Kim’s die 2 comprises an upper die of the stack 200) comprises a metal plate (lower portion of shield 400 that convers the bottom portion of the upper die of 2) in direct contact with the metal layer (upper and lateral portions of the shield 400, in direct contact with the lower side portion of the shield, see Figure 4).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Kim above into the teachings of Woychik. The claimed elements were known in the prior art, and one having ordinary skill in the art could combine the elements with no change in their respective functions with the predictable result of further providing electromagnetic shielding and protection to a lower surface of the upper die within each die stack. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 14, Kim discloses wherein the metal layer (400) is a conformal layer (here, conformal is interpreted to be a layer which conforms to a surface, Kim’s metal layer, upper and lateral portions of the shield 400, conform to the outer surface of the chip/package 1, thus is considered a conformal layer).
Regarding claim 15, Woychik discloses wherein ends of the metal pillars (410) are embedded within the thermal interface material (440, see Figure 7E which shows the metal pillars 410 being embedded in the encapsulant/thermal interface material 440).
Regarding claim 16, Kim discloses wherein the metal plate (lower portion of 400 covering the lower surface of the die 2) defines a plurality of through holes (see through holes in Figures 3 and 4) sized to allow one or more of the electrical bumps (155/130) to pass though the metal plate (see Figure 4).
Regarding claim 17, Woychik discloses wherein a first end (lower ends) of at least a portion of the plurality of metal pillars (410) is located proximate to a first side of a host die (lowermost, largest dies 130 upon which the further stacks of dies 130 are mounted), wherein the plurality of die stacks (stacks of dies 130 on the host dies) are electrically coupled to the first side of the host die (upper side of the host dies 130, see electrical bumps therebetween, providing electrical connection, see also para. [0024] which describes electrical connections) and a second side of the host die (lower side of the host die) is coupled to the substrate (120, see Figure 7E).
Regarding claim 18, Woychik discloses wherein the plurality of metal pillars (410) does not form electrical pathways through the microelectronics package (para. [0062] discloses that the metal pillars 410 may not be connected to an electrically active pad or pathway in any of the dies 130 or substrate 120).
Response to Arguments
Applicant’s arguments with respect to claims 1 and 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s amendments to claims 9, 11, and 17 with respect to the objection to claims 9, 11, and 17 have been fully considered and overcome the objections. The objections of claims 9, 11, and 17 have been withdrawn.
Applicant’s amendments to claims 15 and 16 with respect to the 112 rejections of claims 15 and 16 have been fully considered and overcome the 112 rejection. The 112 rejections of claims 15 and 16 have been withdrawn.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899