DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office Action is in response to Applicant’s amendment filed on February 06, 2026. Claims 1, 2, 4-16, and 19 have been amended. No new claims have been added. No claims have been cancelled. Currently, claims 1-20 are pending.
Response to Arguments
Applicant’s arguments with respect to claims 1, 6 and 10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL. —The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 1-5 and 17-19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites " each multi-device stack structure of the first set and the second set of multi- device stack structures is stacked together and arranged vertically at different vertical positions within a common vertical stack ". However, the original claim set and the specification does not mention “the first set and the second set of multi- device stack structures is stacked together and arranged vertically at different vertical positions within a common vertical stack”. Therefore, it introduces new matter which is not covered by the original specification filed with the application.
Claims 2-5 and 17-19 inherit the deficiencies of the Independent Claim 1.
Appropriate corrections are required.
Election/Restrictions
Amended claims 6-9, 10-16, and 20 directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
This application contains claims directed to the following patentably distinct species.
Species I: Claims 1-5, and 17-19 directed to an embodiment of a multi- device stack structures, which includes a complementary field effect transistor (CFET) technology, e.g. Figs. 3-9.
Species II: Claims 6-9, 10-16, and 20, directed to an embodiment of a multi- device stack structures, which includes various multi-transistor fabrication schemes and techniques described herein may provide for other types of multiple stack configurations with any number of devices, such as, e.g., an N-only stack and/or a P-only stack. For instance, as described herein, a precharge circuit may be formed with a P-only stack, wherein the P-only stack may include multiple transistors, such as, e.q., 2 or 3 or 4 or may be built on top of each other in a multi-transistor various other circuits associated with memory similar P-only/N-only stack configurations.
The inventions are independent or distinct, each from the other because as disclosed the different species have mutually exclusive characteristics for each identified species. Specifically, Species I claims an embodiment of a multi- device stack structures, which includes a complementary field effect transistor (CFET) technology. For instance, in Figs. 3-9 show a device with N-type and P-type transistors and can be used in NAND gates, NOR gates and AND- OR-Invert (AOI) gates.
In contrast, Species II, claims a method of forming an embodiment of a multiple stack configurations with any number of devices, such as, e.g., an N-only stack and/or a P-only stack. For instance, in Specification ¶ [0019] discloses multiple stack configurations with any number of devices, such as, e.g., an N-only stack and/or a P-only stack which are used in AND gates, OR gates and NOT gates.
In addition, these species are not obvious variants of each other based on the current record because the functionality of the structures with complementary transistor stack with P-type and N-type transistors are different than the functionality of the structures with solely P-type or N-type transistors.
There is a search and/or examination burden for the patentably distinct species, e.g. Species I and Species II as set forth above because at least the following reason(s) apply: a search for CFET device with N-type and P-Type transistors, is not likely to find art pertinent to multiple stack configurations with an N-only stack and/or a P-only stack.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 6-9, 10-16, and 20 withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 and 18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Liebmann, Lars (US 20200135718 A1) “Liebmann et al.”.
With Regard to Independent Claim 1, Liebmann et al. Figs. 5-8 discloses a device (“3D IC” ¶ [0046]) comprising:
a multi-layered circuit architecture (“3D IC having three tiers” ¶ [0046]; “each tier of semiconductor devices may include vertically stacked semiconductor devices” ¶ [0045]),
having a first circuit layer formed by a first set of multi-device stack structures (“first tier of transistors includes SD region 505P and SD region 505N of respective p-type and n-type devices,” ¶ [0046]) and
a second circuit layer formed by a second set of multi-device stack structures (“a second tier includes SD region 507N and SD region 507P of respective p-type and n-type devices” ¶ [0046])
wherein the first circuit layer and the second circuit layer each includes a sole logic circuit or a sole memory circuit of a same type (“an AO122 logic cell formed of a plurality of stacked complementary FET devices, with the stacked complementary FETS repeated within t” ¶ [0054]);
each the multi-device stack structure of the first set and the second set of multi- device stack structures is stacked together and arranged vertically at different vertical positions within a common vertical stack and has at least two transistors (“Specifically, FIGS. 7 and 8 show the A, B, C and D complementary pairs of FETs arranged in that order along the west to east direction of the device.” ¶ [0054]; “G1, G2, G3 and G4 tracks provide gate inputs for A, B, C and D complementary FET devices of the AOI cell” ¶ [0055]); and
the at least two transistors are arranged vertically in a multi-transistor stack configuration (“SD regions 505P and 505N form a complementary pair, SD regions 507N and 507P form a complementary pair, and SD regions 509P and 509N form another complementary pair.” ¶ [0047]).
With Regard to Claim 2, Liebmann et al. discloses the limitations of claim 1 as discussed above. Liebmann et al., Figs. 5-8 further discloses the multi-device stack structures of the first set and the second set of multi-device stack structures are formed in a single semiconductor die 501 (“a monolithic semiconductor substrate having a generally planar substrate surface 501” ¶ [0046]), and wherein the at least two transistors include at least one of one or more P-type transistors and one or more N-type transistors that are formed within the single semiconductor die 501 (“structure 500 represents a portion of a monolithic semiconductor substrate having a generally planar substrate surface 501” ¶ [0046]), and wherein the multi-layered circuit architecture is a three-dimensional (3D) circuit architecture (“3D IC having three tiers” ¶ [0046]).
With Regard to Claim 3, Liebmann et al. discloses the limitations of claim 1 as discussed above. Liebmann et al., Figs. 5-8, further discloses the multi-layered circuit architecture is used for at least one of bitcells, inverters, NANO gates, NOR gates and AND-OR-Invert (AOI) gates (“FIGS. 5 and 6 provides a lower tier implementing an AOI logic cell” ¶ (0054)).
With Regard to Claim 4, Liebmann et al. discloses the limitations of claim 1 as discussed above. Liebmann et al., Figs. 5-8, further discloses the multi-transistor stack configuration (“the stacked transistor pairs are configured in an alternating stack orientation by doping type of the transistors.” ¶ [0047]) includes a multi-device stack configuration of at least one of one or more P-type transistors and one or more N-type transistors arranged (“In the embodiment of FIG. 5, SD region 505P is part of a p-type transistor, while its complement 505N is of an n-type transistor. Similarly, SD region 507N is of n-type and its complement 507P is of p-type” ¶ [0047]) in at least one of a P-over-N-over-N-over-P (PNNP) stack configuration, a N-over-P-over-P-over-N (NPPN) stack configuration (“stack orientation (i.e. n-over-p, then p-over-n)” ¶ [0047]), a P-over-N-over-P-over-N (PNPN) stack configuration and a N-over-P-over-N-over-P (NPNP) stack configuration.
With Regard to Claim 5, Liebmann et al. discloses the limitations of claim 1 as discussed above. Liebmann et al., Figs. 5-8, further discloses the multi-transistor stack configuration (“the stacked transistor pairs are configured in an alternating stack orientation by doping type of the transistors.” ¶ [0047]) includes a multi-device stack configuration of at least one of one or more P-type transistors and one or more N-type transistors (“In the embodiment of FIG. 5, SD region 505P is part of a p-type transistor, while its complement 505N is of an n-type transistor. Similarly, SD region 507N is of n-type and its complement 507P is of p-type” ¶ [0047]), and wherein the P-type transistors are P-type field-effect transistors (PFETs), and wherein the N-type transistors are N-type field-effect transistors (NFETs) (“FIGS. 7 and 8 provide planar views of the a lower tier of the IC of FIGS. 5 and 6 implementing an AO122 logic cell formed of a plurality of stacked complementary FET devices, with the stacked complementary FETS repeated within the lower tier” ¶ [0054]; “FETs may be n-type or p-type FETS that are arranged along the substrate surface or stacked vertically over one another along the thickness direction of the substrate” ¶ [0033] ).
With Regard to Claim 18, Beigel et al. discloses the limitations of claim 1. However, Beigel et al. further discloses, wherein the multi-layered circuit architecture includes vertically aligned inter-layer vias electrically coupling the first circuit layer and the second circuit layer (“Several local interconnects to electrically connect the semiconductor devices as necessary to form functional circuits.” ¶ [0049]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17 is rejected under 35 U.S.C. 103 as being unpatentable over Liebmann, Lars (US 20200135718 A1) “Liebmann et al.” further in view of Zhang, Chen (US 20190229117 A1) “Zhang et al.”.
With Regard to Claim 17, Beigel et al. discloses the limitations of claim 1. However, Beigel et al. does not disclose, wherein the multi-transistor stack configuration includes nano-sheet field-effect transistors (nano-sheet FETs) or fin field-effect transistors (FinFETs) devices.
In the similar field of endeavor 3D stacked structure Zhang et al. Fig. 1, discloses wherein the multi-transistor stack configuration includes nano-sheet field-effect transistors (nano-sheet FETs) or fin field-effect transistors (FinFETs) devices (“the top VTFETs are located at the tops of two adjacent fins 102 and 104” ¶ [0041]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the transistors of Beigel et al. with the VFET on the fin of Zhang et al. in order to provide improved control over the channel due to the 3D fin shaped structure and effective current flow.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKHEE SARKER-NAG whose telephone number is (703)756-4655. The examiner can normally be reached Monday -Friday 7:15 AM to 5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, YARA J. GREEN can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893