DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office Action is in response to Applicant’s amendment filed on April 27, 2026. Claims 1, 2, 6 and 10-11 have been amended. No new claims have been added. No claims have been cancelled. Currently, claims 1-20 are pending.
Amendments to the independent claim to recite “single vertical stack,” rather than “common vertical stack.” which overcomes the 112 Rejection.
The Final Rejection mailed on February 26, 2026 has been withdrawn and prosecution has been reopened.
The Species restriction set forth in the Final Rejection mailed on February 26, 2026 has been withdrawn.
Response to Arguments
Applicant’s arguments, see page 9-12 of the Remarks document, filed 04/27/2026, with respect to the rejection(s) of claim(s) 1 under 35 U.S.C. 102(a)(2) have been fully considered but not persuasive. The reason is set forth below,
Regarding Amended Claim 1, Applicant argues “Liebmann does not contemplate (and therefore cannot teach or suggest) that the same circuit is repeated in multiple tiers. Indisputably, Liebmann is devoid of teaching circuit layers of a multi-device stack structure each including a same logic or a same memory circuit, as required by claim 1, as amended.” However, Liebman et al. clearly shows the first and second circuits both are same type of complementary FETs. Furthermore, Liebman et al. Abstract discloses “A first vertical interconnect structure extends downward from the wiring tier to the first tier of semiconductor devices to electrically connect the wiring tier to a device within the first tier of semiconductor devices. A second vertical interconnect structure extends upward from the wiring tier to the second tier of semiconductor devices to electrically connect the wiring tier to a device within the second tier of semiconductor devices.”; ¶ [0035] discloses, “As with the lower tier, the upper tier of devices may include one or more semiconductor devices, such as n-type or p-type FETs arranged laterally or stacked over one another, to form a functional circuit” and ¶ [0058-0066] clearly discloses that the same types of logic devices are stacked collinearly, which enables monolithic fabrication. Moreover, Applicant’s specification ¶ [0028] discloses “in some instances, the vertical z-direction refers to dual or double multi-device stack.”
Furthermore, upon consideration, a new additional ground of rejection is made over Wu, Gary Chunshien (US 20170264288 A1) “Wu et al.”. and Liu, Chi-Lin (US 20200395938 A1) “Liu et al.”.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL. —The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 2 and 11 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 2 recites " the first set of multi-device stack structures that are non-contiguous within the single vertical stack and the second circuit layer includes two or more multi-device stack structures of the second set of multi-device stack structures that are non-contiguous within the single vertical stack.". However, the original claim set and the specification does not mention “the first set of multi-device stack structures that are non-contiguous within the single vertical stack and the second circuit layer includes two or more multi-device stack structures of the second set of multi-device stack structures that are non-contiguous within the single vertical stack.”. Therefore, it introduces new matter which is not covered by the original specification filed with the application.
Claim 11 recites " the plurality of multi-device stack structures that are non-contiguous". However, the original claim set and the specification does not mention “the plurality of multi-device stack structures that are non-contiguous.”. Therefore, it introduces new matter which is not covered by the original specification filed with the application.
Appropriate corrections are required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 5-6 and 19-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wu, Gary Chunshien (US 20170264288 A1) “Wu et al.”.
With Regard to Independent Claim 1, Wu et al. Figs. 2A-4B discloses a device comprising:
a multi-layered circuit architecture (“a circuit diagram of an inverter (110B)” ¶ [0039]),
having a first circuit layer formed by a first set of multi-device stack structures (“the first stack” ¶ [0039]) and
a second circuit layer formed by a second set of multi-device stack structures (“the second stack” ¶ [0039])
wherein the first circuit layer and the second circuit layer each includes a sole logic circuit (“each of the first NMOS stack (MS01-MS04) and the second PMOS stack (MS11-MS14)” ¶ [0039]) or a sole memory circuit of a same type;
each multi-device stack structure of the first set and the second set of multi- device stack structures is stacked together and arranged vertically at different vertical positions within a single vertical stack and has at least two transistors (Fig. 2B shows PMOS stack (MS11-MS14) and NMOS stack (MS01-MS04) is stacked together and arranged vertically at different vertical positions within a single vertical stack and has at least two transistors); and
the at least two transistors are arranged vertically in a multi-transistor stack configuration (“the first stack and the second stack of the inverter (110B) each comprise four transistors” ¶ [0039]).
With Regard to Claim 3, Wu et al. discloses the limitations of claim 1 as discussed above. Wu et al., 2A-3B, further discloses the multi-layered circuit architecture is used for at least one of bitcells, inverters (“a circuit diagram of an inverter” ¶ (0039)), NANO gates, NOR gates and AND-OR-Invert (AOI) gates.
With Regard to Claim 5, Wu et al. discloses the limitations of claim 1 as discussed above. Wu et al., 2A-4B, further discloses the multi-transistor stack configuration includes a multi-device stack configuration of at least one of one or more P-type transistors and one or more N-type transistors, and wherein the P-type transistors are P-type field-effect transistors (PFETs), and wherein the N-type transistors are N-type field-effect transistors (NFETs) (“the high stack (310) comprises PMOS FET transistors (MS11-MS16) arranged in a stacked configuration as depicted in FIG. 4A, and the low stack (315) comprises NMOS FET transistors (MS01-MS06) arranged in a stacked configuration as depicted in FIG. 4B.” ¶ [0049]).
With Regard to Independent Claim 6, Wu et al. Figs. 2A-4B discloses a device comprising: a multi-device stack structure for use in multi-bit circuit architecture (“a circuit diagram of an inverter (110B)” ¶ [0039]),
wherein the multi-device stack structure has at least two transistors (“each of the first NMOS stack (MS01-MS04) and the second PMOS stack (MS11-MS14)” ¶ [0039]), wherein the at least two transistors are arranged vertically in one or more of at least four transistor stack configurations (“the first stack and the second stack of the inverter (110B) each comprise four transistors” ¶ [0039]).
With Regard to Claim 19, Wu et al. discloses the limitations of claim 1 as discussed above. Wu et al., 2A-4B, further discloses wherein at least one multi-device stack structure of the first set and the second set of multi-device stack structures is arranged in at least one of a P-over-P (PP) stack configuration and a N-over-N stack (NN) configuration that are arranged vertically in the multi-transistor stack configuration (“each of the first NMOS stack (MS01-MS04) and the second PMOS stack (MS11-MS14)” ¶ [0039]).
With Regard to Claim 20, Wu et al. discloses the limitations of claim 6 as discussed above. Wu et al., 2A-4B, further discloses, wherein the one or more at least four transistor stack configuration includes solely an N-type stack (“NMOS stack (MS01-MS04)” ¶ [0039]) or solely a P-type stack (“PMOS stack (MS11-MS14)” ¶ [0039]).
Claims 10-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Liu, Chi-Lin (US 20200395938 A1) “Liu et al.”.
With Regard to Independent Claim 10, Liu et al. Figs. 1-13 discloses a device comprising: a plurality of multi-device stack structures stacked together and arranged vertically in a single vertical stack for use in multi-bit circuit architecture (“ An interconnect layer 64 includes N (e.g., an integer number of) conductive layers (e.g., metal layers M1 to MN) used for interconnecting devices within layers in interconnect layer 64 and for forming electrical connections to external devices, etc.” ¶ [0041]), wherein each multi- device stack structure of the plurality of multi-device stack structures has at least two transistors (“PMOS transistors 110-113” ¶ [0043]), wherein the at least two transistors are arranged vertically in a multi-transistor stack configuration (Figs. 5A-13B shows the transistors are arranged vertically), wherein different subsets include one or more multi-device stack structures of the plurality of multi-device stack structures, and wherein the different subsets are electrically grouped to form different respective logic or respective memory circuits (“The DMUX4 circuit 100 includes an eight-input AND-OR (AO2222) logic circuit 102 and an inverter 104 that together are implemented by 18 transistors.” ¶ [0042]).
With Regard to Claim 11, Liu et al. discloses the limitations of claim 10. Liu et al. Figs. 1-13 further discloses, wherein the plurality of multi-device stack structures are formed in a single monolithic semiconductor die, and wherein the at least two transistors include at least one of one or more P-type transistors (“PMOS transistors” ¶ [0043]) and one or more N-type transistors (“NMOS transistors” ¶ [0044]) are formed within the single monolithic semiconductor die, and wherein the multi- bit circuit architecture is a three-dimensional (3D) circuit architecture (“The structure 60 is shown in the X-axis and Z-axis directions while the Y-axis direction is orthogonal to the plane of the cross-section illustrated in FIG. 4.” ¶ [0040]), and wherein at least one of the different subsets includes two or more multi-device stack structures of the plurality of multi-device stack structures that are non-contiguous within the single vertical stack (“The DMUX4 circuit 100 includes an eight-input AND-OR (AO2222) logic circuit 102 and an inverter 104 that together are implemented by 18 transistors.” ¶ [0042]).
With Regard to Claim 12, Liu et al. discloses the limitations of claim 10. Liu et al. Figs. 1-13 further discloses, wherein the multi-bit circuit architecture comprises a multi-layer inverter standard cell for use in integrated circuits (“A standard cell can include an entire device, such as ….an inverter” ¶ [0033]), and wherein the multi-transistor stack configuration includes a multi-device stack configuration of at least one of one or more P-type transistors (“PMOS transistors” ¶ [0043]) and one or more N-type transistors (“NMOS transistors” ¶ [0044]), and wherein the one or more P-type transistors are P-type field-effect transistors (PFETs), and wherein the one or more N-type transistors are N-type field-effect transistors (NFETs) (“logic circuits with transistors formed using a fin field effect transistor (FinFET)” ¶ [0039]).
With Regard to Claim 13, Liu et al. discloses the limitations of claim 10. Liu et al. Figs. 1-13 further discloses, wherein the multi-bit circuit architecture comprises a multi-bit NAND gate (“standard cells can be logic gates, such as an AND gate, an OR gate, an XOR gate, a NOT gate, a NAND gate, a NOR gate, and an XNOR gate, and combinational logic circuits such as a multiplexer, a flip-flop, an adder, and a counter. Standard cells can be implemented to realize complex integrated circuit functions.” ¶ [0002]; “a four-input NAND (ND4)” ¶ [0069]) for use in integrated circuits, and wherein the multi-transistor stack configuration includes a multi-device stack configuration of at least one of one or more P-type transistors (“PMOS transistors” ¶ [0043]) and one or more N-type transistors (“NMOS transistors” ¶ [0044]), and wherein the one or more P-type transistors are P-type field-effect transistors (PFETs), and wherein the one or more N-type transistors are N-type field-effect transistors (NFETs) (“logic circuits with transistors formed using a fin field effect transistor (FinFET)” ¶ [0039]).
With Regard to Claim 14, Liu et al. discloses the limitations of claim 10. Liu et al. Figs. 1-13 further discloses, wherein the multi-bit circuit architecture comprises a multi-bit NOR gate for use in integrated circuits (“standard cells can be logic gates, such as an AND gate, an OR gate, an XOR gate, a NOT gate, a NAND gate, a NOR gate, and an XNOR gate, and combinational logic circuits such as a multiplexer, a flip-flop, an adder, and a counter. Standard cells can be implemented to realize complex integrated circuit functions.” ¶ [0002]), and wherein the multi-transistor stack configuration includes a multi-device stack configuration of at least one of one or more P-type transistors (“PMOS transistors” ¶ [0043]) and one or more N-type transistors (“NMOS transistors” ¶ [0044]), and wherein the one or more P-type transistors are P-type field-effect transistors (PFETs), and wherein the one or more N-type transistors are N-type field-effect transistors (NFETs) (“logic circuits with transistors formed using a fin field effect transistor (FinFET)” ¶ [0039]).
With Regard to Claim 15, Liu et al. discloses the limitations of claim 10. Liu et al. Figs. 1-13 further discloses, wherein the multi-bit circuit architecture comprises a multi-bit AND-OR-Invert gate for use in integrated circuits (“DMUX4 circuit 200 utilizes six-input AND-OR-INVERT (AOI222) logic” ¶ [0052]; “A 4-input AND-OR-INVERT (AOI22)” ¶ [0060]), and wherein the multi-transistor stack configuration includes a multi-device stack configuration of at least one of one or more P-type transistors (“PMOS transistors” ¶ [0062]) and one or more N-type transistors (“NMOS transistors” ¶ [0061]), and wherein the one or more P-type transistors are P-type field-effect transistors (PFETs), and wherein the one or more N-type transistors are N-type field-effect transistors (NFETs) (“logic circuits with transistors formed using a fin field effect transistor (FinFET)” ¶ [0039]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Wu, Gary Chunshien (US 20170264288 A1) “Wu et al.” in view of Liu, Chi-Lin (US 20200395938 A1) “Liu et al.”.
With Regard to Claim 2, Wu et al. discloses the limitations of claim 1 as discussed above. However, Wu et al., does not disclose, wherein the first circuit layer includes two or more multi-device stack structures of the first set of multi-device stack structures that are non-contiguous within the single vertical stack and the second circuit layer includes two or more multi-device stack structures of the second set of multi-device stack structures that are non-contiguous within the single vertical stack.
In the similar field of endeavor of semiconductor devices, Liu et al. Fig. discloses, wherein the first circuit layer (“Some disclosed DMUX cells include logic circuits with transistors formed using a fin field effect transistor (FinFET) architecture.” ¶ [0039]) includes two or more multi-device stack structures of the first set of multi-device stack structures that are non-contiguous within the single vertical stack and the second circuit layer includes two or more multi-device stack structures of the second set of multi-device stack structures that are non-contiguous within the single vertical stack (“An interconnect layer 64 includes N (e.g., an integer number of) conductive layers (e.g., metal layers M1 to MN) used for interconnecting devices within layers in interconnect layer 64 and for forming electrical connections to external devices, etc. The interconnect layer 64 generally includes vias, inter-level dielectric materials, passivation layers, bonding pads, packaging resources, etc. Each metal (e.g., conductive) layer M in the interconnect layer 64 is commonly called metal one, metal two, metal three (M1, M2, M3, etc) layers, etc. Between the various metal layers M are dielectric materials (e.g., high-K, low-K material, etc.) 66 used to insulate the metal layers M.” ¶ [0041]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the transistors structure of Wu et al, using the structure of Liu et al. in order to insulate the metal layers (Liu et al. ¶ [0041]).
With Regard to Claim 7, Wu et al. discloses the limitations of claim 6 as discussed above. Wu et al., 2A-4B, further discloses wherein the multi-device stack structure is formed in a single semiconductor die, and wherein the at least two transistors include at least one of one or more P-type transistors and one or more N-type transistors that are formed within the single semiconductor die (“each of the first NMOS stack (MS01-MS04) and the second PMOS stack (MS11-MS14)” ¶ [0039]),
However, Wu et al., does not disclose, wherein the multi-bit circuit architecture is a three-dimensional (3D) circuit architecture.
In the similar field of endeavor of semiconductor devices, Liu et al. Fig. 4 discloses, wherein the multi-bit circuit architecture is a three-dimensional (3D) circuit architecture (“The structure 60 is shown in the X-axis and Z-axis directions while the Y-axis direction is orthogonal to the plane of the cross-section illustrated in FIG. 4.” ¶ [0040]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the transistors structure of Wu et al, using the structure of Liu et al. in order to implementing DMUX devices (Liu et al. ¶ [0040]).
With Regard to Claim 8, Wu et al. discloses the limitations of claim 6 as discussed above. Wu et al., 2A-4B, further discloses, wherein the at least two transistors are arranged vertically in a multi- transistor stack configuration that includes at least one multi-device stack configuration of at least one of one or more P-type transistors and one or more N-type transistors, and wherein the one or more P-type transistors are P-type field-effect transistors (PFETs), and wherein the one or more N-type transistors are N-type field-effect transistors (NFETs) (“the high stack (310) comprises PMOS FET transistors (MS11-MS16) arranged in a stacked configuration as depicted in FIG. 4A, and the low stack (315) comprises NMOS FET transistors (MS01-MS06) arranged in a stacked configuration as depicted in FIG. 4B.” ¶ [0049]).
However, Wu et al., does not disclose, wherein the multi-bit circuit architecture comprises a multi-bit memory cell for use in random access memory (RAM) applications.
In the similar field of endeavor of semiconductor devices, Liu et al. Figs. 1-13 discloses, wherein the multi-bit circuit architecture comprises a multi-bit memory cell for use in random access memory (RAM) applications (“The CPU 20 may comprise any type of electronic data processor, and the memory 22 may comprise any type of system memory, such as static random-access memory (SRAM), dynamic random-access memory (DRAM), or read-only memory (ROM).” ¶ [0025]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the transistors structure of Wu et al, using the structure of Liu et al. in order to implement an EDA system in accordance with various processes (Liu et al. ¶ [0024]) and to implementing DMUX devices (Liu et al. ¶ [0040]).
Claims 16 is rejected under 35 U.S.C. 103 as being unpatentable over Liu, Chi-Lin (US 20200395938 A1) “Liu et al.” in view of Liebmann, Lars (US 20200135718 A1) “Liebmann et al.”.
With Regard to Claim 16, Liu et al. discloses the limitations of claim 10. Liu et al. Figs. 1-13 further discloses, wherein the multi-transistor stack configuration includes a multi-device stack configuration of at least one of one or more P- type transistors (“PMOS transistors” ¶ [0062]) and one or more N-type transistors (“NMOS transistors” ¶ [0061]).
However, Liu et al. does not disclose, at least one of a P-over-N- over-N-over-P (PNNP) stack configuration, a N-over-P-over-P-over-N (NPPN) stack configuration, a P-over-N-over-P-over-N (PNPN) stack configuration, and a N-over-P-over- N-over-P (NPNP) stack configuration.
In the similar field of endeavor of semiconductor devices, Liebmann et al., Figs. 5-8 further discloses at least one of a P-over-N-over-N-over-P (PNNP) stack configuration, a N-over-P-over-P-over-N (NPPN) stack configuration (“stack orientation (i.e. n-over-p, then p-over-n)” ¶ [0047]), a P-over-N-over-P-over-N (PNPN) stack configuration, and a N-over-P-over-N-over-P (NPNP) stack configuration.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify stack configuration of Liu et al. with the N-over-P-over-P-over-N configuration of Liebmann et al. in order to improve process efficiency for implants and device type specific selective depositions as compared to maintaining a same stacking order for all device pairs in the stack (Liebmann et al., ¶ [0047]).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-5 and 17-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Liebmann, Lars (US 20200135718 A1) “Liebmann et al.”.
With Regard to Independent Claim 1, Liebmann et al. Figs. 5-8 discloses a device (“3D IC” ¶ [0046]) comprising:
a multi-layered circuit architecture (“3D IC having three tiers” ¶ [0046]; “each tier of semiconductor devices may include vertically stacked semiconductor devices” ¶ [0045]),
having a first circuit layer formed by a first set of multi-device stack structures (“first tier of transistors includes SD region 505P and SD region 505N of respective p-type and n-type devices,” ¶ [0046]) and
a second circuit layer formed by a second set of multi-device stack structures (“a second tier includes SD region 507N and SD region 507P of respective p-type and n-type devices” ¶ [0046])
wherein the first circuit layer and the second circuit layer each includes a sole logic circuit (“a plurality of stacked complementary FET devices, with the stacked complementary FETS repeated within” ¶ [0054]) or a sole memory circuit of a same type;
each the multi-device stack structure of the first set and the second set of multi- device stack structures is stacked together and arranged vertically at different vertical positions within a single vertical stack (Fig. 5 shows 505P and 505N form a complementary pair, SD regions 507N and 507P form a complementary pair and stacked together and arranged vertically at different vertical positions within a single vertical stack) and has at least two transistors (); and
the at least two transistors are arranged vertically in a multi-transistor stack configuration (“SD regions 505P and 505N form a complementary pair, SD regions 507N and 507P form a complementary pair, and SD regions 509P and 509N form another complementary pair.” ¶ [0047]).
With Regard to Claim 3, Liebmann et al. discloses the limitations of claim 1 as discussed above. Liebmann et al., Figs. 5-8, further discloses the multi-layered circuit architecture is used for at least one of bitcells, inverters, NANO gates, NOR gates and AND-OR-Invert (AOI) gates (“FIGS. 5 and 6 provides a lower tier implementing an AOI logic cell” ¶ (0054)).
With Regard to Claim 4, Liebmann et al. discloses the limitations of claim 1 as discussed above. Liebmann et al., Figs. 5-8, further discloses the multi-transistor stack configuration (“the stacked transistor pairs are configured in an alternating stack orientation by doping type of the transistors.” ¶ [0047]) includes a multi-device stack configuration of at least one of one or more P-type transistors and one or more N-type transistors arranged (“In the embodiment of FIG. 5, SD region 505P is part of a p-type transistor, while its complement 505N is of an n-type transistor. Similarly, SD region 507N is of n-type and its complement 507P is of p-type” ¶ [0047]) in at least one of a P-over-N-over-N-over-P (PNNP) stack configuration, a N-over-P-over-P-over-N (NPPN) stack configuration (“stack orientation (i.e. n-over-p, then p-over-n)” ¶ [0047]), a P-over-N-over-P-over-N (PNPN) stack configuration and a N-over-P-over-N-over-P (NPNP) stack configuration.
With Regard to Claim 5, Liebmann et al. discloses the limitations of claim 1 as discussed above. Liebmann et al., Figs. 5-8, further discloses the multi-transistor stack configuration (“the stacked transistor pairs are configured in an alternating stack orientation by doping type of the transistors.” ¶ [0047]) includes a multi-device stack configuration of at least one of one or more P-type transistors and one or more N-type transistors (“In the embodiment of FIG. 5, SD region 505P is part of a p-type transistor, while its complement 505N is of an n-type transistor. Similarly, SD region 507N is of n-type and its complement 507P is of p-type” ¶ [0047]), and wherein the P-type transistors are P-type field-effect transistors (PFETs), and wherein the N-type transistors are N-type field-effect transistors (NFETs) (“FIGS. 7 and 8 provide planar views of the a lower tier of the IC of FIGS. 5 and 6 implementing an AO122 logic cell formed of a plurality of stacked complementary FET devices, with the stacked complementary FETS repeated within the lower tier” ¶ [0054]; “FETs may be n-type or p-type FETS that are arranged along the substrate surface or stacked vertically over one another along the thickness direction of the substrate” ¶ [0033] ).
With Regard to Claim 17, Liebmann et al. discloses the limitations of claim 1. Liebmann et al. further discloses, wherein the multi-transistor stack configuration includes nano-sheet field-effect transistors (nano-sheet FETs) (“gate region 557 is a gate-all-around (GAA) structure which surrounds channel regions 505P-C and 5095N-C of the devices in the lower tier, and gate region 567 is a GAA structure which surrounds channel regions 507N-C and 507P-C of the devices in the middle tier as shown. Gate region 568 is a gate-all-around (GAA) structure which surrounds channel regions 509P-C and 509N-C of the devices in the upper tier. The channel 511P-C includes GAA structure 570, which serves as a passgate for an SRAM circuit implemented by the upper tier of three stacked transistors.” ¶ [0051]) or fin field-effect transistors (FinFETs) devices.
With Regard to Claim 18, Liebmann et al. discloses the limitations of claim 1, Liebmann et al. further discloses, wherein the multi-layered circuit architecture includes vertically aligned inter-layer vias electrically coupling the first circuit layer and the second circuit layer (“Several local interconnects to electrically connect the semiconductor devices as necessary to form functional circuits.” ¶ [0049]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Liebmann, Lars (US 20200135718 A1) “Liebmann et al.” in view of Wu, Gary Chunshien (US 20170264288 A1) “Wu et al.”.
With Regard to Independent Claim 6, Liebmann et al. Figs. 5-8 discloses a device (“3D IC” ¶ [0046]) comprising:
a multi-device stack structure 500 (“structure 500” ¶ [0046]) for use in multi-bit circuit architecture (“structure 500 includes vertically stacked semiconductor devices, with such stack repeated laterally along the substrate surface to form complex cells for implementing a functional circuit such as a memory” ¶ [0053]) formed with complementary field effect transistor (CFET) technology (“a plurality of stacked complementary FET devices, with the stacked complementary FETS” ¶ [0054]),
wherein the multi-device stack structure 500 has at least two transistors, wherein the at least two transistors are arranged vertically (“each tier of semiconductor devices may include vertically stacked semiconductor devices” ¶ [0045]).
However, Liebmann et al. does not disclose, wherein the at least two transistors are arranged vertically in one or more of at least four transistor stack configurations.
In the similar field of endeavor of semiconductor devices, Wu et al. Figs. 2A-4B discloses wherein the at least two transistors are arranged vertically in one or more of at least four transistor stack configurations (“the first stack and the second stack of the inverter (110B) each comprise four transistors” ¶ [0039]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the transistors structure of Liebmann et al., using the structure of Wu et al, in order to function as an inverter operating from a supply voltage higher than a voltage handling capability of any of the individual transistors in the stacks (Wu et al. ¶ [0029]).
With Regard to Claim 7, Liebmann et al. discloses the limitations of claim 6 as discussed above. Liebmann et al., Figs. 5-8 further discloses the multi-device stack structure 500 is formed in a single semiconductor die 501 (“a monolithic semiconductor substrate having a generally planar substrate surface 501” ¶ [0046]), and wherein the at least one of the one or more P-type transistors and the one or more N-type transistors are formed within the single semiconductor die 501 (“structure 500 represents a portion of a monolithic semiconductor substrate having a generally planar substrate surface 501” ¶ [0046]), and wherein the multi-bit circuit architecture is a three-dimensional (3D) circuit architecture (“3D IC having three tiers” ¶ [0046]).
With Regard to Claim 8, Liebmann et al. discloses the limitations of claim 6 as discussed above. Liebmann et al., Figs. 5-8 further discloses the multi-bit memory architecture 500 comprises a multi-bit memory cell (“an upper tier implementing an SRAM cell.” ¶ [0054]) for use in random access memory (RAM) applications (“an SRAM circuit implemented by the upper tier of three stacked transistors” ¶ [0051]), and wherein the multi-transistor stack configuration (“the stacked transistor pairs are configured in an alternating stack orientation by doping type of the transistors.” ¶ [0047]) includes at least one multi-device stack configuration of the at least one of the one or more P-type transistors and the one or more N-type transistors (“In the embodiment of FIG. 5, SD region 505P is part of a p-type transistor, while its complement 505N is of an n-type transistor. Similarly, SD region 507N is of n-type and its complement 507P is of p-type” ¶ [0047]), and wherein the one or more P-type transistors are P-type field-effect transistors (PFETs), and wherein the one or more N-type transistors are N-type field-effect transistors (NFETs) (“FIGS. 7 and 8 provide planar views of the a lower tier of the IC of FIGS. 5 and 6 implementing an AO122 logic cell formed of a plurality of stacked complementary FET devices, with the stacked complementary FETS repeated within the lower tier” ¶ [0054]; “FETs may be n-type or p-type FETS that are arranged along the substrate surface or stacked vertically over one another along the thickness direction of the substrate” ¶ [0033]).
With Regard to Claim 9, Liebmann et al. discloses the limitations of claim 6 as discussed above. Liebmann et al., does not disclose the one or more at least four transistor multi-transistor stack configuration includes a multi-device stack configuration of the at least one of the one or more P-type transistors and the one or more N-type transistors, arranged in at least one of a P-over-N-over-N-over-P (PNNP) stack configuration, a N-over-P-over-P-over-N (NPPN) stack configuration, a P-over-N-over-P-over-N (PNPN) stack configuration, and a N-over-P-over-N-over-P (NPNP) stack configuration.
Liebmann et al., Figs. 5-8 further discloses the one or more at least two transistor multi-transistor stack configuration (“the stacked transistor pairs are configured in an alternating stack orientation by doping type of the transistors.” ¶ [0047]) includes a multi-device stack configuration of the at least one of the one or more P-type transistors and the one or more N-type transistors (“In the embodiment of FIG. 5, SD region 505P is part of a p-type transistor, while its complement 505N is of an n-type transistor. Similarly, SD region 507N is of n-type and its complement 507P is of p-type” ¶ [0047]), arranged in at least one of a P-over-N-over-N-over-P (PNNP) stack configuration, a N-over-P-over-P-over-N (NPPN) stack configuration (“stack orientation (i.e. n-over-p, then p-over-n)” ¶ [0047]), a P-over-N-over-P-over-N (PNPN) stack configuration, and a N-over-P-over-N-over-P (NPNP) stack configuration.
Claims 10-11 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Liebmann, Lars (US 20200135718 A1) “Liebmann et al.” in view of Liu, Chi-Lin (US 20200395938 A1) “Liu et al.”.
With Regard to Independent Claim 10, Liebmann et al. Figs. 5-8 discloses a device (“3D IC” ¶ [0046]) comprising: a plurality of multi-device stack structures stacked together and arranged vertically in a single vertical stack for use in multi-bit circuit architecture (Fig. 5 shows 505P and 505N form a complementary pair, SD regions 507N and 507P form a complementary pair and stacked together and arranged vertically at different vertical positions within a single vertical stack), wherein each multi- device stack structure of the plurality of multi-device stack structures has at least two transistors (Fig. 5 shows 505P and 505N form a complementary pair, SD regions 507N and 507P form a complementary pair), wherein the at least two transistors are arranged vertically in a multi-transistor stack configuration (Fig. 5 shows 505P and 505N form a complementary pair, SD regions 507N and 507P are vertically stacked),
However, Liebmann et al. does not disclose, wherein different subsets include one or more multi-device stack structures of the plurality of multi-device stack structures, and wherein the different subsets are electrically grouped to form different respective logic or respective memory circuits.
In the similar field of endeavor of stacked semiconductor devices, Liu et al. Figs. 1-13 discloses, wherein different subsets include one or more multi-device stack structures of the plurality of multi-device stack structures, and wherein the different subsets are electrically grouped to form different respective logic or respective memory circuits (“The DMUX4 circuit 100 includes an eight-input AND-OR (AO2222) logic circuit 102 and an inverter 104 that together are implemented by 18 transistors.” ¶ [0042]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the transistors structure of Liebmann et al, using the structure of Liu et al. in order to implement an EDA system in accordance with various processes (Liu et al. ¶ [0024]) and to implementing DMUX devices (Liu et al. ¶ [0040]).
With Regard to Claim 11, Liebmann et al. as modified by Liu et al. discloses the limitations of claim 10 as discussed above. Liebmann et al., Figs. 5-8 further discloses, wherein the plurality of multi-device stack structures are formed in a single monolithic semiconductor die(“a monolithic semiconductor substrate having a generally planar substrate surface 501” ¶ [0046]), and wherein the at least two transistors include at least one of one or more P-type transistors and one or more N-type transistors are formed within the single monolithic semiconductor die (Fig. 5 shows 505P and 505N form a complementary pair, SD regions 507N and 507P form a complementary pair and are within the single monolithic semiconductor die), and wherein the multi- bit circuit architecture is a three-dimensional (3D) circuit architecture (“structure 500 represents a portion of a monolithic semiconductor substrate having a generally planar substrate surface 501” ¶ [0046]), and wherein the logic architecture is a three-dimensional (3D) circuit architecture (“3D IC having three tiers” ¶ [0046]), and
However, Liebmann et al. does not disclose, wherein at least one of the different subsets includes two or more multi-device stack structures of the plurality of multi-device stack structures that are non-contiguous within the single common vertical stack.
In the similar field of endeavor of stacked semiconductor devices, Liu et al. Figs. 1-13 discloses, wherein at least one of the different subsets includes two or more multi-device stack structures of the plurality of multi-device stack structures that are non-contiguous within the single common vertical stack (“An interconnect layer 64 includes N (e.g., an integer number of) conductive layers (e.g., metal layers M1 to MN) used for interconnecting devices within layers in interconnect layer 64 and for forming electrical connections to external devices, etc. The interconnect layer 64 generally includes vias, inter-level dielectric materials, passivation layers, bonding pads, packaging resources, etc. Each metal (e.g., conductive) layer M in the interconnect layer 64 is commonly called metal one, metal two, metal three (M1, M2, M3, etc) layers, etc. Between the various metal layers M are dielectric materials (e.g., high-K, low-K material, etc.) 66 used to insulate the metal layers M.” ¶ [0041]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the transistors structure of Liebmann et al, using the structure of Liu et al. in order to implement an EDA system in accordance with various processes (Liu et al. ¶ [0024]) and to implementing DMUX devices (Liu et al. ¶ [0040]).
With Regard to Claim 15, Liebmann et al. as modified by Liu et al. discloses the limitations of claim 10 as discussed above. Liebmann et al., Figs. 5-8 further discloses the multi-bit circuit architecture comprises a multibit AND-OR-Invert gate for use in integrated circuits, and wherein the multi-transistor stack configuration (“the stacked transistor pairs are configured in an alternating stack orientation by doping type of the transistors.” ¶ [0047]) includes a multi-device stack configuration (“lower and middle tiers include two stacked transistors each” ¶ [0046]) of the at least one of the one or more P-type transistors and the one or more N-type transistors (“In the embodiment of FIG. 5, SD region 505P is part of a p-type transistor, while its complement 505N is of an n-type transistor. Similarly, SD region 507N is of n-type and its complement 507P is of p-type” ¶ [0047]), and wherein the one or more P-type transistors are P-type field-effect transistors (PFETs), and wherein the one or more N-type transistors are N-type field-effect transistors (NFETs) (“FIGS. 7 and 8 provide planar views of the a lower tier of the IC of FIGS. 5 and 6 implementing an AO122 logic cell formed of a plurality of stacked complementary FET devices, with the stacked complementary FETS repeated within the lower tier” ¶ [0054]; “FETs may be n-type or p-type FETS that are arranged along the substrate surface or stacked vertically over one another along the thickness direction of the substrate” ¶ [0033]).
With Regard to Claim 16, Liebmann et al. as modified by Liu et al. discloses the limitations of claim 10 as discussed above. Liebmann et al., Figs. 5-8 further discloses the multi-transistor stack configuration (“the stacked transistor pairs are configured in an alternating stack orientation by doping type of the transistors.” ¶ [0047]) includes a multi-device stack configuration (“lower and middle tiers include two stacked transistors each” ¶ [0046]) of the at least one of the one or more P-type transistors and the one or more N-type transistors (“In the embodiment of FIG. 5, SD region 505P is part of a p-type transistor, while its complement 505N is of an n-type transistor. Similarly, SD region 507N is of n-type and its complement 507P is of p-type” ¶ [0047]), arranged in at least one of a P-over-N-over-N-over-P (PNNP) stack configuration, a N-over-P-over-P-over-N (NPPN) stack configuration (“stack orientation (i.e. n-over-p, then p-over-n)” ¶ [0047]), a P-over-N-over-P-over-N (PNPN) stack configuration, and a N-over-P-over-N-over-P (NPNP) stack configuration.
Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Liebmann, Lars (US 20200135718 A1) “Liebmann et al.” in view of Liu, Chi-Lin (US 20200395938 A1) “Liu et al.” further in view of Zhang, Chen (US 20190229117 A1) “Zhang et al.”.
With Regard to Claim 12, Liebmann et al. as modified by Liu et al. discloses the limitations of claim 10 as discussed above. Liebmann et al., Figs. 5-8 further discloses the multi-transistor stack configuration (“the stacked transistor pairs are configured in an alternating stack orientation by doping type of the transistors.” ¶ [0047]) includes a multi-device stack configuration (“lower and middle tiers include two stacked transistors each” ¶ [0046]) of the at least one of the one or more P-type transistors and the one or more N-type transistors (“In the embodiment of FIG. 5, SD region 505P is part of a p-type transistor, while its complement 505N is of an n-type transistor. Similarly, SD region 507N is of n-type and its complement 507P is of p-type” ¶ [0047]), and wherein the one or more P-type transistors are P-type field-effect transistors (PFETs), and wherein the one or more N-type transistors are N-type field-effect transistors (NFETs) (“a plurality of stacked complementary FET devices, with the stacked complementary FETS repeated within the lower tier” ¶ [0054]; “FETs may be n-type or p-type FETS that are arranged along the substrate surface or stacked vertically over one another along the thickness direction of the substrate” ¶ [0033]).
However, Liebmann et al. does not disclose the multi-bit logic architecture comprises a multilayer inverter standard cell for use in integrated circuits.
In the similar field of endeavor 3D monolithic stacked FET, Zhang et al. Fig. 12-16 discloses, the multi-bit logic architecture (“stacked VTFET, i.e., one top VTFET and one bottom VTFET.” ¶ [0055]) comprises a multilayer inverter standard cell (“the inverter stack can include a top NFET and a bottom PFET, or a top PFET and a bottom NFET” ¶ [0055]) for use in integrated circuits (“stacked VTFET devices” ¶ [0039]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the logic gate of Liebmann et al. with the inverter gate of Zhang et al. in order to derive a single output (Zhang et al., ¶ [0039]) specific to an inverter (“An inverter (a NOT gate) flips the input, i.e., input 1, output 0, or vice versa.” ¶ [0039]).
With Regard to Claim 13, Liebmann et al. as modified by Liu et al. discloses the limitations of claim 10 as discussed above. Liebmann et al., Figs. 5-8 further discloses the multi-transistor stack configuration (“the stacked transistor pairs are configured in an alternating stack orientation by doping type of the transistors.” ¶ [0047]) includes a multi-device stack configuration (“lower and middle tiers include two stacked transistors each” ¶ [0046]) of the at least one of the one or more P-type transistors and the one or more N-type transistors (“In the embodiment of FIG. 5, SD region 505P is part of a p-type transistor, while its complement 505N is of an n-type transistor. Similarly, SD region 507N is of n-type and its complement 507P is of p-type” ¶ [0047]), and wherein the one or more P-type transistors are P-type field-effect transistors (PFETs), and wherein the one or more N-type transistors are N-type field-effect transistors (NFETs) (“a plurality of stacked complementary FET devices, with the stacked complementary FETS repeated within the lower tier” ¶ [0054]; “FETs may be n-type or p-type FETS that are arranged along the substrate surface or stacked vertically over one another along the thickness direction of the substrate” ¶ [0033]).
However, Liebmann et al. does not disclose the multi-bit logic architecture comprises a multibit NAND gate for use in integrated circuits.
In the similar field of endeavor 3D monolithic stacked FET, Zhang et al. Fig. 1-5 discloses, the multi-bit logic architecture (“a stacked VTFET” ¶ [0040]) comprises a multilayer NAND gate (“NAND gate will be formed by a pair of stacked VTFETs, i.e., two top VTFETs and two bottom VTFETs” ¶ [0040]) for use in integrated circuits (“stacked VTFET devices” ¶ [0039]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the logic gate of Liebmann et al. with the NAND gate of Zhang et al. in order to derive a single output (Zhang et al., ¶ [0039]) specific to a NAND gate (“A NAND gate, for instance, will output a logic 0 only if all of its inputs have a value of 1, otherwise the NAND gate will output a logic 1” ¶ [0039]).
With Regard to Claim 14, Liebmann et al. as modified by Liu et al. discloses the limitations of claim 10 as discussed above. Liebmann et al., Figs. 5-8 further discloses the multi-transistor stack configuration (“the stacked transistor pairs are configured in an alternating stack orientation by doping type of the transistors.” ¶ [0047]) includes a multi-device stack configuration (“lower and middle tiers include two stacked transistors each” ¶ [0046]) of the at least one of the one or more P-type transistors and the one or more N-type transistors (“In the embodiment of FIG. 5, SD region 505P is part of a p-type transistor, while its complement 505N is of an n-type transistor. Similarly, SD region 507N is of n-type and its complement 507P is of p-type” ¶ [0047]), and wherein the one or more P-type transistors are P-type field-effect transistors (PFETs), and wherein the one or more N-type transistors are N-type field-effect transistors (NFETs) (“a plurality of stacked complementary FET devices, with the stacked complementary FETS repeated within the lower tier” ¶ [0054]; “FETs may be n-type or p-type FETS that are arranged along the substrate surface or stacked vertically over one another along the thickness direction of the substrate” ¶ [0033]).
However, Liebmann et al. does not disclose the multi-bit logic architecture comprises a multibit NOR gate for use in integrated circuits.
In the similar field of endeavor 3D monolithic stacked FET, Zhang et al. Fig. 6-11 discloses, the multi-bit logic architecture (“a stacked VTFET” ¶ [0047]) comprises a multilayer NOR gate (“the NOR gate will be formed by a pair of stacked VTFETs, i.e., two top VTFETs and two bottom VTFETs.” ¶ [0047]) for use in integrated circuits (“stacked VTFET devices” ¶ [0039]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the logic gate of Liebmann et al. with the NOR gate of Zhang et al. in order to derive a single output (Zhang et al., ¶ [0039]) specific to a NOR gate (“A NOR gate will output a logic 1 only if all of its inputs have a value of 0, otherwise the NOR gate will output a logic 0.” ¶ [0039]).
Conclusion
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/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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