DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-5, 7-9, 11-22, 24, and 25 are pending.
Claims 1 and 22 are amended.
Claims 6, 8, 10, and 23 are cancelled.
Claims 15-21 are withdrawn.
Applicant is reminded, as discussed in the office actions dated 01/14/2026 and 03/19/2026, as well as in a phone call with Justin Brask on 12/10/2025, in regards to claim 8, which currently reads (Original) with no further claim language, that this claim should be cancelled in any further amended claim filings. The claim will be treated as cancelled in this action. Applicant is requested to confirm this status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/09/2026 has been entered.
Response to Arguments
Applicant’s arguments, see pages 8-11, filed 04/09/2026, with respect to the rejection(s) of amended independent claims 1 and 22 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. Accordingly, the rejections of dependent claims 2-5, 7, 9,11-14, 24, and 25, are withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kuang et al. (US PGPub 2022/0278196).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 6, 9, 13, 14, 22, 24, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Ando et al. (US PGPub 2019/0157386; herein known as Ando) in view of Kuang et al. (US PGPub 2022/0278196; herein known as Kuang).
Regarding claim 1, Ando teaches (annotated Fig. 1a below) an apparatus comprising: a substrate (5, [0028]) that includes silicon ([0028]); a layer (6, [0029]) with a first side (S1)and a second side (S2) opposite the first side, the first side of the layer on a side of the substrate; a scaffold (7A, [0027])extending from a portion of the substrate proximate (Pside) to the side of the substrate through at least a portion of the layer, wherein a first edge of the scaffold is adjacent to a portion of the substrate and wherein a second edge of the scaffold opposite the first edge of the scaffold is distal (Dside) from the substrate; and a stack of semiconductor layers (6, 8, [0027]) on the second edge of the scaffold, wherein the first layers and the second layers are in direct contact and wherein the edges are in vertical alignment (see annotated figure below).
Ando does not explicitly teach the 2D semiconductor layers each having a first thickness and comprising a transition metal dichalcogenide (TMD) material, and the 3D semiconductor layers each having a second thickness and including a material comprising silicon and germanium.
Kuang teaches (Fig. 3) the 2D semiconductor layers (16, [0017]) each having a first thickness ([0021]) and comprising a transition metal dichalcogenide (TMD) material ([0018]), and the 3D semiconductor layers (14, [0017]) each having a second thickness ([0022]) and including a material comprising silicon and germanium ([0017]).
Because Ando and Kuang are both directed toward nanosheet transistors, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include teach the 2D semiconductor layers each having a first thickness and comprising a transition metal dichalcogenide (TMD) material, and the 3D semiconductor layers each having a second thickness and including a material comprising silicon and germanium in order to enable selective etching of the sacrificial 3D semiconductor layer in relation to the 2D channel layer during manufacturing processes (Kuang, [0063]).
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Regarding claim 2, Ando in view of Kuang teaches (Fig. 1a) the apparatus of claim 1, wherein each of the 2D semiconductor layers (8) is a single crystal 2D semiconductor layer ([0026]).
Regarding claim 3, Ando in view of Kuang teaches (annotated Fig. 1a, above) the apparatus of claim 2, wherein a bottommost one of the 2D semiconductor layers (8) is grown on the second edge of the scaffold (Dside).
Regarding claim 4, Ando in view of Kuang teaches (Fig. 1a) the apparatus of claim 1, wherein the scaffold (6) includes a semiconductor material ([0026]).
Regarding claim 5, Ando in view of Kuang teaches (Fig. 1a) the apparatus of claim 1, (Fig. 1B) wherein the scaffold forms a plane that is substantially perpendicular to a plane of the side of the substrate.
Regarding claim 7, Ando in view of Kuang teaches (Fig. 1a) the apparatus of claim 3, wherein a bottommost one of the 3D semiconductor layers (7) is grown on the bottommost one of the 2D semiconductor layers (8, [0036]).
Regarding claim 9, Ando in view of Kuang teaches (Fig. 1a) the apparatus of claim 1, wherein each of the 2D semiconductor layers (8, [0031]) has a same crystal orientation ([0031]).
Regarding claim 13, Ando in view of Kuang teaches (Fig. 1a) the apparatus of claim 1, wherein the scaffold (7a) is grown from the substrate (5, [0026]).
Regarding claim 14, Ando in view of Kuang teaches (Fig. 1a) the apparatus of claim 1, wherein the layer (6) on the substrate (5) includes silicon and oxygen ([0029]).
Regarding claim 22, Ando teaches (annotated Fig. 1a, below) a method comprising: providing a substrate (5, [0028]) that includes silicon; forming a scaffold (7a) on the substrate, the scaffold having a first edge (Pside) physically coupled with the substrate and a second edge (Dside) opposite the first edge; and forming a stack of semiconductor layers on the second edge of the scaffold, the stack of semiconductor layers comprising alternating 2D semiconductor layers (8, [0027]) and semiconductor layers (6, [0028]) and wherein the edges of the semiconductor materials are in vertical alignment (see annotated figure below).
Ando does not explicitly teach the 2D semiconductor layers each having a first thickness and comprising a transition metal dichalcogenide (TMD) material, and the 3D semiconductor layers each having a second thickness and including a material comprising silicon and germanium.
Kuang teaches (Fig. 3) the 2D semiconductor layers (16, [0017]) each having a first thickness ([0021]) and comprising a transition metal dichalcogenide (TMD) material ([0018]), and the 3D semiconductor layers (14, [0017]) each having a second thickness ([0022]) and including a material comprising silicon and germanium ([0017]).
Because Ando and Kuang are both directed toward nanosheet transistors, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include teach the 2D semiconductor layers each having a first thickness and comprising a transition metal dichalcogenide (TMD) material, and the 3D semiconductor layers each having a second thickness and including a material comprising silicon and germanium in order to enable selective etching of the sacrificial 3D semiconductor layer in relation to the 2D channel layer during manufacturing processes (Kuang, [0063]).
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Regarding claim 24, Ando in view of Kuang teaches (annotated Fig. 1a, above) the method of claim 22, wherein forming a scaffold on the substrate further includes: forming a layer (6) on the substrate, the layer having a first side on the substrate (S1) and a second side (S2) of the layer opposite the first side; etching a trench (not pictured, [0027]) from the second side of the layer through the first side of the layer and into a portion of the substrate; and forming the scaffold within the etched trench ([0027]).
Regarding claim 25, Ando in view of Kuang teaches (Fig. 1a) the method of claim 24, wherein forming the scaffold (7a) within the etched trench (not pictured, [0027]) further includes growing the scaffold within the etched trench from a surface of the substrate (5, [0027]).
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Ando in view of Kuang, as applied to claim 1 above, in view of Glass et al. (US PGPub 2020/0091287), herein referred to as Glass.
Regarding claim 11, Ando in view of Kuang teaches (Fig. 1a) the apparatus of claim 1, wherein the scaffold is a first scaffold (6); and further comprising, wherein a first edge of the scaffold is adjacent to a portion of the substrate ([0063]).
Ando in view of Kuang does not explicitly teach a second scaffold extending from a portion of the substrate proximate to the side of the substrate through at least a portion of the layer, nor and wherein a second edge of the scaffold opposite the first edge of the scaffold is distal to the substrate; and a semiconductor layer on the second edge of the second scaffold.
Ando in view of Kuang teaches an exemplary structure of a nanosheet gate-all-around FET, the structure of which could be applied to the formation of multiple nanosheet GAA FET stacks.
Glass teaches (Fig. 7) a nanowire transistor structure containing multiple FET stacks, each containing their own scaffold structure (162, [0068]) and semiconductor layer (136, [0068]) on the edge of the scaffold.
A person of ordinary skill in the art would have understood that more than one FET stack would be formed for use in a semiconductor device, therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Ando in view of Kuang to include the multiple FET stacks of Glass in order to allow for creation of a CMOS device. See MPEP 2141.III(C).
Regarding claim 12, Ando in view of Kuang and further in view of Glass teaches (see annotated Fig. 7 below) the apparatus of claim 11, having the first scaffold (7a) and the second scaffold (not pictured, [0063]), wherein the first (S1) and second (S2) scaffold are substantially parallel with each other (Glass[0068]).
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY N FARMER whose telephone number is (703)756-1472. The examiner can normally be reached Monday-Friday 7:30-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EMILY FARMER/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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