DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Species-I (claim 1, 3-7, 10-12, 14, 15, 17-20 and 22-25) in the reply filed on 8/11/2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 4, 12-15, 17, 20, 22, 23 and 25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by NISHIOKA et al. (US PGpub: 2021/0057641 A1), hereinafter NISHIOKA.
Regarding claim 1, NISHIOKA teaches an integrated circuit apparatus comprising:
a plurality of metallization layers (1 & 5, Paragraph [0054], [0069]), each metallization layer on a different respective vertical plane within the apparatus;
a first logic circuit formed between a first metallization layer and a second metallization layer, the first logic circuit (2) comprising non-CMOS logic devices (Marked logic device is MESO devices which is spintronic logic device which is a non-CMOS device. No CMOS part present in this device) ; and
a second logic circuit formed between the second metallization layer and a third metallization layer (7), the second logic circuit comprising non-CMOS logic devices (Marked logic device is MESO devices which is spintronic logic device which is a non-CMOS device. No CMOS part present in this device).
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Regarding claim 3, NISHIOKA teaches the apparatus of claim 1, wherein the non-CMOS logic devices include spintronic logic devices (Marked logic device can be MESO devices which is spintronic logic device).
Regarding claim 4, NISHIOKA teaches the apparatus of claim 3, wherein the spintronic logic devices include magnetoelectric spin orbit (MESO) devices (Marked logic device can be MESO devices).
Regarding claim 12, NISHIOKA teaches a chip package comprising:
a package substrate (Bottom layers can be considered package substrate);
an integrated circuit die coupled to the package substrate, the integrated circuit die comprising:
a first logic circuit formed between a first metallization layer of the die and a second metallization layer of the die, the first logic circuit comprising non-CMOS logic devices (Marked logic device is MESO devices which is spintronic logic device which is a non-CMOS device. No CMOS part present in this device); and
a second logic circuit formed between the second metallization layer and a third metallization layer of the die, the second logic circuit comprising non-CMOS logic devices (Marked logic device is MESO devices which is spintronic logic device which is a non-CMOS device. No CMOS part present in this device);
wherein the first logic circuit is formed on a different vertical plane within the integrated circuit die than the second logic circuit (see marked Figure above).
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Regarding claim 14, NISHIOKA teaches the chip package of claim 12, wherein the non-CMOS logic devices include spintronic logic devices (Marked logic device are spintronic logic device).
Regarding claim 15, NISHIOKA teaches the chip package of claim 14, wherein the spintronic logic devices include magnetoelectric spin orbit (MESO) devices (Marked logic device can be MESO devices).
Regarding claim 17, NISHIOKA teaches the chip package of claim 12, wherein the integrated circuit die further comprises:
a third logic circuit formed between the first metallization layer and the second metallization layer, the third logic circuit comprising non-CMOS logic devices to receive an first output signal from the first logic circuit (each logic circuit has multiple layers, so , they can be considered third and fourth logic circuits. Each output signal will receive signal from each logic circuits anyway otherwise the circuit will not operate); and
a fourth logic circuit formed between the second metallization layer and the third metallization layer, the fourth logic circuit comprising non-CMOS logic devices to receive an output signal from the second logic circuit (each logic circuit has multiple layers, so , they can be considered third and fourth logic circuits. Each output signal will receive signal from each logic circuits anyway otherwise the circuit will not operate).
Regarding claim 20, NISHIOKA teaches a system comprising:
a processor comprising:
a plurality of metallization layers comprising voltage supply lines and signal lines, each metallization layer on a different respective vertical plane within the processor (see marked Figure above);
a plurality of logic circuits, each logic circuit comprising non-CMOS logic devices (Marked logic device is MESO devices which is spintronic logic device which is a non-CMOS device. No CMOS part present in this device) and formed between respective pairs of metallization layers (see marked Figure above).
Regarding claim 22, NISHIOKA teaches the system of claim 20, wherein the non-CMOS logic devices include spintronic logic devices (Marked logic device can be MESO devices. see marked Figure above)).
Regarding claim 23, NISHIOKA teaches the system of claim 20, wherein each set of logic circuits is formed on a different vertical plane within the processor (see FIG. 3A where both logic circuits are formed on different plane. Logic circuit descriptions are in Paragraph [0102]-[0105]).
Regarding claim 25, NISHIOKA teaches the system of claim 20, wherein the plurality of logic circuits comprise:
a first logic circuit formed between a first metallization layer of the processor and a second metallization layer of the processor, the first logic circuit comprising non-CMOS logic devices (Marked logic device is MESO devices which is spintronic logic device which is a non-CMOS device. No CMOS part present in this device); and
a second logic circuit formed between the second metallization layer and a third metallization layer of the processor, the second logic circuit comprising non-CMOS logic devices (Marked logic device is MESO devices which is spintronic logic device which is a non-CMOS device. No CMOS part present in this device).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-7, 10, 11, 18, 19 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over NISHIOKA et al. (US PGpub: 2021/0057641 A1), hereinafter NISHIOKA, in view of Sato et al (US PGpub: 2019/0019944 A1), hereinafter Sato.
Regarding claim 5, NISHIOKA teaches the apparatus of claim 3, wherein at least one spintronic logic device comprises:
an electrically conductive layer (see marked Figure above);
a ferromagnetic layer (see marked Figure above);
a magnetoelectric layer disposed at least partially between the electrically conductive layer and the ferromagnetic layer (see marked Figure above).
NISHIOKA does not explicitly teach a spin orbit coupling (SOC) material; and a non-magnetic electrical conductor at least partially between the SOC material and the ferromagnetic layer.
Sato teaches a spin orbit coupling (SOC) material; and a non-magnetic electrical conductor at least partially between the SOC material and the ferromagnetic layer (see FIG. 12 and description).
Hence, It would have been obvious to one of ordinary skill in the art at the time of the invention was made to use NISHIOKA’s apparatus to modify with teachings from Sato in order to have higher thermal stability factor and a magnetic memory.
Regarding claim 6, NISHIOKA teaches the apparatus of claim 3, in Paragraph [0054]-[0080], wherein at least one spintronic logic device comprises:
an electrically conductive layer (see marked Figure above. Also, Paragraphs [0054]-[0080]);
a first ferromagnetic layer; a second ferromagnetic layer (see marked Figure above);
a magnetoelectric layer disposed at least partially between the electrically conductive layer and the first ferromagnetic layer (see marked Figure above);
an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer;
NISHIOKA does not explicitly teach a spin orbit coupling (SOC) material; and a non-magnetic electrical conductor at least partially between the SOC material and the ferromagnetic layer.
Sato teaches a spin orbit coupling (SOC) material; and a non-magnetic electrical conductor at least partially between the SOC material and the ferromagnetic layer.. Hence, It would have been obvious to one of ordinary skill in the art at the time of the invention was made to use NISHIOKA’s apparatus to modify with teachings from Sato in order to have higher thermal stability factor and a magnetic memory.
Regarding claim 7, NISHIOKA teaches the apparatus of claim 6, wherein the electrically conductive layer is a first electrically conductive layer, the apparatus further comprises a second electrically conductive layer, and the first ferromagnetic layer (CoFe) and the magnetoelectric layer are between the first electrically conductive layer and the second electrically conductive layer (see marked Figure above. Also, Paragraphs [0054]-[0080]).
Regarding claim 10, NISHIOKA in view of Sato teaches the apparatus of claim 1, further comprising: a third logic circuit formed between the first metallization layer (each logic circuit has multiple layers, so , they can be considered third and fourth logic circuits) and the second metallization layer, the third logic circuit comprising non-CMOS logic devices to receive an output signal from the first logic circuit; and a fourth logic circuit formed between the second metallization layer and the third metallization layer, the fourth logic (each logic circuit has multiple layers, so , they can be considered third and fourth logic circuits) circuit comprising non-CMOS logic devices to receive an output signal from the second logic circuit (Paragraph [0074]-[0076] in Sato who teaches voltage supply) .
Regarding claim 11, NISHIOKA in view of Sato teaches the apparatus of claim 1, wherein each metallization layer (See marked Figure above) comprises voltage supply lines and signal lines, the voltage supply lines of the metallization layers (See marked Figure above)include a first set of voltage supply lines to carry a first voltage and a second set of voltage supply lines to carry a second voltage, the first set of voltage supply lines and second set of voltage supply lines are not routed in the same metallization layer (Paragraph [0074]-[0076] in Sato who teaches voltage supply).
Regarding claim 18, NISHIOKA in view of Sato teaches the chip package of claim 12, wherein each metallization layer (See marked Figure above) comprises voltage supply lines and signal lines, the voltage supply lines of the metallization layers (See marked Figure above) comprising a first set of voltage supply lines to carry a first voltage and a second set of voltage supply lines to carry a second voltage, wherein the first set of voltage supply lines and second set of voltage supply lines are not routed in the same metallization layer (Paragraph [0074]-[0076] in Sato who teaches voltage supply).
Regarding claim 19, NISHIOKA in view of Sato teaches the chip package of claim 18, wherein the voltage supply lines connect to electrical connections on a side of the integrated circuit die opposite a side of the integrated circuit die coupled to the package substrate (Paragraph [0074]-[0076] in Sato who teaches voltage supply).
Regarding claim 24, NISHIOKA does not explicitly teach the system of claim 20, wherein the voltage supply lines comprise a first set of voltage supply lines to carry a first voltage and a second set of voltage supply lines to carry a second voltage, wherein the first set of voltage supply lines and second set of voltage supply lines are routed in different metallization layers (Paragraph [0054]-[0080]).
Sato teaches voltage supply lines comprise a first set of voltage supply lines to carry a first voltage and a second set of voltage supply lines to carry a second voltage, wherein the first set of voltage supply lines and second set of voltage supply lines are routed in different metallization layers (Paragraph [0074]-[0076]).
Hence, It would have been obvious to one of ordinary skill in the art at the time of the invention was made to use NISHIOKA’s apparatus to modify with teachings from Sato in order to have higher thermal stability factor and a magnetic memory.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See form PTO-892.
Similar references are US 2021/0329784 A1 (PARK et al.) and US 2017/0178705A1 Buhrman et al. could have been used for independent claims 1, 12 and 20
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached on M-F, 8am-6pm EDT.
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/SHEIKH MARUF/Primary Examiner, Art Unit 2897