DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/26/2026 has been entered.
Response to Amendment
The amendment filed on 01/26/2026, has been accepted and entered. Claims 1-9 and 23-25 remain pending in this application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 20210359091 A1-Hsu91) in view of Chiu et al. (US 20210335783-Chiu83).
Regarding Claim 1: Hsu91 discloses a semiconductor device (Title), comprising:
a semiconductor substrate (Semiconductor Substrate 204-Examiner’s annotated Fig 20B, [0014] L14-15);
a non-planar transistor (non-planar transistor 200-Examiner’s annotated Fig 20B)with
a source and a drain over the semiconductor substrate (Source/Drain 260 over substrate 204-Examiner’s annotated Fig 20B);
a backside contact to the source or the drain through the semiconductor substrate (Backside S/D contact 282 going through substrate 204-Examiner’s annotated Fig 20B)
such that the backside contact is in a same horizontal plane as the semiconductor substrate (Backside S/D contact 282 going through substrate 204 and being is the same horizontal plane as substrate 204-Examiner’s annotated Fig 20B); and
a liner between the source or the drain and the backside contact (Liner 280 between source/drain 260 and backside contact 282-Examiner’s annotated Fig 20B).
Hsu91 does not disclose a semiconductor device comprising:
a residual liner,
wherein the residual liner does not extend entirely across an interface between the backside contact and the source or the drain.
Chiu83 teaches a semiconductor device comprising:
a residual liner (residual liner 94 between source or drain 92 and backside contact 112-See Examiner's annotated Fig 38B),
wherein the residual liner does not extend entirely across an interface between the backside contact and the source or the drain (Residual liner 94 does not extend entirely across an interface between Source/drain 92 and backside contact 112-See Examiner's annotated Fig 38B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Hsu91 as taught by Chiu83 for the purpose of reducing parasitic capacitance by performing backside etching/trimming processes on gate structures and epitaxial source/drain regions of semiconductor devices (Chiu83:[0009]).
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Regarding Claim 2: Hsu91 and Chiu83 combination discloses all the elements of claim 1, as noted above.
Chiu83 further discloses a semiconductor device (See examiner’s annotated Fig 38B),
wherein the residual liner is at an edge of the interface between the source or the drain and the backside contact (Residual liner 94 is at an edge of the interface between 92 and 112-See Examiner's annotated Fig 38B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Hsu91 as taught by Chiu83 for the purpose of reducing parasitic capacitance by performing backside etching/trimming processes on gate structures and epitaxial source/drain regions of semiconductor devices (Chiu83:[0009]).
Regarding Claim 3: Hsu91 and Chiu83 combination discloses all the elements of claim 2, as noted above.
Chiu83 further discloses a semiconductor device (See examiner’s annotated Fig 38B),
wherein the residual liner comprises
a first portion and a second portion (See Examiner’s annotated Fig 38B),
wherein the first portion is separated from the second portion by the backside contact (First portion of residual liner 94 and second portion of residual liner 94 are separated by backside contact 112-See Examiner's annotated Fig 38B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Hsu91 as taught by Chiu83 for the purpose of reducing parasitic capacitance by performing backside etching/trimming processes on gate structures and epitaxial source/drain regions of semiconductor devices (Chiu83:[0009]).
Regarding Claim 4: Hsu91 and Chiu83 combination discloses all the elements of claim 1, as noted above.
Chiu83 further discloses a semiconductor device (See examiner’s annotated Fig 38B),
wherein a surface of the residual liner is substantially coplanar with an interface between the source or the drain and the backside contact (surface of residual liner 94 is
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Hsu91 as taught by Chiu83 for the purpose of reducing parasitic capacitance by performing backside etching/trimming processes on gate structures and epitaxial source/drain regions of semiconductor devices (Chiu83:[0009]).
Regarding Claim 5: Hsu91 and Chiu83 combination discloses all the elements of claim 1, as noted above.
Chiu83 further discloses a semiconductor device (See examiner’s annotated Fig 38B),
wherein the residual liner has a non-uniform thickness (residual liner 94 has a non-uniform thickness as the liner has a trapezoid shape-See Examiner's annotated Fig 38B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Hsu91 as taught by Chiu83 for the purpose of reducing parasitic capacitance by performing backside etching/trimming processes on gate structures and epitaxial source/drain regions of semiconductor devices (Chiu83:[0009]).
Regarding Claim 6: Hsu91 and Chiu83 combination discloses all the elements of claim 5, as noted above.
Chiu83 further discloses a semiconductor device (See examiner’s annotated Fig 38B),
wherein the residual liner has a first thickness adjacent to an edge of the backside contact and a second thickness on an opposite end of the residual liner from the edge of the backside contact, wherein the first thickness is greater than the second thickness (first thickness is greater than the second thickness-See Examiner's annotated Fig 38B-Zoom in).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Hsu91 as taught by Chiu83 for the purpose of reducing parasitic capacitance by performing backside etching/trimming processes on gate structures and epitaxial source/drain regions of semiconductor devices (Chiu83:[0009]).
Regarding Claim 9: Hsu91 and Chiu83 combination discloses all the elements of claim 1, as noted above.
Chiu83 further discloses a semiconductor device (See examiner’s annotated Fig 38B),
wherein the non-planar transistor comprises a gate-all-around (GAA) transistor (54A/B/C structure is a gate all around nanosheet FET as the gate electrode is all around the nanosheets 54A/B/C -Fig 38A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Hsu91 as taught by Chiu83 for the purpose of reducing parasitic capacitance by performing backside etching/trimming processes on gate structures and epitaxial source/drain regions of semiconductor devices (Chiu83:[0009]).
Claim(s) 23 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (US 20210335783-Chiu83) in view of Hsu et al. (US 20210359091 A1-Hsu91).
Regarding Claim 23: Chiu83 discloses an electronic system ([0002]), comprising:
a board (PCB [0113] L18) ;
a package substrate coupled to the board (UBM 166 and external connector 168 of semiconductor device are connected to PCB so the substrate is coupled to the board- [0113] L14-20; Fig 38C); and
a die coupled to the package substrate (UBM 166 and connectors 168 couple the die to the package substrate-Fig 38C; [0113] L14-20, wherein the die (Fig 38C) comprises:
a source or a drain (92-Examiner annotated Fig 38B);
a backside contact below the source or the drain (backside contact 112 below source/Drain 92 -See Examiner's annotated Fig 38B); and
a residual liner between the source or the drain and the backside contact (residual liner 94 between source or drain 92 and backside contact 112-See Examiner's annotated Fig 38B),
wherein the residual liner is positioned at corners of an interface between the source or the drain and the backside contact (Residual liner 94 is at the corner of interface between Source/drain 92 and backside contact 112-See Examiner's annotated Fig 38B).
Chiu83 does not disclose an electronic system comprising:
a source and a drain over the semiconductor substrate;
a backside contact to the source or the drain through the semiconductor substrate
such that the backside contact is in a same horizontal plane as the semiconductor substrate.
Hsu91 teaches an electronic system comprising:
a source and a drain over the semiconductor substrate (Source/Drain 260 over substrate 204-Examiner’s annotated Fig 20B);
a backside contact to the source or the drain through the semiconductor substrate (Backside S/D contact 282 going through substrate 204-Examiner’s annotated Fig 20B)
such that the backside contact is in a same horizontal plane as the semiconductor substrate (Backside S/D contact 282 going through substrate 204 and being is the same horizontal plane as substrate 204-Examiner’s annotated Fig 20B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Chiu83 as taught by Hsu91 for the purpose of increasing the number of metal tracks available in the structure for directly connecting to source/drain contacts and vias (Hsu91:[0011]).
Regarding Claim 25: Hsu91 and Chiu83 combination discloses all the elements of claim 23, as noted above.
Chiu83 further discloses a semiconductor device (See examiner’s annotated Fig 38B),
wherein the source or the drain is part of a gate-all-around (GAA) transistor (54A/B/C structure is a gate all around nanosheet FET as the gate electrode is all around the nanosheets 54A/B/C -Fig 38A).
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Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 20210359091 A1-Hsu91) in view of Chiu et al. (US 20210335783-Chiu83), and further in view of in view of Park et al (US 20220165857-Park57).
Regarding claim 7, Hsu91 and Chiu83 combination discloses all the elements of claim 1, as noted above.
Chiu83 fails to disclose a semiconductor device
wherein the residual liner comprises silicon, oxygen, and carbon.
Park57 teaches a semiconductor device
wherein the residual liner comprises silicon, oxygen, and carbon (Residual liner 142 comprises SiOC so silicon, oxygen, and carbon-[0067] L6-7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Hsu91 in view of Chiu83 as taught by Park57 for the purpose of reducing parasitic capacitance (Park57:[003]L3-4).
Regarding claim 8, Hsu91, Chiu83 and Park 57 discloses all the elements of claim 7, as noted above.
Park57 further teaches a semiconductor device
wherein the residual liner comprises SiOC (Residual liner 142 comprises SiOC-[0067] L6-7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Hsu91 in view of Chiu83 as taught by Park57 for the purpose of reducing parasitic capacitance (Park57:[003]L3-4).
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (US 20210335783-Chiu83), in view of Hsu et al. (US 20210359091 A1-Hsu91), and further in view of Park et al (US 20220165857-Park57).
Regarding Claim 24: Hsu91 and Chiu83 combination discloses all the elements of claim 23, as noted above.
Park57 further teaches a semiconductor device
wherein the residual liner comprises silicon, oxygen, and carbon (Residual liner 142 comprises SiOC so silicon, oxygen, and carbon-[0067] L6-7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Chiu83 in view of Hsu91, as taught by Park57 for the purpose of reducing parasitic capacitance (Park57:[003]L3-4).
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Response to Arguments
Applicant’s arguments see pages 7-11 of Remarks, filed on 10/17/2025 with respect to claim(s) 1-9 and 23-25 have been considered. Applicants' arguments involve discussing why the previously cited prior art documents fail to disclose the amended limitations. Examiner finds this argument persuasive and has brought in an additional reference to address the amended claim limitations. The applicability of the reference to the amended elements is discussed in the claim rejections above.
Amended Claim(s) 1-6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 20210359091 A1-Hsu91) in view of Chiu et al. (US 20210335783-Chiu83), as described above.
Therefore, claim(s) 1-6 and 9 stand rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 20210359091 A1-Hsu91) in view of Chiu et al. (US 20210335783-Chiu83).
Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 20210359091 A1-Hsu91) in view of Chiu et al. (US 20210335783-Chiu83), and further in view of in view of Park et al (US 20220165857-Park57), as noted above.
Therefore, claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 20210359091 A1-Hsu91) in view of Chiu et al. (US 20210335783-Chiu83), and further in view of in view of Park et al (US 20220165857-Park57).
Amended Claim(s) 23 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (US 20210335783-Chiu83) in view of Hsu et al. (US 20210359091 A1-Hsu91), as described above.
Therefore, claim(s) 23 and 25 stand rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (US 20210335783-Chiu83) in view of Hsu et al. (US 20210359091 A1-Hsu91).
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (US 20210335783-Chiu83), in view of Hsu et al. (US 20210359091 A1-Hsu91), and further in view of Park et al (US 20220165857-Park57), as noted above.
Therefore, claim(s) 24 stands rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (US 20210335783-Chiu83), in view of Hsu et al. (US 20210359091 A1-Hsu91), and further in view of Park et al (US 20220165857-Park57).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Khaderbad et al. (US 20230015572 A1-Khaderbad72) teaches a semiconductor device (title) comprising: a semiconductor substrate (106/108A-Fig 1B);a non-planar transistor (Fig 1B) with a source and a drain over the semiconductor substrate (110 over 106/108A-Fig 1B) ;a backside contact to the source or the drain through the semiconductor substrate (140 on 110 through 106/108A-Fig 1B) such that the backside contact is in a same horizontal plane as the semiconductor substrate; and a residual liner between the source or the drain and the backside contact(144-Fig 1B).
Lilak et al. (US 20200294998 A1-Lilak98) teaches a semiconductor device (Title) comprising: a semiconductor substrate (112-Fig 1B); a non-planar transistor with a source and a drain over the semiconductor substrate (104 with s/d 124A over 112-Fig 1B) ; a backside contact to the source or the drain through the semiconductor substrate (138 to s/d 124A-Fig 1B).
Chen et al. (US20220285510A1-Chen10) teaches a semiconductor device (title) comprising: a semiconductor substrate (104’-Fig 9D); a non-planar transistor with a source and a drain (500A/B-Fig 13); a backside contact to the source or the drain through the semiconductor substrate (360A-Fig 13), and a residual liner between the source or the drain and the backside contact (370A-Fig 13).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHALIE R FAYETTE whose telephone number is (571)272-1220. The examiner can normally be reached Monday-Friday 8:30 am-6pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/Examiner, Art Unit 2812 03/23/2026
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812