DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/08/2025 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 7, 9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xie et al (US Publication No. 2023/0207553).
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Regarding claim 1, Xie discloses a semiconductor device, comprising: a substrate Fig 1A, 105; a transistor above the substrate ¶0043-0045, wherein the transistor comprises a source, a gate, and a drain¶0043-0045; a first metal layer above the transistor Fig 1A, T1-T8 or Fig 9, T1-T8, wherein the first metal layer comprises: a source metal Fig 1A, 160 or Fig 9, 160 coupled to the source; a drain metal Fig 1A, 161 Fig 9, 161 coupled to the drain; and a gate metal Fig 1A, 151; Fig 6C, 151, Fig 9, 151 coupled to the gate, wherein the source metal, the drain metal Fig 1A-1B ¶0048, and the gate metal are parallel conductive lines Fig 1A-1B ¶0048 and Fig 6A; a backside Fig 1A, 181 and Fig 9, 181 via passing through the substrate Fig 1A; and a contact metal Fig 9, 261 ¶0100 in the first metal layer Fig 1A, 160/161 and Fig 9, 160/161 that is above and coupled to the backside via ¶0048-0050, wherein the contact metal is oriented orthogonal to the source metal Fig 1A and Fig 9 ¶0049-0050; and wherein the contact metal Fig 9, 261 and the source metal Fig 9, 160 are in a same horizontal plane Fig 9.
Regarding claim 2, Xie discloses wherein the contact metal is adjacent to an end of the drain metal Fig 1A-1B and Fig 9.
Regarding claim 3, Xie discloses, wherein the source metal, the drain metal, and the gate metal have a pitch Fig 1A, P.
Regarding claim 7, Xie discloses wherein the transistor is a non-planar transistor ¶0039.
Regarding claim 9, Xie discloses wherein the transistor is a gate-all-around (GAA) transistor¶0039.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al (US Publication No. 2023/0207553).
Regarding claims 4-6, Xie discloses all the limitations Fig 1A-1B but silent on the specific spacing/pitch. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the pitch, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Xie et al (US Publication No. 2023/0207553) in view of Mannebach et al (US Publication No.2020/0219970).
Regarding claim 8, Xie discloses all the limitation but silent on the type of transistor. Whereas Mannebach discloses a tri-gate transistor ¶0003, 0101. Xie and Mannebach are analogous art because they are directed to semiconductor devices having back side contacts and one of ordinary skill in the art would have had a reasonable expectation of success to modify Xie because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the transistor type and incorporate the teachings of Mannebach as an alternative type of transistor known in the art.
Claims 10-15, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (US Publication No. 2022/0359491) in view of Xie et al (US Publication No. 2023/0207553).
Regarding claim 10, Chen discloses a semiconductor device Fig 2A-6B, comprising: a first transistor Fig 2A-3, wherein the first transistor is coupled to a first source metal Fig 2A-2B and Fig 5A ¶0039, 0068-0069, a first drain metal, and a first gate metal Fig 2A-2B ¶0039, wherein the first source metal, the first drain metal Fig 2A-2B ¶0039, and the first gate metal are parallel traces in a first metal layer above the first transistor Fig 2A-3 ¶0039; a second transistor Fig 2A-2B and Fig 5A-6B, adjacent to the first transistor, wherein the second transistor is coupled to a second source metal Fig 2A, 5A ¶0039, 0068-0069, a second drain metal, and a second gate metal Fig 2A and 5A ¶0039, 0068-0069, wherein the second source metal, the second drain metal, and the second gate metal are parallel to the first source metal Fig 5A ¶0039, 0068-0069; a first backside via adjacent to an edge of the first gate metal; and a second backside via in line with the first backside via and spaced away from an edge of the second gate metal ¶0034 Fig 3. Chen discloses all the limitations but silent on the arrangement of the contact metal. Whereas Xie discloses a contact metal Fig 9, 261 in the first metal layer Fig 1A or Fig 9, 160/161 that is above and coupled to the backside via ¶0048-0050, wherein the contact metal is oriented orthogonal to the source metal Fig 1A or Fig 9 ¶0049-0050 and wherein the contact metal Fig 9, 261 and the source metal Fig 9, 160 are in a same horizontal plane Fig 9. Chen and Xie are analogous art because they are directed to semiconductor devices having back side contacts and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chen because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the interconnect and incorporate the teachings of Xie to provide an improved connection.
Regarding claim 11, Chen discloses wherein the first source metal, the first drain metal, and the first gate metal have a pitch Fig 2A-2B and Fig 5A-6B.
Regarding claim 12, Chen discloses wherein the second backside via is spaced away from the edge of the second gate metal by at least one pitch Fig 2A-2B and Fig 5A-6B.
Regarding claims 13-15, Xie discloses all the limitations but silent on the specific spacing/pitch. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the pitch, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955).
Regarding claim 19, Chen discloses wherein the first backside via and the second backside via are orthogonal to the first source metal Fig 2A-2B, Fig 3 and Fig 5A-6B.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (US Publication No. 2022/0359491) and Xie et al (US Publication No. 2023/0207553) in further view of Yu et al (US Publication No.2022/0130991).
Regarding claim 16, Chen discloses all the limitations but silent on the switching speed. Whereas Yu discloses wherein the first transistor has a first switching speed, and wherein the second transistor has a second switching speed that is greater than the first switching speed ¶0015. Chen and Yu are analogous art because they are directed to semiconductor devices having back side contacts and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chen because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the transistor type and incorporate the teachings of Yu as an alternative type of transistor to improve device performance.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (US Publication No. 2022/0359491) and Xie et al (US Publication No. 2023/0207553) in further view of Lin et al (US Patent No.10,867,101).
Regarding claim 17, Chen discloses all the limitations but silent on the dummy gate. Whereas Lin discloses a dummy gate metal between the first transistor and the second transistor (Column 5, lines 5-59) Fig 1A-1C. Chen and Lin are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chen because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Chen and incorporate the teachings of Lin to prevent leakage.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (US Publication No. 2022/0359491) and Xie et al (US Publication No. 2023/0207553) in further view of Yu et al (US Publication No.2021/0336020).
Regarding claim 18, Chen discloses all the limitations but silent on the different length of the via. Whereas Yu discloses wherein a length of the first backside via is different than a length of the second backside via Fig 37B ¶0047. Chen and Yu are analogous art because they are directed to semiconductor devices having back side contacts and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chen because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the length of the via and incorporate the teachings of Yu to improve device performance.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (US Publication No. 2022/0359491) and Xie et al (US Publication No. 2023/0207553) in further view of Mannebach et al (US Publication No.2020/0219970).
Regarding claim 20, Chen discloses all the limitation but silent on the type of transistor. Whereas Mannebach discloses a tri-gate transistor ¶0003, 0101. Chen and Mannebach are analogous art because they are directed to semiconductor devices having back side contacts and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chen because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the transistor type and incorporate the teachings of Mannebach as an alternative type of transistor known in the art.
Claims 21 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al (US Publication No.2021/0336020) in view of Xie et al (US Publication No. 2023/0207553).
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Regarding claim 21, Yu discloses semiconductor device, comprising: a first transistor Fig 40B with a first drain metal that is spaced away from a first backside via by a first distance Fig 40B, the first backside via Fig 40B, 180 coupled to a first source metal Fig 40B, 186 of the first transistor by a first contact metal Fig 40B, 178, the first contact metal above the first backside via and oriented orthogonal to the first source metal Fig 40B; and a second transistor Fig 40B with second drain metal that is spaced away from a second backside via by a second distance that is different than the first distance Fig 37B and Fig 40B ¶0047, the second backside via Fig 40B, 180 coupled to a second source metal Fig 40B, 186 of the second transistor by a second contact metal Fig 40B, 178, the second contact metal above the second backside via and oriented orthogonal to the second source metal Fig 40B. Yu discloses all the limitations but silent on the arrangement of the contact metal. Whereas Xie discloses a contact metal Fig 9, 261 in the first metal layer Fig 1A or Fig 9, 160/161 that is above and coupled to the backside via ¶0048-0050, wherein the contact metal is oriented orthogonal to the source metal Fig 1A or Fig 9 ¶0049-0050 and wherein the contact metal Fig 9, 261 and the source metal Fig 9, 160 are in a same horizontal plane Fig 9. Yu and Xie are analogous art because they are directed to semiconductor devices having back side contacts and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yu because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the interconnect and incorporate the teachings of Xie to provide an improved connection.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al (US Publication No.2021/0336020) and Xie et al (US Publication No. 2023/0207553) in further view of Yu et al (US Publication No.2022/0130991).
Regarding claim 22, Yu 020 discloses all the limitations but silent on the switching speed. Whereas Yu 991 discloses wherein the first distance is greater than the second distance, and wherein the first transistor has a first switching speed that is greater than a second switching speed of the second transistor ¶0015. Yu 020 and Yu 991 are analogous art because they are directed to semiconductor devices having back side contacts and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yu 020 because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the transistor type and incorporate the teachings of Yu 991 as an alternative type of transistor to improve device performance.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al (US Publication No.2021/0336020) and Xie et al (US Publication No. 2023/0207553) in further view of Lin et al (US Patent No.10,867,101).
Regarding claim 23,Yu discloses all the limitations but silent on the dummy gate. Whereas Lin discloses wherein the first transistor is adjacent to the second transistor, wherein a dummy gate metal separates the first transistor from the second transistor (Column 5, lines 5-59) Fig 1A-1C. Yu and Lin are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yu because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Yu and incorporate the teachings of Lin to prevent leakage.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Rachmady et al (US Publication No. 2020/0219979) in view of Yu et al (US Publication No.2021/0336020) and Xie et al (US Publication No. 2023/0207553).
.Regarding claim 24, Rachmady discloses an electronic system, comprising: a board ¶0136-0138; a package substrate coupled to the board ¶0136-0138; and a die coupled to the package substrate Fig 11; wherein the die comprises a first transistor with a first drain metal that is spaced away from a first backside via by a first distance Fig 5. Rachmady discloses all the limitations except silent on having a second transistor. Whereas Yu discloses a die comprises: a first transistor Fig 40B with a first drain metal that is spaced away from a first backside via by a first distance Fig 40B, the first backside via Fig 40B, 180 coupled to a first source metal Fig 40B, 186 of the first transistor by a first contact metal Fig 40B, 178, the first contact metal above the first backside via and oriented orthogonal to the first source metal Fig 40B; and a second transistor Fig 40B with second drain metal that is spaced away from a second backside via by a second distance that is different than the first distance Fig 37B and Fig 40B ¶0047, the second backside via Fig 40B, 180 coupled to a second source metal Fig 40B, 186 of the second transistor by a second contact metal Fig 40B, 178, the second contact metal above the second backside via and oriented orthogonal to the second source metal Fig 40B. Rachmady and Yu are analogous art because they are directed to semiconductor devices having back side contacts and one of ordinary skill in the art would have had a reasonable expectation of success to modify Rachmady because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the length of the via and incorporate the teachings of Yu to improve device performance. Rachmady and Yu discloses all the limitations but silent on the arrangement of the contact metal. Whereas Xie discloses a contact metal Fig 9, 261 in the first metal layer Fig 1A or Fig 9, 160/161 that is above and coupled to the backside via ¶0048-0050, wherein the contact metal is oriented orthogonal to the source metal Fig 1A or Fig 9 ¶0049-0050 and wherein the contact metal Fig 9, 261 and the source metal Fig 9, 160 are in a same horizontal plane Fig 9. Rachmandy, Yu and Xie are analogous art because they are directed to semiconductor devices having back side contacts and one of ordinary skill in the art would have had a reasonable expectation of success to modify Rachmady and Yu because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the interconnect and incorporate the teachings of Xie to provide an improved connection.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Rachmady et al (US Publication No. 2020/0219979) in view of Yu et al (US Publication No.2021/0336020) and Xie et al (US Publication No. 2023/0207553) and in further view of Yu et al (US Publication No.2022/0130991).
Regarding claim 25, Rachmady discloses all the limitations but silent on the switching speed. Whereas Yu 991 discloses wherein the first distance is greater than the second distance, and wherein the first transistor has a first switching speed that is greater than a second switching speed of the second transistor ¶0015. Rachmady and Yu 991 are analogous art because they are directed to semiconductor devices having back side contacts and one of ordinary skill in the art would have had a reasonable expectation of success to modify Rachmady because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the transistor type and incorporate the teachings of Yu as an alternative type of transistor to improve device performance.
Response to Arguments
Applicant’s arguments with respect to claims 1-25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/CHRISTINE A ENAD/ Primary Examiner, Art Unit 2811