DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/23/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5 and 11-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 11 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2021/0375857 A1, hereinafter Huang ‘857), in view of Vellianitis et al. (US 2021/0376096 A1, hereinafter Vellianitis ‘096), in further view of Dentoni Litta et al. (US 2021/0193821 A1, hereinafter Dentoni Litta ‘821) in view of the following arguments.
PNG
media_image1.png
697
540
media_image1.png
Greyscale
With respect to Claim 1 Huang ‘857 discloses an integrated circuit structure (Fig 1-20E), comprising:
a plurality of horizontally stacked nanowires (124, Fig 9A, Para [0043])(Para [0013] discloses channel 124 as nanowires);
a gate structure (180, Fig 9A, Para [0027]) over the plurality of horizontally stacked nanowires (124);
an epitaxial source or drain structure (240, Fig 10, Para [0035]) at an end of the plurality of horizontally stacked nanowires (124)(Fig 9A & 10 and Para [0036] discloses epitaxial source/drain regions are formed at end of nanowires 124), and
a conductive trench contact structure (280, Fig 12, Para [0047]) vertically over (disclosed in Fig 12) the epitaxial source or drain structure (240), the conductive trench contact structure (280) electrically connected (disclosed in Para [0047]) to a top (disclosed in Fig 12) of the epitaxial source or drain structure (240) of the epitaxial source or drain structure (240); and
a dielectric plug (255, Fig 12, Para [0046]) adjacent to a side of the conductive trench contact structure (280)(255 adjacent to a side of conductive trench contact structure 280 is disclosed in Fig 13),
But Huang ‘857 fails to explicitly disclose the epitaxial source or drain structure having a maximum lateral width between laterally opposing sides of the epitaxial source or drain structure; and a conductive trench contact structure connected to at least 10% of a length of the laterally opposing sides of the epitaxial source or drain structure, the conductive trench contact having a lateral width greater than the maximum lateral width of the epitaxial source or drain structure.
Nevertheless, in a related endeavor (Fig 1-17B-3 of Vellianitis ‘096), Vellianitis ‘096 teaches the epitaxial source or drain structure (255, Fig 17B-3 of Vellianitis ‘096, Para [0034]) having a maximum lateral width (maximum lateral width as shown in annotated Fig 17B-3 of Vellianitis ‘096) between laterally opposing sides (opposite sides of 255 as shown in annotated Fig 17B-3 of Vellianitis ‘096, hereinafter LOS) of the epitaxial source or drain structure (255); and a conductive trench contact structure (290, Fig 17B-3, Para [0034]) connected to at least 10% of a length of the laterally opposing sides (length of LOS)(Fig 17B-3 of Vellianitis ‘096 discloses the contact 290 covers all sides of LOS) of the epitaxial source or drain structure (255), the conductive trench contact (290) having a lateral width (lateral width of 290 as shown in annotated Fig 17B-3 of Vellianitis ‘096) greater than the maximum lateral width (maximum lateral width as shown in annotated Fig 17B-3 of Vellianitis ‘096) of the epitaxial source or drain structure (255)(Annotated Fig 17B-3 of Vellianitis ‘096 discloses trench contact 290 having a greater lateral width than source/drain structure 255).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Vellianitis ‘096’s teaching of the epitaxial source or drain structure having a maximum lateral width between laterally opposing sides of the epitaxial source or drain structure; and a conductive trench contact structure connected to at least 10% of a length of the laterally opposing sides of the epitaxial source or drain structure, the conductive trench contact having a lateral width greater than the maximum lateral width of the epitaxial source or drain structure into Huang ‘857’s integrated circuit structure. Huang ‘857 teaches a gate all around FinFET structure with contacts to the epitaxial source/drain regions. Vellianitis ‘096 also teaches a gate all around FinFET structure with contacts that wrap around the epitaxial source/drain regions. The ordinary artisan would have been motivated to modify Huang ‘857 in the manner set forth above, at least, because the teaching of Vellianitis ‘096’s contacts wrapping around the epitaxial source/drain regions, as taught in Para [0010 of Vellianitis ‘096] states that forming wrap around source/drain contacts in the manner described above can lower the contact resistance between the contact and the source/drain structures and creating that structure integrates seamlessly with current manufacturing process, thereby allowing the ordinary artisan to improve the performance and simplify the manufacturing process of the device.
As incorporated, the source/drain connection structure (290) of Vellianitis ‘096 would be used as the conductive trench contact structure (280) of Huang ‘857.
Huang ‘857 as modified by Vellianitis ‘096 fails to explicitly disclose the dielectric plug having an uppermost surface above an uppermost surface of the conductive trench contact structure.
Nevertheless, in a related endeavor, (Fig 1-8a of Dentoni Litta ‘821), Dentoni Litta ‘821 teaches the dielectric plug (108/109, Fig 7b of Dentoni Litta ‘821, Para [0084 and 0086]) having an uppermost surface (top of 108 and 109 as shown in Fig 7b of Dentoni Litta ‘821) above an uppermost surface of the conductive trench contact structure (112b/112d/112e, Fig 7b of Dentoni Litta ‘821, Para [0084]) (Fig 7b and Para [0083] of Dentoni Litta ‘821 disclose contact structure is etched below top surface of 108 and 109).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Dentoni Litta ‘821’s teaching of the dielectric plug having an uppermost surface above an uppermost surface of the conductive trench contact structure into Huang ‘857 as modified by Vellianitis ‘096’s device. Huang ‘857 as modified by Vellianitis ‘096 teaches an integrated circuit structure comprising nanowires, a conductive trench contact structure over an epitaxial source/drain region and a dielectric plug separating the conductive trench contact structure. Dentoni Litta ‘821 also teaches an integrated circuit structure comprising nanowires, a conductive trench contact structure over an epitaxial source/drain region and a dielectric plug separating the conductive trench contact structure and further teaches the dielectric plug regions above the uppermost surface of the conductive trench contact structure as described above. The ordinary artisan would have been motivated to modify Huang ‘857 as modified by Vellianitis ‘096 in the manner set forth above, at least, because this extension of the dielectric plug above the uppermost surface of the conductive trench contact structure can provide additional dielectric protection from parasitic capacitance between neighboring conductive trench contact structures.
As incorporated, the teaching of Dentoni Litta ‘821 of the dielectric plugs (108 and 109) extending over the uppermost surface of the conductive trench contact structure (112b/112d/112e) would be used so the dielectric plug (255 of Huang ‘857) extends over the uppermost surface of the conductive contact structure (280 of Huang ‘857) in the structure of Huang ‘857 as modified by Vellianitis ‘096.
With respect to Claim 2 Huang ‘857 as modified by Vellianitis ‘096 and further modified by Dentoni Litta ‘821 discloses all limitations of the integrated circuit structure of claim 1, and Huang ‘857 as modified by Vellianitis ‘096 discloses further comprising:
a metal silicide layer (270, Fig 12, Para [0047]) between and in contact with (Para [0047] discloses 270 formed between 280 and 240) the conductive trench contact structure (280 of Huang ‘857 as modified by 290 of Vellianitis ‘096 as incorporated in Huang ‘857 above) and the epitaxial source or drain structure (240).
With respect to Claim 3 Huang ‘857 as modified by Vellianitis ‘096 and further modified by Dentoni Litta ‘821 discloses all limitations of the integrated circuit structure of claim 1, and Huang ‘857 as modified by Vellianitis ‘096 and further modified by Dentoni Litta ‘821 discloses further comprising:
a second conductive trench contact (280 (280 of Huang ‘857 as modified by 290 of Vellianitis ‘096 as incorporated in Huang ‘857 above) in center of structure shown in Fig 12, Para [0047] also discloses a plurality of contacts) structure laterally spaced apart (disclosed in Fig 12) from the conductive trench contact structure (280 on left side of structure shown in Fig 12) by the dielectric plug (255 as modified by Dentoni Litta ‘821 as incorporated above).
With respect to Claim 4 Huang ‘857 as modified by Vellianitis ‘096 and further modified by Dentoni Litta ‘821 discloses all limitations of the integrated circuit structure of claim 3, and Huang ‘857 as modified by Vellianitis ‘096 and further modified by Dentoni Litta ‘821 discloses further comprising:
an etch stop layer portion (portion of 250 under dielectric plug 255, shown in annotated Fig 12 of Huang ‘857, Para [0038]) vertically beneath (annotated Fig 12 of Huang ‘857 discloses etch stop portion 250 below dielectric plug 255) the dielectric plug (255 as modified by Dentoni Litta ‘821 as incorporated above).
PNG
media_image2.png
657
701
media_image2.png
Greyscale
With respect to Claim 5 Huang ‘857 as modified by Vellianitis ‘096 and further modified by Dentoni Litta ‘821 discloses all limitations of the integrated circuit structure of claim 4, and Huang ‘857 as modified by Vellianitis ‘096 and further modified by Dentoni Litta ‘821 discloses further wherein the etch stop layer portion (portion of 250 under dielectric plug 255, shown in annotated Fig 12 of Huang ‘857), is not in contact with the epitaxial source or drain structure (240)(annotated Fig 12 of Huang ‘857 discloses etch stop portion 250 below dielectric plug 255 odes not contact source or drain structure 240).
PNG
media_image1.png
697
540
media_image1.png
Greyscale
With respect to Claim 11 Huang ‘857 discloses a computing device (Fig 1-20E), comprising:
a board (110, Fig 12, Para [0015]); and
a component (Para [0013 and 0014] discloses device in Fig 1-20E of Huang ‘857 as a semiconductor device) coupled to the board (110), the component (device disclosed in Fig 1-20E of Huang ‘857) including an integrated circuit structure (Para [0014] discloses device disclosed in Fig 1-20E of Huang ‘857 as an integrated circuit structure), comprising:
a plurality of horizontally stacked nanowires (124, Fig 9A, Para [0043])(Para [0013] discloses channel 124 as nanowires);
a gate structure (180, Fig 9A, Para [0027]) over the plurality of horizontally stacked nanowires (124);
an epitaxial source or drain structure (240, Fig 10, Para [0035]) at an end of the plurality of horizontally stacked nanowires (124)(Fig 9A & 10 and Para [0036] discloses epitaxial source/drain regions are formed at end of nanowires 124); and
a conductive trench contact structure (280, Fig 12, Para [0047]) vertically over (disclosed in Fig 12) the epitaxial source or drain structure (240), the conductive trench contact structure (280) electrically connected (disclosed in Para [0047]) to a top (disclosed in Fig 12) of the epitaxial source or drain structure (240) of the epitaxial source or drain structure (240); and
a dielectric plug (255, Fig 12, Para [0046]) adjacent to a side of the conductive trench contact structure (280)(255 adjacent to a side of conductive trench contact structure 280 is disclosed in Fig 13),
Huang ‘857 fails to expressly disclose the epitaxial source or drain structure having a maximum lateral width between laterally opposing sides of the epitaxial source or drain structure; and a conductive trench contact structure connected to at least 10% of a length of the laterally opposing sides of the epitaxial source or drain structure, the conductive trench contact having a lateral width greater than the maximum lateral width of the epitaxial source or drain structure.
Nevertheless, in a related endeavor (Fig 1-17B-3 of Vellianitis ‘096), Vellianitis ‘096 teaches the epitaxial source or drain structure (255, Fig 17B-3 of Vellianitis ‘096, Para [0034]) having a maximum lateral width (maximum lateral width as shown in annotated Fig 17B-3 of Vellianitis ‘096) between laterally opposing sides (opposite sides of 255 as shown in annotated Fig 17B-3 of Vellianitis ‘096, hereinafter LOS) of the epitaxial source or drain structure (255); and a conductive trench contact structure (290, Fig 17B-3, Para [0034]) connected to at least 10% of a length of the laterally opposing sides (length of LOS)(annotated Fig 17B-3 of Vellianitis ‘096 discloses the contact 290 covers all sides of LOS) of the epitaxial source or drain structure (255), the conductive trench contact (290) having a lateral width (lateral width of 290 as shown in annotated Fig 17B-3 of Vellianitis ‘096) greater than the maximum lateral width (maximum lateral width as shown in annotated Fig 17B-3 of Vellianitis ‘096) of the epitaxial source or drain structure (255)(Annotated Fig 17B-3 of Vellianitis ‘096 discloses trench contact 290 having a greater lateral width than source/drain structure 255).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Vellianitis ‘096’s teaching of the epitaxial source or drain structure having a maximum lateral width between laterally opposing sides of the epitaxial source or drain structure; and a conductive trench contact structure connected to at least 10% of a length of the laterally opposing sides of the epitaxial source or drain structure, the conductive trench contact having a lateral width greater than the maximum lateral width of the epitaxial source or drain structure into Huang ‘857’s integrated circuit structure. Huang ‘857 teaches a gate all around FinFET structure with contacts to the epitaxial source/drain regions. Vellianitis ‘096 also teaches a gate all around FinFET structure with contacts that wrap around the epitaxial source/drain regions. The ordinary artisan would have been motivated to modify Huang ‘857 in the manner set forth above, at least, because the teaching of Vellianitis ‘096’s contacts wrapping around the epitaxial source/drain regions, as taught in Para [0010 of Vellianitis ‘096] states that forming wrap around source/drain contacts in the manner described above can lower the contact resistance between the contact and the source/drain structures and creating that structure integrates seamlessly with current manufacturing process, thereby allowing the ordinary artisan to improve the performance and simplify the manufacturing process of the device.
As incorporated, the source/drain connection structure (290) of Vellianitis ‘096 would be used as the conductive trench contact structure (280) of Huang ‘857.
Huang ‘857 as modified by Vellianitis ‘096 fails to explicitly disclose the dielectric plug having an uppermost surface above an uppermost surface of the conductive trench contact structure.
Nevertheless, in a related endeavor, (Fig 1-8a of Dentoni Litta ‘821), Dentoni Litta ‘821 teaches the dielectric plug (108/109, Fig 7b of Dentoni Litta ‘821, Para [0084 and 0086]) having an uppermost surface (top of 108 and 109 as shown in Fig 7b of Dentoni Litta ‘821) above an uppermost surface of the conductive trench contact structure (112b/112d/112e, Fig 7b of Dentoni Litta ‘821, Para [0084]) (Fig 7b and Para [0083] of Dentoni Litta ‘821 disclose contact structure is etched below top surface of 108 and 109).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Dentoni Litta ‘821’s teaching of the dielectric plug having an uppermost surface above an uppermost surface of the conductive trench contact structure into Huang ‘857 as modified by Vellianitis ‘096’s device. Huang ‘857 as modified by Vellianitis ‘096 teaches an integrated circuit structure comprising nanowires, a conductive trench contact structure over an epitaxial source/drain region and a dielectric plug separating the conductive trench contact structure. Dentoni Litta ‘821 also teaches an integrated circuit structure comprising nanowires, a conductive trench contact structure over an epitaxial source/drain region and a dielectric plug separating the conductive trench contact structure and further teaches the dielectric plug regions above the uppermost surface of the conductive trench contact structure as described above. The ordinary artisan would have been motivated to modify Huang ‘857 as modified by Vellianitis ‘096 in the manner set forth above, at least, because this extension of the dielectric plug above the uppermost surface of the conductive trench contact structure can provide additional dielectric protection from parasitic capacitance between neighboring conductive trench contact structures.
As incorporated, the teaching of Dentoni Litta ‘821 of the dielectric plugs (108 and 109) extending over the uppermost surface of the conductive trench contact structure (112b/112d/112e) would be used so the dielectric plug (255 of Huang ‘857) extends over the uppermost surface of the conductive contact structure (280 of Huang ‘857) in the structure of Huang ‘857 as modified by Vellianitis ‘096.
With respect to Claim 14 Huang ‘857 as modified by Vellianitis ‘096 and further modified by Dentoni Litta ‘821 discloses all limitations of the computing device of claim 11, and Huang ‘857 further discloses wherein the component (device disclosed in Fig 1-20E of Huang ‘857) is a packaged integrated circuit die (Para [0014] disclose component as part of an integrated circuit).
With respect to Claim 15 Huang ‘857 as modified by Vellianitis ‘096 and further modified by Dentoni Litta ‘821 discloses all limitations of the computing device of claim 11, and Huang ‘857 further discloses wherein the component (device disclosed in Fig 1-20E of Huang ‘857) is selected from the group consisting of a processor, a communications chip, and a digital signal processor (Para [0014] discloses component of Fig 1-20E “may be intermediate devices fabricated during processing of an integrated circuit (IC), or a portion thereof, that may include static random access memory (SRAM), logic circuits, passive components, such as resistors, capacitors, and inductors, and/or active components, such as p-type field effect transistors (PFETs), n-type FETs (NFETs), multi-gate FETs, metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and combinations thereof”).
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Huang ‘857 in view of Vellianitis ‘096, in view of Dentoni Litta ‘821 in further view of Glass et al. (US 2020/0258982 A1, hereinafter Glass ‘982), in view of the following arguments.
With respect to Claim 12 Huang ‘857 as modified by Vellianitis ‘096 and further modified by Dentoni Litta ‘821 discloses all limitations of the computing device of claim 11, but Huang ‘857 as modified by Vellianitis ‘096 and further modified by Dentoni Litta ‘821 fails to explicitly disclose further comprising:
a memory coupled to the board.
Nevertheless, in a related endeavor (Fig 1-4 of Glass ‘982), Glass ‘982 teaches a memory (DRAM, Fig 4 of Glass ‘982, Para [0067]) coupled to the board (1002, Fig 4 of Glass ‘982, Para [0066]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Glass ‘982’s teaching of a memory coupled to the board into Huang ‘857 as modified by Vellianitis ‘096 and further modified by Dentoni Litta ‘821’s device. The ordinary artisan would have been motivated to modify Huang ‘857 as modified by Vellianitis ‘096 and further modified by Dentoni Litta ‘821 in the manner set forth above, at least, because the further addition of a memory component on the board would increase the functionality of the end device.
As incorporated, the memory (DRAM) coupled to the board (1002) of Glass ‘982 would be incorporated in the device of Huang ‘857 as modified by Vellianitis ‘096 and further modified by Dentoni Litta ‘821 so that Huang ‘857 as modified by Vellianitis ‘096 and further modified by Dentoni Litta ‘821’s device and the memory would be on the same board.
With respect to Claim 13 Huang ‘857 as modified by Vellianitis ‘096 and further modified by Dentoni Litta ‘821 discloses all limitations of the computing device of claim 11, but Huang ‘857 as modified by Vellianitis ‘096 and further modified by Dentoni Litta ‘821 fails to explicitly disclose further comprising:
a communication chip coupled to the board.
Nevertheless, in a related endeavor (Fig 1-4 of Glass ‘982), Glass ‘982 teaches a communication chip (1006, Fig 4 of Glass ‘982, Para [0066]) coupled to the board (1002, Fig 4 of Glass ‘982, Para [0066]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Glass ‘982’s teaching of a communication chip coupled to the board into Huang ‘857 as modified by Vellianitis ‘096 and further modified by Dentoni Litta ‘821’s device. The ordinary artisan would have been motivated to modify Huang ‘857 as modified by Vellianitis ‘096 and further modified by Dentoni Litta ‘821 in the manner set forth above, at least, because the further addition of a communication chip component on the board would increase the functionality of the end device.
As incorporated, the communication chip (1006) coupled to the board (1002) of Glass ‘982 would be incorporated in the device of Huang ‘857 as modified by Vellianitis ‘096 and further modified by Dentoni Litta ‘821 so that Huang ‘857 as modified by Vellianitis ‘096 and further modified by Dentoni Litta ‘821’s device and the communication chip would be on the same board.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights