DETAILED ACTION
Response to Arguments
Applicant's arguments filed 4/29/25 have been fully considered but they are not persuasive.
Applicant argues that Scanlan teaches the opposite of what is claimed in claim 1, stating that Scanlan teaches the back side surface of the die facing the carrier. However, the claims don’t establish orientation and use broad language such as “on” and “over” to describe placement, which doesn’t imply direct contact, orientation, or any other type of order. “On” and “over” are so broad that the layers involve need only be “on” (intervening layers are not exclusive of this language) and/or “over” which just means over, so above, anywhere. As such, the arguments that Scanlan fails to teach specific locations in physical contact with others is not persuasive as those orientations are not specifically claimed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-10, 21, 22, 24-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Scanlan (US 20150115456 A1) in view of Chen (US 20210066222 A1) and further in view of Lakhera (US 20190181079 A1).
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Provided directly below is an annotated Fig. 7 from Scanlan.
Regarding claims 1, 21 and 22, Scanlan teaches a method of making a semiconductor package, comprising:
forming bond pads 304 over a device side surface of a semiconductor die 305,
placing Fig. 5 the device side surface of the semiconductor dies on a carrier 501 ;
forming a dielectric layer 601 over a back side surface of the semiconductor dies opposite the device side surface to form a reconstituted wafer (Paragraph [0034]) including the semiconductor dies 305 spaced from one another Fig. 5;
removing the carrier 501 from the semiconductor dies 305;
forming a redistribution layer 302 303 and bottom part of 702 (Herein referred to as R1, and can be seen in annotated Fig. 7) over the bond pads 304 on the device side surface of the semiconductor dies 305;
forming interconnects I1 (See annotated Fig. 7) on the redistribution layer , the interconnects coupled to the bond pads by conductors in the redistribution layer (Note: element 303 of R1 is expressly noted as conductive), the interconnects spaced from one another by a second pitch P2 distance that is greater than the first pitch P1 distance (See annotated Fig. 7);
singulating a reconstituted semiconductor device from the reconstituted wafer Fig. 8, the reconstituted semiconductor device comprising one of the semiconductor dies 305 and solder bumps 701 over the one of the semiconductor dies 305;
Although Scanlan shows much of the claimed device, Scanlan fails to expressly disclose the bond pads 304 spaced from one another at a first pitch distance that is less than 100 microns.
Chen teaches the bond pads 304 spaced from one another at a first pitch distance that is less than 100 microns (Paragraph [0015], Note: Chen discloses the use of bond pads on a semiconductor die, with distanced between within 2 to 20 microns.), for reducing the routing distance between features allowing higher operation speeds (Paragraph [0015]).
Therefore, it would have been obvious to a person of ordinary skill before the effective filing date of the claimed invention to have performed the method of making a semiconductor package taught by Scanlan with the first pitch distance less than 100 microns, for the purposes of reducing the routing distance between features allowing higher operation speeds.
Although the combination of Scanlan and Chen show much of the claimed device, Scanlan and Chen fail to expressly disclose mounting the reconstituted semiconductor device onto a device side surface of a package substrate; and covering the reconstituted semiconductor device and the device side surface of the package substrate with a protective cover.
Lakhera teaches mounting the reconstituted semiconductor device onto a device side surface of a package substrate 102; and covering the reconstituted semiconductor device and the device side surface of the package substrate with a protective cover 126 (Paragraph [0001] & [0002], Note: Lakhera teaches semiconductor packages may be attached to BGAs and have support structures).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of making a semiconductor package taught by the combination of Scanlan and Chen with the mounting of the reconstituted semiconductor device onto a device side surface of a package substrate; and covering the reconstituted semiconductor device and the device side surface of the package substrate with a protective cover as taught by Lakhera. The two devices merely performing their same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. V. Teleflex Inc., 550 U.S. 398,417 (2007)).
Regarding claims 2 and 24, the combination of Scanlan, Chen, and Lakhera teach the method of claim 1 and 21, with Lakhera further teaching: wherein mounting the reconstituted semiconductor device onto a device side surface of a package substrate further comprises flip chip mounting the reconstituted semiconductor device onto a ball grid array package substrate (Lakhera, Paragraphs [0002] and [0014], Note: Lakhera teaches that the semiconductor packages which may be attached to BGAs are possibly flip chip dies).
Regarding claims 3 and 25, the combination of Scanlan, Chen, and Lakhera teach the method of claim 1 and 21, with Lakhera further teaching: wherein the package substrate is a ball grid array substrate, a premolded lead frame, a metal lead frame, a ceramic package substrate, or a multilayer package substrate (Lakhera, Paragraph [0002], Note: BGA).
Regarding claim 5, the combination of Scanlan, Chen, and Lakhera teach the method of claim 1, with Chen further teaching: wherein the first pitch distance P1 is less than 60 microns (Paragraph [0015]).
Regarding claim 6, the combination of Scanlan, Chen, and Lakhera teach the method of claim 5.
Additionally, it would have been obvious to a person of ordinary skill in the art before the effective filing date to have the second pitch distance be greater than 150 microns, since it has been held by the federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 7, the combination of Scanlan, Chen, and Lakhera teach the method of claim 1, with Chen further teaching: wherein the first pitch distance P1 is greater than 10 microns and less than 60 microns (Paragraph [0015]).
Regarding claim 8, the combination of Scanlan, Chen, and Lakhera teach the method of claim 5.
Additionally, it would have been obvious to a person of ordinary skill in the art before the effective filing date to have the second pitch distance be greater than 100 microns, since it has been held by the federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 9 and 26, the combination of Scanlan, Chen, and Lakhera teach the method of claim 1 and 21, with Scanlan further teaching: wherein forming the reconstituted wafer further comprises covering the back side surface of the semiconductor dies with one of a thermoplastic, acrylonitrile butadiene styrene (ABS) , acrylonitrile styrene acrylate (ASA), resin, epoxy 910, plastic, or epoxy resin mold compound (Paragraph [0034], Note: 910 may be laminate epoxy).
Regarding claim 10, the combination of Scanlan, Chen, and Lakhera teach the method of claim 1, with Scanlan further teaching: wherein forming the interconnects I1 further comprises forming conductive post connects extending from proximate ends on the redistribution layer R1 and having solder at distal ends facing away from the redistribution layer (See annotated Fig. 7).
Claim(s) 4 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Scanlan (US 20150115456 A1) in view of Chen (US 20210066222 A1) and further in view of Lakhera (US 20190181079 A1) and even further in view of Darveaux (US 8941250 B1).
Regarding claims 4 and 23, the combination of Scanlan, Chen, and Lakhera teach the method of claim 1 and 21.
although the combination of Scanlan, Chen, and Lakhera shows much of the claimed invention, the combination of Scanlan, Chen, and Lakhera fails to expressly disclose : wherein forming the redistribution layer further comprises: forming a layer of passivation material over the bond pads of the semiconductor dies; patterning the layer of passivation material to expose the bond pads; plating a conductor layer on the bond pads; forming conductive lands over the layer of passivation material configured to receive solder bumps; and forming solder bumps on the conductive lands, the solder bumps spaced from one another by at least the second pitch distance.
Darveaux teaches, wherein forming the redistribution layer further comprises (Note: the following numerical references are all from Darveaux, for clarity):
forming a layer of passivation material 214 over the bond pads 210 of the semiconductor dies 202;
patterning the layer of passivation material 214 to expose the bond pads 210 (Paragraph [0021], Note: pattern 214 is patterned to form apertures 216, which would expose bond pads 210);
plating a conductor layer 220 on the bond pads; forming conductive lands 842 over the layer of passivation material configured to receive solder bumps 952 (Fig. 3);
and forming solder bumps 952 on the conductive lands 842, the solder bumps spaced from one another by at least the second pitch distance (This would be the case, making into the form that Scanlan taught above in claim 1).
For the purposes of isolating the circuit patterns (Note: Scanlan’s bond pads, redistribution structures, and interconnect structures) from one another (Paragraph [0004]).
Therefore, it would have been obvious to a person of ordinary skill before the effective filing date of the claimed invention to have modified the method of claim 1 taught by the combination of Scanlan, Chen, and Lakhera with the method wherein forming the redistribution layer further comprises: forming a layer of passivation material over the bond pads of the semiconductor dies; patterning the layer of passivation material to expose the bond pads; plating a conductor layer on the bond pads; forming conductive lands over the layer of passivation material configured to receive solder bumps; and forming solder bumps on the conductive lands, the solder bumps spaced from one another by at least the second pitch distance as taught by Darveaux for the purposes of isolating the circuit patterns (Note: Scanlan’s bond pads, redistribution structures, and interconnect structures) from one another (Paragraph [0004]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J TOBERGTE whose telephone number is (571)272-6458. The examiner can normally be reached M-F 7:30-4:30.
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/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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