DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 5, 2026, has been entered.
Election/Restrictions
Claims 1-5 and 7-21 are pending in this application.
Applicant elected without traverse of Group I, claims 1-17 in the reply filed on June 23, 2025. Claim 6 is now cancelled.
Claims 18-21 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on June 23, 2025.
The Examiner notes that claims 1-5 and 7-17 are examined and claims 18-21 are withdrawn.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed April 2, 2026, and entered with the request for continued examination filed May 5, 2026. Claims 1 and 11 are amended. Claims 18-21 remain withdrawn. The Examiner notes that claims 1-5 and 7-17 are examined.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 5, and 11-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claim 2, the term “stress and defect free” is indefinite because it is unclear what “stress” is referring to and whether it refers to strain on the epitaxial layer to the side of the spacer from the channel regions or if it refers to an internal stress field caused by crystallographic defects. For the purpose of this action, the claim will be interpreted to mean that the material is free of localized stress fields caused by crystal defects in the epitaxial growth. Although the claim language appears in para. 80 of the specification, the intended meaning of “stress” is unclear even when considering the language of para. 80 because the specification also teaches in para. 36 that no defects occurring during growth results in larger stress and that this stress is desirable.
Claim 5 recites the limitation "the layer" in line 3. There is insufficient antecedent basis for this limitation in the claim.
With respect to claim 11, the limitation “and wherein a volume of the first epitaxial material adjacent to the spacer at ends of each of the first plurality of layers of gate electrode material” is indefinite because the clause appears incomplete and it is not clear what relationships the elements have to each other.
Claim 11 recites the limitation "the layer" in line 16. There is insufficient antecedent basis for this limitation in the claim and it is unclear which layer of the plurality of layers “the layer” refers to.
Dependent claims 12-17 are rejected at least on the same basis as the claims from which they depend.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-12, and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Hashemi (US 2017/0200832 A1) in view of More (US 2023/0058459 A1).
With respect to claim 1, Hashemi teaches in Fig. 8C:
A transistor structure (title, “nanowire transistor structures”) comprising:
an epitaxial material (source/drain regions 60 and nanowires 46 formed from silicon layers 38 (para. 26) which are epitaxial per para. 23 “layers 36 are grown epitaxially in alternating sequence with the silicon layers 38 using a blanket layer deposition process.”) above a substrate (base layer 32);
a plurality of layers of gate electrode material (gate conductor layers 52 located between the nanowires 46) that extend through the epitaxial material (46),
wherein each of the plurality of layers are in a separate plane (Fig. 8C shows multiple planes of gate conductive material),
wherein the plurality of layers are substantially parallel to each other (See Fig. 8C),
wherein the epitaxial material (46) separates each of the plurality of layers (46 separates each of the layers of 52) from the other (see Fig. 9);
a spacer (gate spacer 56) at ends of each of the plurality of layers of gate electrode material (52),
the spacer in direct physical contact with the plurality of layers of gate electrode material (see Fig. 8C)
Hashemi fails to teach:
and wherein the epitaxial material is vertically intervening between the substrate and a bottommost surface of the gate electrode material;
More teaches in Fig. 20:
and wherein the epitaxial material (buffer layer 203 in addition to channel members 2080 and source drain features 244 which are analogous to the epitaxial features of Hashemi) is vertically intervening between the substrate (substrate 201) and a bottommost surface of the gate electrode material (gate electrode 260);
Hashemi discloses the claimed invention except for the epitaxial material including a layer between the substrate and the gate electrode. More teaches that it is known to epitaxially grow a buffer layer between the substrate and gate electrode as set forth in para. [0022] and Fig. 20. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Hashemi to include a buffer layer between the substrate and gate in the epitaxial layers, as taught by More in order to transition between the substrate and the channel layers in a way that prevents defects in the substrate from causing defects in the epitaxial layers. See MPEP 2144.
With respect to claim 2, More teaches:
wherein a volume of the epitaxial material adjacent to the spacer for at least some of the plurality of layers of gate material is stress and defect free. ([0019] “When the buffer layer 203 of a sufficient thickness is epitaxially deposited on the substrate 201 as shown in FIG. 2, lattice defects may only be present at or near an interface 203I with the substrate 201 but do not propagate through the thickness of the buffer layer 203. This is because the lattice strain may be gradually released with the distance from the interface 203I. In an ideal case, a top surface of the buffer layer 203 may include germanium lattice structures that are substantially defect-free. The top surface of the buffer layer 203 therefore serves as a low-lattice-strain foundation for the formation of the stack 204. In some embodiments, the buffer layer 203 includes germanium (Ge) that is undoped or not intentionally doped. To sufficiently release the lattice strain at the interface 203I, the buffer layer 203 may have a first thickness T1 between about 50 nm and about 200 nm. This thickness is not trivial. When the thickness of the buffer layer 203 is smaller than 50 nm, the lattice defect density on the top surface of the buffer layer 203 may still be too high, preventing formation of high-quality stack 204”)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Hashemi in view of More as explained above.
With respect to claim 3, Hashemi further teaches:
wherein the epitaxial material (48) includes a selected one of: silicon (Si) or silicon germanium (SiGe) (nanowires 46 formed from silicon layers 38 (para. 26) which are epitaxial per para. 23 “layers 36 are grown epitaxially in alternating sequence with the silicon layers 38 using a blanket layer deposition process.”)
With respect to claim 4, Hashemi further teaches:
wherein a material of the spacer (56) includes a selected one or more of: silicon, nitrogen, oxygen, silicon nitride, silicon oxide, silicon oxynitride, silicon nitride oxide, or carbon films. (para 31 “The spacers can be formed by depositing a dielectric film such as silicon nitride and etching the dielectric film from all horizontal surfaces by RIE”)
With respect to claim 5, Hashemi further teaches:
further comprising a high-k dielectric material (high-k dielectric layers 50) on a top surface of the layer and the high-k dielectric material on a bottom surface of each of the plurality of layers of gate electrode material (52). (See Fig. 9, layers between the nanowires have high-k dielectric on both top and bottom)
With respect to claim 7, Hashemi further teaches:
wherein the gate material includes a selected one or more of: tungsten, titanium, titanium nitride, silver, indium, or cadmium (para. 27, “The gate conductors may be comprised of metals such as TiN, TaN, W, WN, TaAlN, Al, Au, Ag, or a combination of such metals”)
With respect to claim 8, Hashemi further teaches:
wherein the transistor structure is on a substrate (substrate 32, 34), the substrate includes a selected one of: Si or buried oxide (BOX). (para. 22 “The base layer 32 can be bulk silicon”)
With respect to claim 9, Hashemi further teaches:
wherein the plurality of layers (52) overlap each other in a direction perpendicular to the plurality of planes (see Fig. 9, overlap in a vertical direction).
With respect to claim 10, Hashemi further teaches:
wherein the transistor structure includes a plurality of transistor structures. (See Fig. 9, there are two separate stacks of nanosheet transistors)
With respect to claim 11, Hashemi teaches in Fig. 8C:
a first epitaxial material (source/drain 60 and nanowires 46 associated with transistor on the left) and a second epitaxial material (source drain 60 and nanowires 46 associated with transistor on the right);
a first plurality of layers of gate electrode material (gate conductor layers 52 located between the nanowires 46 on left) that extend through the first epitaxial material (46 on left side),
wherein each of the first plurality of layers are substantially parallel to each other (see Fig. 8C),
wherein the first epitaxial material (46 on left) separates each of the first plurality of layers from another (52 on left);
a first spacer (gate spacer 56 on left side) at ends of each of the first plurality of layers of gate electrode material (52 on left), the first spacer in direct physical contact with the first plurality of layers of gate electrode material (see Fig. 8C);
and a second plurality of layers of gate material electrode (gate conductor layers 52 located between the nanowires 46 on right) that extend through the second epitaxial material (46 on right),
wherein each of the second plurality of layers are substantially parallel to each other (see Fig. 8C),
wherein the second epitaxial material (46 on right) separates each of the second plurality of layers (52 on right) from another;
a second spacer (gate spacer 56 on right) that surrounds an edge of the layer (56 on right) between a first side of the layer (left) and a second side (right) of the layer opposite the first side;
the second spacer (56 on right) in direct physical contact with the second plurality of layers of gate electrode materials (52 on right),
Hashemi fails to teach:
wherein the first epitaxial material is vertically intervening between the substrate and a bottommost surface of the first plurality of layers of gate electrode material;
and wherein the second epitaxial material is vertically intervening between the substrate and a bottommost surface of the second plurality of layers of gate electrode material;
wherein a volume of the second epitaxial material adjacent to the spacer of each of the second plurality of layers of gate material is defect free.
More teaches in Fig. 20:
and wherein the epitaxial material (buffer layer 203 in addition to channel members 2080 and source drain features 244 which are analogous to the epitaxial features of Hashemi) is vertically intervening between the substrate (substrate 201) and a bottommost surface of the gate electrode material (gate electrode 260);
wherein a volume of the second epitaxial material adjacent to the spacer of each of the second plurality of layers of gate material is defect free. ([0019] “When the buffer layer 203 of a sufficient thickness is epitaxially deposited on the substrate 201 as shown in FIG. 2, lattice defects may only be present at or near an interface 203I with the substrate 201 but do not propagate through the thickness of the buffer layer 203. This is because the lattice strain may be gradually released with the distance from the interface 203I. In an ideal case, a top surface of the buffer layer 203 may include germanium lattice structures that are substantially defect-free. The top surface of the buffer layer 203 therefore serves as a low-lattice-strain foundation for the formation of the stack 204. In some embodiments, the buffer layer 203 includes germanium (Ge) that is undoped or not intentionally doped. To sufficiently release the lattice strain at the interface 203I, the buffer layer 203 may have a first thickness T1 between about 50 nm and about 200 nm. This thickness is not trivial. When the thickness of the buffer layer 203 is smaller than 50 nm, the lattice defect density on the top surface of the buffer layer 203 may still be too high, preventing formation of high-quality stack 204”)
Hashemi discloses the claimed invention except for the epitaxial material including a layer between the substrate and the gate electrode and a defect free volume of the epitaxial layers. More teaches that it is known to epitaxially grow a buffer layer between the substrate and gate electrode as set forth in para. [0022] and Fig. 20 that leads to defect free epitaxial layers. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Hashemi to include a buffer layer between the substrate and gate in the epitaxial layers of the transistors, as taught by More, in order to transition between the substrate and the channel layers in a way that prevents defects in the substrate from causing defects in the epitaxial layers. See MPEP 2144.
With respect to claim 12, Hashemi further teaches:
wherein the first epitaxial material and the second epitaxial material are a same material (Hashemi teaches that the nanowires 46 are silicon for both the left and right transistor and that the source/drain regions may be the same material on both sides of the device).
With respect to claim 14, Hashemi further teaches:
wherein the first epitaxial material and the second epitaxial material are on a same substrate (substrate 32, 34). (See Fig. 8C)
With respect to claim 15, Hashemi further teaches:
wherein the substrate is a silicon substrate. (para. 22 “The base layer 32 can be bulk silicon”)
With respect to claim 16, Hashemi further teaches:
wherein a material of the first spacer and the second spacer includes a selected one or more of: silicon, nitrogen, oxygen, silicon nitride, silicon oxide, silicon oxynitride, silicon nitride oxide, or carbon films. (para 31 “The spacers can be formed by depositing a dielectric film such as silicon nitride and etching the dielectric film from all horizontal surfaces by RIE”)
With respect to claim 17, Hashemi further teaches:
wherein the gate material includes a selected one or more of: tungsten, titanium, titanium nitride, silver, indium, or cadmium (para. 27, “The gate conductors may be comprised of metals such as TiN, TaN, W, WN, TaAlN, Al, Au, Ag, or a combination of such metals”)
Claims 13 is rejected under 35 U.S.C. 103 as being unpatentable over Hashemi (US 2017/0200832 A1) and More (US 2023/0058459 A1) as applied to claim 11 above and in view of Liaw (US 2021/0083054 A1) and Fulford (US 2021/0104523 A1).
With respect to claim 13, Hashemi/More teaches all limitations of claim 11 upon which claim 13 depends. Hashemi further teaches:
wherein the first epitaxial material is silicon (Si) (nanowires 46 formed from silicon layers 38 (para. 26) which are epitaxial per para. 23 “layers 36 are grown epitaxially in alternating sequence with the silicon layers 38 using a blanket layer deposition process.”, para. 33 teaches that the s/d regions may also be doped silicon)
Hashemi/More fails to teach:
and the second epitaxial material is silicon germanium (SiGe)
However, Hashemi teaches in para. 33 that if “Boron doped SiGe regions may be employed to form pFET structures”
Liaw teaches in para. 38:
“The semiconductor device includes a substrate having a first region and a second region; a first n-type gate-all-around (GAA) transistor and a first p-type GAA transistor in the first region”
Fulford teaches in para. 1:
“For a p-type transistor, a SiGe channel can improve the mobility and thus the on current can increase at the same off current.”
Hashemi modified by Liaw such that the two transistors include a p-type and n-type transistor integrated on the same substrate and further modified by Fulford to use SiGe for the channel of the p-type transistor teaches:
and the second epitaxial material is silicon germanium (SiGe) (Hashemi teaches in para. 33 that if “Boron doped SiGe regions may be employed to form pFET structures”” Fulford teaches the use of a SiGe channel for a p-type transistor.
Hashemi/More discloses the claimed invention except that the device of Hashemi/More uses the same epitaxial material (channel and source/drain) for each transistor. Liaw teaches that it is known to integrate a n-type transistor and a p-type transistor on the same substrate and Fulford teaches that it is known to use SiGe as a channel material for a p-type gate all around transistor. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Hashemi/More to comprise transistors of both n-type and p-type as taught by Liaw and use Si as the epitaxial material of the n-type as taught by Hashemi and SiGe as the epitaxial material for the p-type as taught by Hashemi and Fulford, since Liaw states para. 12 that such a modification would allow for the integration of different devices to meet requirements for different applications and since Fulford states in para. 1 that SiGe channels improve the mobility of p-type transistors. See MPEP 2144.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights