DETAILED ACTION
Response to Amendment
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-11, 13-19, and 21-22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding Claims 1, 9, and 16, in lines 6-8, 8-9, and 6-8, respectively, it is stated “wherein the one or more reference clocks are generated with adjustments by the system PLL circuitry to compensate for different respective skews”. However, the originally filed specification does not support this feature. The specification states “the system PLL circuit 26 may, in response to receiving the primary reference clock 25 from the reference clock source, generate a number of reference clocks 27. The reference clocks 27 may be identical to the primary reference clock 25 or otherwise based on the primary reference clock 25. The system PLL circuit 26 may supply the reference clocks 27 to the PLL circuits 24 in the integrated circuit device 10 through routing circuitry. In some embodiments, the reference clocks 27 received by the PLL circuits 24 may be identical or nearly identical to each other. Alternatively, the reference clocks 27 may be adjusted to reduce skew by driving the reference clocks 27 differently to account for various delays, such as propagation delays and process corners.” Specification, paragraph 0018. As can be seen, this paragraph does not state that the system PLL 26 is the device that makes the adjustments to compensate for the different respective skews. The specification does not provide any details of which device performs this function and does not provide details of how the system PLL 26 can perform the function. Accordingly, the claims add new matter.
Regarding Claims 1, 9, and 16, in lines 6-10, 8-12, and 6-10, respectively, it is stated “generate one or more reference clocks from the external reference clock, wherein the one or more reference clocks are generated with adjustments by the system PLL circuitry to compensate for different respective skews based at least in part on different propagation delays of the plurality of chiplets and the routing and interconnections therebetween”. This could be taken to mean that the system PLL generates a single reference clock from the external reference clock. Based on this interpretation of the claim language, the system PLL would then have to generate the single reference clock “with adjustments by the system PLL circuitry to compensate for different respective skews based at least in part on different propagation delays of the plurality of chiplets and the routing and interconnections therebetween”. But Figure 2 and paragraph 0018 of the specification do not support this feature. Rather, the system PLL 26 supplies a plurality of reference clocks to the plurality of chiplets 12-22 and an adjustment is made to compensate for the skew for the chiplets 12-22. As can be seen, there is not a single reference clock that is supplied to all of the chiplets 12-22 that is adjusted to compensate for skew for all of them. Rather, there are a plurality of reference clocks generated that are each adjusted for skew to the various chiplets 12-22. Accordingly, the claims add new matter.
All claims that are not specifically addressed are rejected due to a dependency.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9, 10, 13-19, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Self et al. (U.S. Patent Number 6,112,308), Kashem et al. (U.S. Patent Application Publication Number 2023/0205252), and Logue et al. (U.S. Patent 7,564,283).
Regarding Claim 1, Self discloses a device (Figure 6) comprising:
system phase lock loop (PLL) circuitry (Figure 6, item 600, Column 8, lines 47-49; i.e., the “multiple PLL integrated circuit” 600 is equivalent to the claimed “system PLL circuitry”) to:
receive an external reference clock from outside of the device as the only PLL circuitry receiving the external reference clock at the device (Figure 6, item 670);
generate one or more reference clocks from the external reference clock (Figure 6, item 680, Column 8, lines 38-55); and
transmit the one or more reference clocks to the plurality of chips (Column 8, lines 38-55; i.e., a reference clock signal is sent from the system PLL to the multiple PLLs located within items 684 and 694, which are located within integrated circuit chips 682 and 692); and
a plurality of PLL circuitries on the plurality of chips (Figure 6, see plural PLLs located within items 684 and 694, Column 8, lines 38-55; i.e., each of the plurality of PLLs within items 684 and 694 are located within the integrated circuit chips 682 and 692) to:
receive respective reference clocks of the one or more reference clocks at the plurality of chips using inter-die communications (Column 8, lines 38-55; i.e., there are multiple integrated circuit dies 600, 682, and 692; therefore, the clock communications that occur between these various dies is equivalent to the claimed “inter-die communications”),
generate respective sub-reference clocks from the received respective reference clocks (Column 8, lines 41-44; i.e., each PLL of the plurality of PLLs within items 684 and 694 provides a sub-reference clock to its associated subsystem), and
transmit the respective sub-reference clocks from respective PLL circuitries of the plurality of PLL circuitries to drive operations of the plurality of chips (Figure 6, subsystems 1 and 2 within integrated circuits 682 and 692) using the respective sub-reference clocks, wherein one or more of the respective sub-reference clocks drive one or more chip of the plurality of chips (Column 8, lines 41-44; i.e., the subsystems 1 and 2 operate based on [are driven by] the respective sub-reference clocks received from the associated PLLs located within items 684 and 694), and the plurality of PLL circuitries and their respective plurality of chiplets do not directly receive any external reference clocks from outside of the device (Figure 6; i.e., the plural PLLs located within items 684 and 694 only receive the reference clock from item 600, which is within the device shown in Figure 6).
Self does not expressly disclose a plurality of chiplets; and
wherein the system PLL circuitry is to generate one or more reference clocks from the external reference clock, wherein the one or more reference clocks are generated with adjustments by the system PLL circuitry to compensate for different respective skews based at least in part on different propagation delays of the plurality of chiplets and the routing and interconnections therebetween.
In the same field of endeavor (e.g., clock synchronization techniques), Kashem teaches a plurality of chiplets (Figure 4, items 430, paragraphs 0022-0023).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Kashem’s teachings of clock synchronization techniques with the teachings of Self, for the purpose of increasing flexibility and scalability, reduced manufacturing costs, and enhanced performance by allowing for modular design, enabling manufacturers to mix and match different chiplets to create customized solutions and improve yields (these are all known advantages of chiplets) and further for the purpose of ensuring that all of the clocks are received in synchronization to the chiplets based on the particular needs of the circuit design.
Also in the same field of endeavor (e.g., clock synchronization techniques), Logue teaches wherein the system PLL circuitry (Figure 3, item 300) is to generate one or more reference clocks (Figure 3, item O_CLK) from the external reference clock (Figure 3, item REF_CLK), wherein the one or more reference clocks are generated with adjustments by the system PLL circuitry (Column 3, lines 9-15 and Column 13, lines 8-28) to compensate for different respective skews based at least in part on different propagation delays of the plurality of chips (Figure 3, item 190, Column 2, lines 1-3 and Column 14, lines 19-23) and the routing and interconnections therebetween (Column 1, lines 62-65).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Logue’s teachings of clock synchronization techniques with the teachings of Self, for the purpose of being able to maintain synchronization amongst the plurality of chiplets. More specifically, by compensating for different amounts of skew of the various chiplets, each chiplet would be able to receive data at substantially the same time.
Regarding Claim 2, Self discloses the plurality of chiplets, wherein each chiplet of the plurality of chiplets comprises a PLL circuitry of the plurality of PLL circuitries (Figure 6, item 684, Column 8, lines 38-55).
Regarding Claim 3, Self discloses wherein one of the plurality of chiplets comprises the system PLL circuitry (Column 8, lines 49-51; i.e., the system PLL is located within an integrated circuit chip 600).
Regarding Claim 4, Self discloses a system PLL chiplet that comprises the system PLL circuitry (Column 8, lines 49-51; i.e., the system PLL is located within an integrated circuit chip 600).
Regarding Claim 5, Self discloses the plurality of chiplets, wherein a chiplet of the plurality of chiplets comprises a corresponding PLL circuitry of the plurality of PLL circuitries and drives at least two chiplets of the plurality of chiplets (Column 9, lines 15-20; i.e., there may be a chain or cascade of PLL circuits).
Regarding Claim 6, Kashem teaches wherein the at least two chiplets are similar chiplets (paragraph 0022).
Regarding Claim 7, Kashem teaches wherein the at least two chiplets have a same function type (paragraph 0022; i.e., the plurality of chiplets have a slave function type).
Regarding Claim 9, Self discloses a multi-die package (Figure 6) comprising:
first system phase lock loop (PLL) circuitry (Figure 6, item 600, Column 8, lines 47-49; i.e., the “multiple PLL integrated circuit” 600 is equivalent to the claimed “first system PLL circuitry”) to:
receive an external reference clock from outside of the multi-die package as the only PLL circuitry receiving the external reference clock at the multi-die package (Figure 6, item 670);
generate a first one or more reference clocks from the external reference clock (Figure 6, item 680, Column 8, lines 38-55); and
transmit the first one or more reference clocks (Column 8, lines 38-55; i.e., a reference clock signal is sent from the system PLL to the multiple PLLs located within item 684); and
a plurality of PLL circuitries on a plurality of chips of the multi-die package (Figure 6, see plural PLLs located within items 684 and 694, Column 8, lines 38-55; i.e., each of the plurality of PLLs within items 684 and 694 are located within the integrated circuit chips 682 and 692 [the claimed “multi-die package”]) to receive the first one or more reference clocks at the plurality of chips using inter-die communications (Column 8, lines 38-55; i.e., there are multiple integrated circuit dies 600, 682, and 692; therefore, the clock communications that occur between these various dies is equivalent to the claimed “inter-die communications”), wherein the plurality of PLL circuitries and respective pluralities of chips do not receive any external reference clocks from outside of the multi-die package (Figure 6; i.e., the plural PLLs located within item 684 only receive the reference clock from item 600, which is within the device shown in Figure 6).
Self does not expressly disclose a plurality of chiplets; and
wherein the system PLL circuitry is to generate one or more reference clocks from the external reference clock, wherein the one or more reference clocks are generated with adjustments by the system PLL circuitry to compensate for different respective skews based at least in part on different propagation delays of the plurality of chiplets and the routing and interconnections therebetween.
In the same field of endeavor, Kashem teaches a plurality of chiplets (Figure 4, items 430, paragraphs 0022-0023).
Also in the same field of endeavor, Logue teaches wherein the system PLL circuitry (Figure 3, item 300) is to generate one or more reference clocks (Figure 3, item O_CLK) from the external reference clock (Figure 3, item REF_CLK), wherein the one or more reference clocks are generated with adjustments by the system PLL circuitry (Column 3, lines 9-15 and Column 13, lines 8-28) to compensate for different respective skews based at least in part on different propagation delays of the plurality of chips and the routing and interconnections therebetween (Column 1, lines 62-65 and Column 2, lines 1-3).
The motivation discussed above with regards to Claim 1 applies equally as well to Claim 9.
Regarding Claim 10, Self discloses wherein the first plurality of PLL circuitries generates respective sub-reference clocks from the first one or more reference clocks and transmits the respective sub-reference clocks to drive operations of a plurality of chips (Column 8, lines 41-44; i.e., the subsystems 1 and 2 [the “plurality of chips”] operate based on [are driven by] the respective sub-reference clocks received from the associated PLLs located within item 684).
Self does not expressly disclose a plurality of chiplets.
In the same field of endeavor, Kashem teaches a plurality of chiplets (Figure 4, items 430, paragraphs 0022-0023).
The motivation discussed above with regards to Claim 1 applies equally as well to Claim 10.
Regarding Claim 13, Self discloses a plurality of dedicated PLL chips that comprises the plurality of PLL circuitries (Figure 6, items 684 and 694, Column 8, lines 41-44; i.e., the PLL circuits may be in the form of integrated circuit chips [Kashem teaches a plurality of chiplets - see Figure 1, items 110, paragraph 0064]).
Regarding Claim 14, Self discloses a plurality of chiplets driven using the first one or more reference clocks, wherein the plurality of chiplets comprises the plurality of PLL circuitries (Figure 6, item 684, Column 8, lines 38-55).
Regarding Claim 15, Self discloses a plurality of chiplets driven using the first one or more reference clocks (Figure 6, items 684 and 694, Column 8, lines 41-44; i.e., the PLL circuits may be in the form of integrated circuit chips), and
an interconnect of the interconnections that connects at least two of the plurality of chips (Figure 6, item 600), wherein at least one of the plurality of PLL circuitries is located on the interconnect (Figure 6; i.e., item 600, which contains plural PLL circuitries, interconnects the plurality of integrated circuit chips 682 and 692 [Kashem teaches a plurality of chiplets - see Figure 4, items 430, paragraphs 0022-0023]).
Regarding Claim 16, Self discloses a multi-die package (Figure 6) comprising:
system phase lock loop (PLL) circuitry (Figure 6, item 600, Column 8, lines 47-49; i.e., the “multiple PLL integrated circuit” 600 is equivalent to the claimed “system PLL circuitry”) to:
receive an external reference clock from outside of the multi-die package as the only PLL circuitry receiving the external reference clock at the multi-die package (Figure 6, item 670),
generate first reference clocks from the external reference clock (Figure 6, item 680, Column 7, lines 56-67 and Column 8, lines 38-55; i.e., plural first reference clocks can be provided through the use of the programmable divider/counter, each having a different frequency), and
transmit the first reference clocks (Column 8, lines 38-55; i.e., a reference clock signal is sent from the first system PLL to the multiple PLLs located within item 684); and
a first plurality of PLL circuitries on a first plurality of chips (Figure 6, see plural PLLs located within items 684 and 692, Column 8, lines 38-55; i.e., each of the plurality of PLLs within items 684 and 694 are located within the integrated circuit chips 682 and 692) to:
receive the first reference clocks at the plurality of chips using inter-die communications (Column 8, lines 38-55; i.e., there are multiple integrated circuit dies 600, 682, and 692; therefore, the clock communications that occur between these various dies is equivalent to the claimed “inter-die communications”);
generate first sub-reference clocks from the first reference clocks (Column 8, lines 41-44; i.e., each PLL of the plurality of PLLs within item 684 provides a sub-reference clock to its associated subsystem); and
transmit the first sub-reference clocks from the first plurality of PLL circuitries to drive operation of the first plurality of chips (Column 8, lines 41-44; i.e., the subsystems 1 and 2 operate based on [are driven by] the respective sub-reference clocks received from the associated PLLs located within item 684), wherein the first plurality of PLL circuitries and the first plurality of chips do not receive any external reference clocks from outside of the multi-die package (Figure 6; i.e., the plural PLLs located within item 684 only receive the reference clock from item 600, which is within the device shown in Figure 6); and
a second plurality of PLL circuitries (Figure 6, see any additional plural PLLs located within item 684, Column 8, lines 38-55) to:
receive the first reference clocks (Column 8, lines 38-55);
generate second sub-reference clocks from the first reference clocks (Column 8, lines 41-44; i.e., each PLL of the plurality of additional PLLs within item 684 provides a sub-reference clock to its associated subsystem); and
transmit the second sub-reference clocks from the second plurality of PLL circuitries to drive operation of a second plurality of chips (Column 8, lines 41-44; i.e., the subsystems 1 and 2 operate based on [are driven by] the respective sub-reference clocks received from the associated PLLs located within item 694), wherein the second plurality of PLL circuitries and the second plurality of chips do not receive any external reference clocks from outside of the multi-die package (Figure 6; i.e., the plural additional PLLs located within item 684 only receive the reference clock from item 600, which is within the device shown in Figure 6).
Self does not expressly disclose a first and second plurality of chiplets; and
wherein the system PLL circuitry is to generate one or more reference clocks from the external reference clock, wherein the one or more reference clocks are generated with adjustments by the system PLL circuitry to compensate for different respective skews based at least in part on different propagation delays of the plurality of chiplets of the multi-die package and the routing and interconnections therebetween.
In the same field of endeavor, Kashem teaches first and second plurality of chiplets (Figure 4, items 430, paragraphs 0022-0023).
Also in the same field of endeavor, Logue teaches wherein the system PLL circuitry (Figure 3, item 300) is to generate one or more reference clocks (Figure 3, item O_CLK) from the external reference clock (Figure 3, item REF_CLK), wherein the one or more reference clocks are generated with adjustments by the system PLL circuitry (Column 3, lines 9-15 and Column 13, lines 8-28) to compensate for different respective skews based at least in part on different propagation delays of the plurality of chips of the multi-die package and the routing and interconnections therebetween (Column 1, lines 62-65 and Column 2, lines 1-3).
The motivation discussed above with regards to Claim 1 applies equally as well to Claim 16.
Regarding Claim 17, Self discloses the first plurality of chiplets, wherein the first plurality of PLL circuitries are not disposed on the first plurality of chiplets (Figure 6; i.e., this would be the case if subsystems 1 and 2 within item 682 were interpreted as the claimed “first plurality of chiplets”).
Regarding Claim 18, Self discloses the first plurality of chiplets, wherein the first plurality of PLL circuitries are disposed on the first plurality of chiplets (Figure 6, item 684, Column 8, lines 38-55).
Regarding Claim 19, Self discloses the second plurality of chiplets, wherein the second plurality of PLL circuitries are not disposed on the second plurality of chiplets (Figure 6; i.e., this would be the case if subsystems 1 and 2 within item 692 were interpreted as the claimed “second plurality of chiplets”).
Regarding Claim 21, Kashem teaches wherein the interconnections comprise an embedded multi-die interconnect bridge (Figure 2, items 205 and 215, paragraph 0017; i.e., data traverses the interconnections of the various logic units 220; the interconnections between the logic units 220 act as “bridges”; these logic units 220 may be embedded on a multi-die package [paragraphs 0002 and 0022]).
Regarding Claim 22, Logue teaches wherein the one or more reference clocks are generated with the adjustments by the system PLL circuitry to compensate for different respective skews based at least in part on different process corners (Column 25, lines 26-30; i.e., a fast-fast corner of each logic circuit 190) of the plurality of chiplets and the routing and interconnections therebetween (Column 3, lines 9-15 and Column 13, lines 8-28).
Claims 8 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Self, Kashem, and Logue as applied to claims 1 and 10 above, and further in view of Bajaj et al. (U.S. Patent Application Publication Number 2004/0104750).
Regarding Claim 8, Self, Kashem, and Logue do not expressly disclose wherein the system PLL circuitry is to disable transmission of at least one of at least one of the one or more reference clocks to place a corresponding at least one of the chiplets in an idle mode.
In the same field of endeavor (e.g., clock synchronization techniques), Bajaj teaches wherein the system PLL circuitry (Figure 2) is to disable transmission of at least one of at least one of the one or more reference clocks to place a corresponding at least one of the chiplets (Figure 2, item 209) in an idle mode (paragraph 0031; i.e., the clock is terminated from point 206 onward to the chiplet 209 is placed in an idle mode).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Bajaj’s teachings of clock synchronization techniques with the teachings of Self, Kashem, and Logue, for the purpose of reducing power consumption of the integrated circuit when the clock is not needed.
Regarding Claim 11, Self, Kashem, and Logue do not expressly disclose wherein the first system PLL circuitry disables transmission of at least one of the first one or more reference clocks to place an at least one of the chiplets in an idle mode.
In the same field of endeavor (e.g., clock synchronization techniques), Bajaj teaches wherein the first system PLL circuitry (Figure 2) disables transmission of at least one of the first one or more reference clocks to place an at least one of the chiplets (Figure 2, item 209) in an idle mode (paragraph 0031; i.e., the clock is terminated from point 206 onward to the chiplet 209 is placed in an idle mode).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Bajaj’s teachings of clock synchronization techniques with the teachings of Self, Kashem, and Logue, for the purpose of reducing power consumption of the integrated circuit when the clock is not needed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses a device for cascading a plurality of phased lock loop circuits.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 6/18/26 have been fully considered but they are not persuasive.
Regarding Claim 21, Applicant argues “[i]tems 205 and 215 in Kashem are pipeline registers rather than an embedded multi-die interconnect bridge (EMIB). An EMIB is a specific type of silicon bridge embedded in a package substrate that provides high-density die-to-die interconnections. The teaching of Kashem does not support the rejection of claim 21.” Response, page 3. However, the argued claim does not contain this feature. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., an EMIB is a specific type of silicon bridge embedded in a package substrate that provides high-density die-to-die interconnections) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Kashem teaches that data traverses the interconnections of the various logic units 220. See Figure 2, items 205 and 215, paragraph 0017. The interconnections between the logic units 220 act as “bridges”. These logic units 220 may be embedded on a multi-die package. See id. at paragraphs 0002 and 0022. Accordingly, Kashem teaches the argued feature.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL M ZAMAN, ESQ. whose telephone number is (571)272-6495. The examiner can normally be reached Monday - Friday, 8 am - 5 pm, alternate Fridays.
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/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175
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