Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Previous objections to the drawings are now withdrawn.
Claim Rejections - 35 USC § 112
Previous rejections based on 35 USC 112 are now withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 5 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Amo et al. (US Pat. Pub. 2003/0006444).
Regarding claim 1, Amo teaches an integrated circuit (IC) device structure comprising:
one or more gate electrodes, each adjacent to a channel region comprising a semiconductor material [fig. 8, 5, 6 and 7 are gates on semiconductor material 1 with channel under gates];
a source and a drain, each coupled to the semiconductor material, wherein one of the gate electrodes is between the source and the drain [fig. 8, 11 and 12 with gates 5/6/7 between source/drain regions];
a first terminal contact metallization in contact with a first of the source or drain [fig. 8, 13 on the right side of gate 5 in the logic sram region];
a second terminal contact metallization in contact with a second of the source or drain [fig. 8, 13 on the left side of gate 5 in the logic sram region]; and
a jumper metallization in contact with a top surface of a first of the gate electrodes and in contact with a top surface of the first terminal contact metallization, [fig. 8, 48 in contact with a top surface of gate 6 (fig. 6 shows gate six, the number omitted in fig 8), and a top surface of 13 to the left of gate 6 and the right of gate 5 in the logic sram region].
A dielectric material over the one or more gate electrodes, over the first terminal contact metallization, over the second terminal contact metallization, and over the jumper metallization [fig. 8, 21];
A line metallization over the dielectric material layer [fig. 8, 35]; and
A via metallization extending through the dielectric material layer, wherein the via metallization is in contact with the line metallization and in contact with the second terminal contact metallization [fig. 8, 46/56 in contact with 13 on the left side of gate 5 in the logic sram region].
Regarding claim 2, Amo discloses the IC device structure of claim 1, wherein the jumper metallization has the same composition as the via metallization [paragraphs [0057, 0063 and 0069] teach via metallization 46/56 and jumper metallization 48 are W].
Regarding claim 3, Amo teaches the IC device structure of claim 2, further comprising a gate contact metallization in contact with one of the one or more gate electrodes, wherein a top surface of the gate contact metallization is coplanar with a top surface of the dielectric material layer [fig. 8, 26 is in electrical contact with gate 6, top surface coplanar with 21], and wherein at least two of the via metallization, the gate contact metallization, and the jumper metallization have substantially the same composition [paragraphs [0057, 0063 and 0069] teach via metallization 46/56 and jumper metallization 48 are W].
Regarding claim 5, Amo discloses the IC device structure of claim 2, wherein the jumper metallization has a different composition than both of the first terminal contact metallization and the one or more gate electrodes [paragraph [0049] teaches terminal contact metallization is silicide, it also teaches cobalt silicide is formed over gate electrodes 5 and 7, the gates are therefore silicon or polysilicon, paragraph [0063] teaches jumper 48 is W].
Response to Arguments
Applicant's arguments filed 2 January 2026 have been fully considered but they are not persuasive. Applicant argues that Amo does not teach the jumper metallization positioned over a top surface of a gate electrode and first terminal contact metallization but under a top of via metallization that interconnects second terminal contact metallization with overlying line metallization. As shown in the rejection above, applicants amendments have caused a reinterpretation of the structure Amo and all features in claim 1 are anticipated.
Allowable Subject Matter
Claims 11-14 and 21-24 are allowed.
Claims 4 and 6-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 11, the prior art fails to disclose or suggest the device as claimed. Specifically, the prior art fails to teach a second jumper metallization interconnects a drain of the second pull-up transistor to a gate electrode of the first pull-up transistor; and a top of the first and second jumper metallizations is at a first heigh that is below a second height of a top of the via metallization.
Regarding claim 21, the prior art fails to disclose or suggest the device as claimed. Specifically, the prior art fails to teach a first jumper metallization interconnects the first source contact metallization or first drain contact metallization to a gate electrode of the second transistor structure and a second jumper metallization interconnects the second source contact metallization or the second drain contact metallization to a gate electrode of the first transistor structure, a top of the first and second jumper metallizations is at a first height which is below a second height of the a top of the via metallization.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M PARKER whose telephone number is (571)272-8794. The examiner can normally be reached M-F 7:30am - 3:30pm.
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/JOHN M PARKER/Examiner, Art Unit 2899