DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Request for Continued Examination1. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/27/2026 has been entered.
Status of Claims2. This Office Action is in response to amendment filed: 4/27/2026.
Claims 1-7, 9-12, 14-16, and 18-25 are pending.
Claims 8, 13, 17 are canceled. Claims 23-25 are newly added.
Response to Arguments
3. Applicant argued that Cole and Florent do not disclose and teach limitations: “a laser source to output a beam of photons focused into a target portion of semiconductor material in the DUT” in claim 1 and “heating a target portion of semiconductor material in an IC device under test (DUT) by exposing the target portion of semiconductor material to a laser beam” in claim 14. The examiner respectfully disagrees. Cole clearly discloses an IC failure analysis system (Fig. 1) is configured to control a light scanner (24) by focusing a laser beam (20) to probe an IC (100) and produce localized heating which changes the incidence of the functional failures in the IC which can be sensed for locating the IC circuit elements responsible for the functional failures (see at least in the abstract), a laser producing a beam having a photon energy that is less than a bandgap energy of a substrate (e.g. a silicon substrate) whereon the IC is formed; means for focusing and scanning the laser beam across the IC, thereby producing localized heating within the IC that generates a change in the fraction of defective output states from the IC (see at least in column 3, lines 17-25); or the IC substrate comprises silicon and scanning the IC with the focused laser beam from a backside of a substrate whereon the IC is formed, with the focused laser beam being transmitted through the substrate (see column 6, lines 10-12).Therefore, Cole clearly teaches claim limitations “a laser source to output a beam of photons focused into a target portion of semiconductor material in the DUT” in claim 1 and “heating a target portion of semiconductor material in an IC device under test (DUT) by exposing the target portion of semiconductor material to a laser beam” in claim 14. Florent clearly discloses an analyzing system (Figs. 3-6) for analyzing the temperature reliability of an electronic component (10) which includes an electronic chip (12), the chip (12) comprises a silicon substrate (14). For increasing the stress test, two laser beams (33) can be arranged on either side of the electronic component (10) to stimulate an elementary structure independently of the position of the coupling element (25). A first laser source is then arranged to stimulate component (10) from the front face (17) and a second laser source is arranged to stimulate component (10) from the rear face (18). The two laser sources must emit beams of different wavelengths determined according to the layers (13-15) of materials that the laser beams must pass through to solicit the same area of interest (see paragraph [0045]). The wavelength λ of the laser source beam must be greater than 1.1 μm if the beam is required to pass through the silicon substrate (see paragraphs [0051-52]). The laser beam (33) is focused into an area of the chip (12) which is considered as a target area for the beam to pass thru. In this case, the laser beam (33) passes through the silicon substrate (14), the silicon substrate is considered as a target portion of the semiconductor material in the DUT or chip (12).Therefore, Florent clearly teaches claim limitations “a laser source to output a beam of photons focused into a target portion of semiconductor material in the DUT” in claim 1 and “heating a target portion of semiconductor material in an IC device under test (DUT) by exposing the target portion of semiconductor material to a laser beam” in claim 14.
Examiner Notes
4. Examiner cites particular paragraphs, columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 1, 6, 7, 12, 14-15, 19, and 23-25 are rejected under 35 U.S.C. 103 as being unpatentable over Cole et al. (US. Pat. 6549022; hereafter “Cole”) in view of Florent et al. (WO-2014166701; hereinafter “Florent”).
Regarding claim 1, Cole discloses, in Figs. 1-4, an integrated circuit (IC) device testing apparatus (an IC analysis apparatus 10 in Fig. 1), comprising: a stage (a stage 14) comprising an area to support an IC device under test (DUT) (IC 100); a laser source (a laser source 18) to output a beam of photons (a laser beam 20 comprising the photon energy. See Col. 10 lines20-35) focused into a target portion of semiconductor material in the DUT (see at least in Col. 3, lines 18-25, Col. 3, lines 46-55); a controller (such as a tester 12) to heat with the beam a target portion of the DUT for a predetermined time (“changing a power level of the focused laser beam 20 to change the amount of localized heating produced within the IC 100”, see Col. 9 lines 25-40 and Col. 9 line 65- to Col. 10 line 5. “controlling operational parameters of the IC to induce the level of incidence of the functional failures therein comprises controlling a voltage for powering the IC, controlling the temperature of the IC, controlling a clock frequency and the set of input test vectors is provided to the IC, controlling a power level of the focused laser beam…”, see claim 48); a controller to heat with the beam the target portion of semiconductor material for a predetermined time to alter circuitry blocks of the DUT through one or more thermally enhanced physical aging phenomena (“a laser producing a beam having a photon energy that is less than a bandgap energy of a substrate (e.g. a silicon substrate) whereon the IC is formed; means for focusing and scanning the laser beam across the IC, thereby producing localized heating within the IC that generates a change in the fraction of defective output states from the IC, the focusing and scanning means further providing a position signal to indicate the location of the laser beam on the IC at any instant in time”; see Col. 3, lines 17-25. Also see Col. 8, lines 7-24.) and an electrical test interface (such as a socket positioned on the stage for making electrical connections to from the IC 100 and the tester. See Col. 9 lines 12-25) to operate the DUT during, or after, the predetermined time (see Col. 9 lines 12-65).
Cole does not explicitly specify the controller to heat with the beam so that permanently alter circuitry blocks of the DUT through one or more thermally enhanced physical aging phenomena.
Florent discloses an analysis device (Fig. 2) for analyzing the operation of electronic components subjected to thermal stresses during a reliability test or aging test (see paragraphs [0004-5]), comprising a laser source (32) applied heat with a laser beam (33) a target portion (20) of a DUT (an electronic chip 12)( the energy of the laser source 30 is adjusted so that the temperature at the surface of the chip 12 is +200 °C. see [0045]) so that to permanently alter circuitry blocks of the DUT through one or more thermally enhanced physical aging phenomena (“methods for analyzing component failures using laser heating that can identify areas of a semiconductor component that have undergone degradation” in [0014]. “During a procedure to analyze the reliability of an electronic component, it is common to subject the component in operation to a thermal stress (this is then called a functional test) in order to accelerate the aging of said integrated circuit (this is then called an aging test)” in [0005].).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the laser source in the IC analysis apparatus of Cole by having the laser source applied heat with the beam a target portion of the DUT so that to permanently alter circuitry blocks of the DUT through one or more thermally enhanced physical aging phenomena, as taught by Florent for purpose of placing the chip under thermal stress in the area of interest by using the laser source which provided high thermal energy +200oC help to accelerate the aging of integrated circuit, saving time in process of evaluation during the reliability test of the electronic chip.
Regarding claim 6, Cole and Florent disclose the IC device testing apparatus of claim 1, Cole further teaches comprising a beam steering system coupled to the controller, the beam steering system to focus a spot of the beam within the target portion of the semiconductor material (see at least in Col.3 lines 45-55 and Col. 11 lines 28-50).
Regarding claim 7, Cole discloses the IC device testing apparatus of claim 6, Cole further teaches wherein the spot of the beam has a diameter no more than 2 μm (see at least in Col.3 lines 45-55).
Regarding claim 12, Cole discloses the IC device testing apparatus of claim 1, Cole further teaches wherein the electrical test interface comprises: a microprobe card comprising a microprobe array; a host applications board coupled to a power supply to power the IC device; or a probe card electrically coupled to automated test equipment (ATE) (see at least in Col. 7 lines 28-40, Col. 9 lines 13-25, and Fig. 1).
Regarding claim 14, Cole discloses a method of testing an integrated circuit (IC) device (an IC analysis apparatus 10 in Fig. 1), the method comprising: selectively heating a target portion of semiconductor material in an IC device under test (DUT)(100) by exposing the target portion to a laser beam by exposing the target portion of semiconductor material to a laser beam for a predetermined time to alter circuitry blocks of the DUT through one or more thermally enhanced physical aging phenomena (“a laser producing a beam having a photon energy that is less than a bandgap energy of a substrate (e.g. a silicon substrate) whereon the IC is formed; means for focusing and scanning the laser beam across the IC, thereby producing localized heating within the IC that generates a change in the fraction of defective output states from the IC, the focusing and scanning means further providing a position signal to indicate the location of the laser beam on the IC at any instant in time”; see Col. 3, lines 17-25. Also see Col. 8, lines 7-24.); and operating the DUT (100) during, or after, the predetermined time (see Col. 9 lines 12-65).
Cole does not explicitly specify the controller to heat with the beam so that permanently alter circuitry blocks of the DUT through one or more thermally enhanced physical aging phenomena.
Florent discloses an analysis device (Fig. 2) for analyzing the operation of electronic components subjected to thermal stresses during a reliability test or aging test (see paragraphs [0004-5]), comprising a laser source (32) applied heat with a laser beam (33) a target portion (20) of a DUT (an electronic chip 12)( the energy of the laser source 30 is adjusted so that the temperature at the surface of the chip 12 is +200 °C. see [0045]) so that to permanently alter circuitry blocks of the DUT through one or more thermally enhanced physical aging phenomena (“methods for analyzing component failures using laser heating that can identify areas of a semiconductor component that have undergone degradation” in [0014]. “During a procedure to analyze the reliability of an electronic component, it is common to subject the component in operation to a thermal stress (this is then called a functional test) in order to accelerate the aging of said integrated circuit (this is then called an aging test)” in [0005].).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the laser source in the IC analysis apparatus of Cole by having the laser source applied heat with the beam a target portion of the DUT so that to permanently alter circuitry blocks of the DUT through one or more thermally enhanced physical aging phenomena, as taught by Florent for purpose of placing the chip under thermal stress in the area of interest by using the laser source which provided high thermal energy +200oC help to accelerate the aging of integrated circuit, saving time in process of evaluation during the reliability test of the electronic chip.
Regarding claim 15, Cole and Florent disclose the method of claim 14, Cole further teaches wherein the DUT comprises a substrate material and exposing the target portion of semiconductor material to the laser beam further comprises passing the beam through a thickness of the substrate (see at least in Col. 3 lines 45-55 and Col. 8 lines 65 to Col. 8 line 25).
Regarding claim 19, Cole and Florent disclose the method of claim 14, Cole further teaches comprises globally heating the entire DUT with a second heat source while concurrently selectively heating the target portion of the semiconductor material with the laser beam (see at least in Col. 9 lines 25-40). Regarding claim 23, Cole and Florent disclose the IC device testing apparatus of claim 1, Cole further teaches wherein the target portion of semiconductor material is silicon (see at least in Col. 3, lines 17-25).
Regarding claim 24, Cole and Florent disclose the IC device testing apparatus of claim 1, Cole further teaches wherein the target portion of semiconductor material is at or below a device level, which comprises transistor structures (see at least in Col. 3 lines 17-25, and Col. 6, lines 10-12 and Figs. 3-4).
Regarding claim 25, Cole and Florent disclose the IC device testing apparatus of claim 1, Cole further teaches wherein energy in the beam is transferred to free carriers in the target portion of semiconductor material (see the summary).
7. Claims 2-5 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Cole in view of Florent and further in view of Myung et al. (US. Pub. 20210/370439; hereinafter “Myung”).
Regarding claim 2, Cole and Florent disclose the IC device testing apparatus of claim 1, except for explicitly specifying wherein the laser source has an average output power rating of at least 1 W.
Myung discloses, in Figs. 1-2, a laser source 20 provides a plurality of semiconductor chips 14 with a laser beam 22 whose radiation heat is used to heat up the semiconductor chips 14, the laser beam 22 outputs power rating of at least 1 W (see [0023]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the laser source of Cole and Florent for outputting power rating of at least 1W as taught by Cole, for purpose of meeting the system design and specification requirement.
Regarding claim 3, Cole and Florent and Myung disclose the device testing apparatus of claim 2, Cole further teaches wherein: the a semiconductor material having a bandgap; and the laser source has an output energy less than the bandgap (see at least in Col. 4 lines 10-25).
Regarding claim 4, Cole and Florent and Myung disclose the IC device testing apparatus of claim 2, Cole further teaches wherein the laser source has continuous wave output with a center wavelength of 1200 nm-1800 nm (see at least in Col. 3 lines 45-55).
Regarding claim 5, Cole and Florent and Myung disclose the IC device testing apparatus of claim 4, Florent further teaches wherein the output center wavelength is 1550 nm (see [0051-52]).
Regarding claim 16, Cole and Florent disclose the method of claim 14, wherein selectively heating the target portion of the DUT further comprises generating the laser beam with a continuous wave laser source having an output center wavelength of 1200 nm-1800 nm (see Col. 3 lines 45-55 of Cole), except for explicitly specifying that the laser beam with a continuous wave laser source having an output power rating of at least 1 W. Myung discloses, in Figs. 1-2, a laser source 20 provides a plurality of semiconductor chips 14 with a laser beam 22 whose radiation heat is used to heat up the semiconductor chips 14, the laser beam 22 outputs power rating of at least 1 W (see [0023]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the laser source of Cole and Florent for outputting power rating of at least 1W as taught by Cole, for purpose of meeting the system design and specification requirement.
8. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Cole in view of Florent and further in view of Ryu et al. (US. Pub. 2016/0049381; hereinafter “Ryu”).
Regarding claim 9, Cole and Florent disclose the IC device testing apparatus of claim 1, except for explicitly specifying wherein the target portion of semiconductor material is to reach a maximum temperature that is at least 150° C. greater than a second portion of the DUT not irradiated by the beam. Ryu discloses a laser beam heats a target portion of a semiconductor device or a circuit board is to reach a maximum temperature that is at least 150° C. greater than an area of the semiconductor device or the circuit board not irradiated by the laser beam (see [0013, 23, 53] and claims 16-17).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adjust the power of the laser beam of Cole and Florent so that the target portion is to reach a maximum temperature that is at least 150° C. greater than a second portion of the DUT not irradiated by the beam as taught by Ryu for purpose of enabling transferring heat energy derived from the laser beam only to a local region of the circuit board corresponding to the semiconductor die such that thermal expansion and/or shrinkage occurring to an entire region of the circuit board can be minimized, thus improving reliability in electrical connection between the semiconductor die and the circuit board. The method enables minimizing a bonding space using a laser emission system for locally emitting laser beams, thus improving space utilization efficiency.
9. Claims 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Cole in view of Florent.
Regarding claim 11, Cole and Florent disclose the IC device testing apparatus of claim 1, except for explicitly specifying that wherein the predetermined time is at least 12 hours. However, Florent discloses, in order to accelerate the aging of the IC chip for analyzing the reliability of the IC chip (DUT), a laser beam being used to heat up the DUT for a period of time during the thermal stress test. The total predetermined time to heat up the DUT in the reliability test would simply be a matter of inventor design choice. It depends on how the inventor want to apply the stress test level of the reliability test to the DUT. The higher energy of a laser beam applied to the DUT may have less the predetermined time than the lower energy of a laser beam applied to the same DUT. The chip is used for commercial sector that may have less the predetermined time than the same chip is used for industrial sector.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ an IC analysis system of Cole and Florent by setting the predetermined heating time for at least 12 hours, in order to meet the system design and specification requirement.
Regarding claim 18, Cole and Florent disclose the method of claim 14, except for explicitly specifying wherein the predetermined time exceeds 12 hours.
However, Florent discloses, in order to accelerate the aging of the IC chip for analyzing the reliability of the IC chip (DUT), a laser beam being used to heat up the DUT for a period of time during the thermal stress test. The total predetermined time to heat up the DUT in the reliability test would simply be a matter of inventor design choice. It depends on how the stress test level of the reliability test would be applied to the DUT. The higher energy of a laser beam applied to the DUT may have less the predetermined time than the lower energy of a laser beam applied to the same DUT. The chip is used for commercial sector that may have less the predetermined time than the same chip is used for industrial sector.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ an IC analysis system of Cole and Florent by setting the predetermined heating time for at least 12 hours, in order to meet the system design and specification requirement.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ an IC analysis system of Cole and Florent by setting the predetermined heating time for at least 12 hours, in order to meet the system design and specification requirement.
Allowable Subject Matter
10. Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
11. Claims 20-22 are allowed over the prior arts of record.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 20, the cited references, alone or in combination, do not disclose nor fairly suggest:
“ … selectively heating a first of the plurality of functional circuit blocks without heating a second of the functional circuit blocks by exposing the first of the functional circuit blocks to a
laser beam for a predetermined time sufficient to permanently alter circuitry blocks of the
DUT through one or more thermally enhanced physical aging phenomena; and
determining an amount of frequency degradation between a ring oscillator, phase locked loop, or
memory array in the first of the functional circuit blocks and a ring oscillator, phase
locked loop, or memory array in the second of the functional circuit blocks by operating
the plurality of functional circuit blocks during, or after, the predetermined time.” as claimed in claim 20.
As to claim(s) 21-22, the claims are allowed as they further limit allowed claim 20.
Prior Art of Record
12. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Horn (U.S Pat. 7019311) discloses a scanned, pulsed, focused laser irradiation apparatus can measure and image the photocurrent collection resulting from a dose-rate equivalent exposure to infrared laser light across an entire silicon die (see specification for more details).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANG LE whose telephone number is (571)272-9349. The examiner can normally be reached on Monday thru Friday 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached on (571) 272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THANG X LE/Primary Examiner, Art Unit 2858
7/29/2026
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