DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
1. This Office Action is in response to Amendment filed on date: 10/22/2025.
Claims 1-22 are currently pending.
Claims 1, 14, 18, 20-22 have been amended.
Claims 1, 14, and 20 are independent claims.
Response to Arguments
2. Applicant's arguments, see in pages 6-8 in the submitted remarks, filed on 10/22/2025, with respect to the rejection on claims 1-22 have been fully considered but are moot in view of the new ground(s) of rejection.
Examiner Notes
3. Examiner cites particular paragraphs, columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1, 6-7, 12-15, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Cole et al. (US. Pat. 6549022; hereafter “Cole”) in view of Florent et al. (WO-2014166701; hereinafter “Florent”).
Regarding claim 1, Cole discloses, in Figs. 1-4, an integrated circuit (IC) device testing apparatus (an IC analysis apparatus 10 in Fig. 1), comprising: a stage (a stage 14) comprising an area to support an IC device under test (DUT) (IC 100); a laser source (a laser source 18) to output a beam of photons (a laser beam 20 comprising the photon energy. See Col. 10 lines20-35); a controller (such as a tester 12) to heat with the beam a target portion of the DUT for a predetermined time (“changing a power level of the focused laser beam 20 to change the amount of localized heating produced within the IC 100”, see Col. 9 lines 25-40 and Col. 9 line 65- to Col. 10 line 5. “controlling operational parameters of the IC to induce the level of incidence of the functional failures therein comprises controlling a voltage for powering the IC, controlling the temperature of the IC, controlling a clock frequency and the set of input test vectors is provided to the IC, controlling a power level of the focused laser beam…”, see claim 48); and an electrical test interface (such as a socket positioned on the stage for making electrical connections to from the IC 100 and the tester. See Col. 9 lines 12-25) to operate the DUT during, or after, the predetermined time (see Col. 9 lines 12-65).
Cole does not explicitly specify the laser source applied heat with the beam a target portion of the DUT so that to permanently alter circuitry blocks of the DUT through one or more thermally enhanced physical aging phenomena.
Florent discloses an analysis device (Fig. 2) for analyzing the operation of electronic components subjected to thermal stresses during a reliability test or aging test (see paragraphs [0004-5]), comprising a laser source (32) applied heat with a laser beam (33) a target portion (20) of a DUT (an electronic chip 12)( the energy of the laser source 30 is adjusted so that the temperature at the surface of the chip 12 is +200 °C. see [0045]) so that to permanently alter circuitry blocks of the DUT through one or more thermally enhanced physical aging phenomena (“methods for analyzing component failures using laser heating that can identify areas of a semiconductor component that have undergone degradation” in [0014]. “During a procedure to analyze the reliability of an electronic component, it is common to subject the component in operation to a thermal stress (this is then called a functional test) in order to accelerate the aging of said integrated circuit (this is then called an aging test)” in [0005].).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the laser source in the IC analysis apparatus of Cole by having the laser source applied heat with the beam a target portion of the DUT so that to permanently alter circuitry blocks of the DUT through one or more thermally enhanced physical aging phenomena, as taught by Florent for purpose of placing the chip under thermal stress in the area of interest by using the laser source which provided high thermal energy +200oC help to accelerate the aging of integrated circuit, saving time in process of evaluation during the reliability test of the electronic chip.
Regarding claim 6, Cole and Florent disclose the IC device testing apparatus of claim 1, Cole further teaches comprising a beam steering system coupled to the controller, the beam steering system to focus a spot of the beam within the target portion of the DUT (Col.3 lines 45-55 and Col. 11 lines 28-50).
Regarding claim 7, Cole discloses the IC device testing apparatus of claim 6, Cole further teaches wherein the spot of the beam has a diameter no more than 2 μm (Col.3 lines 45-55).
Regarding claim 12, Cole discloses the IC device testing apparatus of claim 1, Cole further teaches wherein the electrical test interface comprises: a microprobe card comprising a microprobe array; a host applications board coupled to a power supply to power the IC device; or a probe card electrically coupled to automated test equipment (ATE) (see Col. 7 lines 28-40, Col. 9 lines 13-25, and Fig. 1).
Regarding claim 13, Cole discloses the IC device testing apparatus of claim 1, Cole further teaches wherein the stage comprises a material transparent to the laser beam and the beam is to pass through the stage (see Col. 10 lines 5-20).
Regarding claim 14, Cole discloses a method of testing an integrated circuit (IC) device (an IC analysis apparatus 10 in Fig. 1), the method comprising: selectively heating a target portion of an IC device under test (DUT)(100) by exposing the target portion to a laser beam (“The laser beam 20 is focused to a spot on the IC 100 to locally heat particular circuit elements in the IC at any instant in time. This can be done, for example, by focusing the laser beam to a micron-sized spot after the laser beam is transmitted-through the substrate…”, see Col. 3 lines 47-55) for a predetermined time (see Col. 9 lines 25-40 and Col. 9 line 65- to Col. 10 line 5); and operating the DUT (100) during, or after, the predetermined time (see Col. 9 lines 12-65).
Cole does not explicitly specify the laser source applied heat with the beam a target portion of the DUT so that to permanently alter circuitry blocks of the DUT through one or more thermally enhanced physical aging phenomena.
Florent discloses an analysis device (Fig. 2) for analyzing the operation of electronic components subjected to thermal stresses during a reliability test or aging test (see paragraphs [0004-5]), comprising a laser source (32) applied heat with a laser beam (33) a target portion (20) of a DUT (an electronic chip 12)( the energy of the laser source 30 is adjusted so that the temperature at the surface of the chip 12 is +200 °C. see [0045]) so that to permanently alter circuitry blocks of the DUT through one or more thermally enhanced physical aging phenomena (“methods for analyzing component failures using laser heating that can identify areas of a semiconductor component that have undergone degradation” in [0014]. “During a procedure to analyze the reliability of an electronic component, it is common to subject the component in operation to a thermal stress (this is then called a functional test) in order to accelerate the aging of said integrated circuit (this is then called an aging test)” in [0005].).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the laser source in the IC analysis apparatus of Cole by having the laser source applied heat with the beam a target portion of the DUT so that to permanently alter circuitry blocks of the DUT through one or more thermally enhanced physical aging phenomena, as taught by Florent for purpose of placing the chip under thermal stress in the area of interest by using the laser source which provided high thermal energy +200oC help to accelerate the aging of integrated circuit, saving time in process of evaluation during the reliability test of the electronic chip.
Regarding claim 15, Cole and Florent disclose the method of claim 14, Cole further teaches wherein the DUT comprises a substrate material and exposing the target portion to the laser beam further comprises passing the beam through a thickness of the substrate (Col. 3 lines 45-55 and Col. 8 lines 65 to Col. 8 line 25).
Regarding claim 19, Cole and Florent disclose the method of claim 14, Cole further teaches comprises globally heating the entire DUT with a second heat source while concurrently selectively heating the target portion of the DUT with the laser beam (see at least in Col. 9 lines 25-40).
6. Claims 2-5 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Cole in view of Florent and further in view of Myung et al. (US. Pub. 20210/370439; hereinafter “Myung”).
Regarding claim 2, Cole and Florent disclose the IC device testing apparatus of claim 1, except for explicitly specifying wherein the laser source has an average output power rating of at least 1 W.
Myung discloses, in Figs. 1-2, a laser source 20 provides a plurality of semiconductor chips 14 with a laser beam 22 whose radiation heat is used to heat up the semiconductor chips 14, the laser beam 22 outputs power rating of at least 1 W (see [0023]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the laser source of Cole and Florent for outputting power rating of at least 1W as taught by Cole, for purpose of meeting the system design and specification requirement.
Regarding claim 3, Cole and Florent and Myung disclose the device testing apparatus of claim 2, Cole further teaches wherein: the DUT is to comprise a semiconductor material having a bandgap; and the laser source has an output energy less than the bandgap (see Col. 4 lines 10-25).
Regarding claim 4, Cole and Florent and Myung disclose the IC device testing apparatus of claim 2, Cole further teaches wherein the laser source has continuous wave output with a center wavelength of 1200 nm-1800 nm (see Col. 3 lines 45-55).
Regarding claim 5, Cole and Florent and Myung disclose the IC device testing apparatus of claim 4, Florent further teaches wherein the output center wavelength is 1550 nm (see [0051-52]).
Regarding claim 16, Cole and Florent disclose the method of claim 14, wherein selectively heating the target portion of the DUT further comprises generating the laser beam with a continuous wave laser source having an output center wavelength of 1200 nm-1800 nm (see Col. 3 lines 45-55), except for explicitly specifying that the laser beam with a continuous wave laser source having an output power rating of at least 1 W. Myung discloses, in Figs. 1-2, a laser source 20 provides a plurality of semiconductor chips 14 with a laser beam 22 whose radiation heat is used to heat up the semiconductor chips 14, the laser beam 22 outputs power rating of at least 1 W (see [0023]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the laser source of Cole and Florent for outputting power rating of at least 1W as taught by Cole, for purpose of meeting the system design and specification requirement.
7. Claims 8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Cole in view of Singh et al. (US. Pub. 2014/0375794; hereinafter “Singh”).
Regarding claim 8, Cole and Florent disclose the IC device testing apparatus of claim 6, wherein the beam steering system comprises a galvanometer (24 in Fig. 1), except for explicitly specifying further comprising an optical encoder.
Singh discloses a laser-marking system 700 comprises a galvanometer (712, 714) further comprising an optical encoder (732, 734). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the IC analysis apparatus of Cole and Florent by having the galvanometer further comprising an optical encoder as taught by Singh for purpose of providing the system couples galvanometers to respective positional-feedback encoder i.e. absolute optical rotary encoder, to enable the system to steer the laser beam with increased precision. The system allows a controller to receive a control signal and to controllably position an arm and an end effector assembly to controllably position a tool into increased alignment with the location.
Regarding claim 17, Cole and Florent disclose the method of claim 14, wherein exposing the target portion to the laser beam further comprises steering the beam with a galvanometer (24 in Fig. 1), except for explicitly specifying comprising an optical encoder.
Singh discloses a laser-marking system 700 comprises a galvanometer (712, 714) further comprising an optical encoder (732, 734). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the IC analysis apparatus of Cole and Florent by having the galvanometer further comprising an optical encoder as taught by Singh for purpose of providing the system couples galvanometers to respective positional-feedback encoder i.e. absolute optical rotary encoder, to enable the system to steer the laser beam with increased precision. The system allows a controller to receive a control signal and to controllably position an arm and an end effector assembly to controllably position a tool into increased alignment with the location.
8. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Cole in view of Florent and further in view of Ryu et al. (US. Pub. 2016/0049381; hereinafter “Ryu”).
Regarding claim 9, Cole and Florent disclose the IC device testing apparatus of claim 1, except for explicitly specifying wherein the target portion is to reach a maximum temperature that is at least 150° C. greater than a second portion of the DUT not irradiated by the beam. Ruy discloses a laser beam heats a target portion of a semiconductor device or a circuit board is to reach a maximum temperature that is at least 150° C. greater than an area of the semiconductor device or the circuit board not irradiated by the laser beam (see [0013, 23, 53] and claims 16-17).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adjust the power of the laser beam of Cole and Florent so that the target portion is to reach a maximum temperature that is at least 150° C. greater than a second portion of the DUT not irradiated by the beam as taught by Ryu for purpose of enabling transferring heat energy derived from the laser beam only to a local region of the circuit board corresponding to the semiconductor die such that thermal expansion and/or shrinkage occurring to an entire region of the circuit board can be minimized, thus improving reliability in electrical connection between the semiconductor die and the circuit board. The method enables minimizing a bonding space using a laser emission system for locally emitting laser beams, thus improving space utilization efficiency.
9. Claims 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Cole in view of Florent.
Regarding claim 11, Cole and Florent disclose the IC device testing apparatus of claim 1, except for explicitly specifying that wherein the predetermined time is at least 12 hours. However, Florent discloses, in order to accelerate the aging of the IC chip for analyzing the reliability of the IC chip (DUT), a laser beam being used to heat up the DUT for a period of time during the thermal stress test. The total predetermined time to heat up the DUT in the reliability test would simply be a matter of inventor design choice. It depends on how the inventor want to apply the stress test level of the reliability test to the DUT. The higher energy of a laser beam applied to the DUT may have less the predetermined time than the lower energy of a laser beam applied to the same DUT. The chip is used for commercial sector that may have less the predetermined time for burn-in than the same chip is used for industrial sector.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ an IC analysis system of Cole and Florent by setting the predetermined heating time for at least 12 hours, in order to meet the system design and specification requirement.
Regarding claim 18, Cole and Florent disclose the method of claim 14, except for explicitly specifying wherein the predetermined time exceeds 12 hours.
However, Florent discloses, in order to accelerate the aging of the IC chip for analyzing the reliability of the IC chip (DUT), a laser beam being used to heat up the DUT for a period of time during the thermal stress test. The total predetermined time to heat up the DUT in the reliability test would simply be a matter of inventor design choice. It depends on how the stress test level of the reliability test would be applied to the DUT. The higher energy of a laser beam applied to the DUT may have less the predetermined time than the lower energy of a laser beam applied to the same DUT. The chip is used for commercial sector that may have less the predetermined time for burn-in than the same chip is used for industrial sector.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ an IC analysis system of Cole and Florent by setting the predetermined heating time for at least 12 hours, in order to meet the system design and specification requirement.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ an IC analysis system of Cole and Florent by setting the predetermined heating time for at least 12 hours, in order to meet the system design and specification requirement.
Allowable Subject Matter
10. Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
11. Claims 20-22 are allowed over the prior arts of record.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 20, the cited references, alone or in combination, do not disclose nor fairly suggest:
“ … selectively heating a first of the plurality of functional circuit blocks without heating a second of the functional circuit blocks by exposing the first of the functional circuit blocks to a
laser beam for a predetermined time sufficient to permanently alter circuitry blocks of the
DUT through one or more thermally enhanced physical aging phenomena; and
determining an amount of frequency degradation between a ring oscillator, phase locked loop, or
memory array in the first of the functional circuit blocks and a ring oscillator, phase
locked loop, or memory array in the second of the functional circuit blocks by operating
the plurality of functional circuit blocks during, or after, the predetermined time.” as claimed in claim 20.
As to claim(s) 21-22, the claims are allowed as they further limit allowed claim 20.
Conclusion
12. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANG LE whose telephone number is (571)272-9349. The examiner can normally be reached on Monday thru Friday 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached on (571) 272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THANG X LE/Primary Examiner, Art Unit 2858
1/24/2026