Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
The previous informalities: Claim 1, the limitation “the inner oxide layer” is corrected to “the inner oxide spacer”. Claim 1 objection is withdrawn.
The previous informalities: Claim 8, the limitation “the inner oxide layer” is corrected to “the inner oxide spacer”. Claim 8 objection is withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 8 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Press et al (US 2008/0299733), hereinafter Press, in view of Thei ( US 2007/0045754 ), hereinafter Thei.
Regarding claim 1, Press (Figs. 2a-2d) discloses a semiconductor structure, comprising: a first sidewall spacer on sidewalls of a first device structure (left transistor) on a surface of a substrate 301, the first sidewall spacer comprising: a first inner liner layer 380 on sidewalls of the first device structure; a first oxide spacer 318 (i.e., silicon oxide or silicon nitride, [0055], corresponding to material of layer 370 after etching, see Figs. 2b-2c) on the first inner liner layer 380 and on the surface of the substrate; and a first outer liner layer 381 on the first oxide spacer 318; and a second sidewall spacer on sidewalls of a second device structure (right transistor) on the surface of the substrate 301, the second sidewall spacer comprising: a second inner liner layer 380 on sidewalls of the second device structure; an inner oxide spacer 418 (i.e., silicon oxide or silicon nitride, [0055], corresponding to material of layer 370 after etching, see Figs. 2b-2c and [0064]) on the second inner liner layer 380 and on the surface of the substrate 301, the inner oxide spacer 418 vertically extending on the second inner liner layer 380; a second outer liner layer 381 on the inner oxide spacer 418, the second outer liner layer 381 vertically extending on the inner oxide spacer 418; and an outer oxide spacer 483 (i.e., silicon oxide or silicon nitride, [0055], corresponding to material of layer 370 or layer 382 after etching, see Figs. 2b-2c and [0068]) on the second outer liner layer 381, wherein the first inner liner layer 380 and the second inner liner layer 381 comprise silicon- containing nitride material (i.e., silicon nitride which opposites with oxide material of oxide spacers, see [0055] and [0068]), and the first oxide spacer 318, the inner oxide spacer 418, and the outer oxide spacer 483 comprise silicon-containing oxide material (as discussed above), and the first outer liner layer 381 is thinner than the first oxide spacer 318, and the second outer liner layer 381 is thinner than the inner oxide spacer 418, and the second outer liner layer 381 is also thinner than the outer oxide spacer 483.
Press fails to disclose:
the inner oxide spacer … reaching the surface of the substrate, the inner oxide spacer including a bottom portion thereof horizontally extending on the surface of the substrate;
the second outer liner layer … reaching the bottom portion of the inner oxide spacer, the second outer liner layer including a bottom portion thereof horizontally extending on the bottom portion of the inner oxide spacer;
However, Thei teaches:
the inner oxide spacer ( Thei, FIG. 6, 108a; [0016], a recessed L-shaped spacer 108a ) … reaching the surface of the substrate ( Thei, FIG. 6, 100; [0013], semiconductor substrate 100 ), the inner oxide spacer ( Thei, FIG. 6, 108a ) including a bottom portion ( Thei, FIG. 6, horizontal portion H; [0016], a horizontal portion H ) thereof horizontally extending on the surface of the substrate ( Thei, FIG. 6, 100 );
the second outer liner layer … reaching the bottom portion of the inner oxide spacer ( Thei, FIG. 6, 108a; [0016], a recessed L-shaped spacer 108a ), the second outer liner layer including a bottom portion thereof horizontally extending on the bottom portion ( Thei, FIG. 6, horizontal portion H; [0016], a horizontal portion H ) of the inner oxide spacer ( Thei, FIG. 6, 108a; [0016], a recessed L-shaped spacer 108a );
Press and Thei are both considered to be analogous to the claimed invention because they are forming the side wall spacer structure for transistors. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Press ( inner oxide spacer 418 vertically extending on the second inner liner layer 380 ), to incorporate the teachings of Thei ( FIG. 6, 108a; [0016], a recessed L-shaped spacer 108a ), to replace Press “ inner oxide spacer 418 and bottom portion of 380 ” by Thei “ L-shaped spacer 108a ”, to implement “ the inner oxide spacer including a bottom portion ( Thei, FIG. 6, horizontal portion H; [0016], a horizontal portion H ) thereof horizontally extending on the surface of the substrate ( Thei, FIG. 6, 100 ); and the second outer liner layer ( Press, 381 ) including a bottom portion thereof horizontally extending on the bottom portion ( Thei, FIG. 6, horizontal portion H; [0016], a horizontal portion H ) of the inner oxide spacer ( Thei, FIG. 6, 108a; [0016], a recessed L-shaped spacer 108a ); ”. Doing so would provide that the spacer widths can be better controlled, and the resistance uniformity between adjacent gates can be improved.
Regarding claim 8, Press (Figs. 2a-2d) discloses a semiconductor structure, comprising: a first device structure (left transistor) on a surface of a substrate 301; a second device structure (right transistor) on the surface of the substrate 301; a first sidewall spacer on sidewalls of the first device structure, the first sidewall spacer comprising: a first inner liner layer 380 on sidewalls of the first device structure; a first oxide spacer 318 (i.e., silicon oxide or silicon nitride, [0055], corresponding to material of layer 370 after etching, see Figs. 2b-2c) on the first inner liner layer 380 and on the surface of the substrate; and a first outer liner layer 381 on the first oxide spacer 318; and a second sidewall spacer on sidewalls of the second device structure, the second sidewall spacer comprising: a second inner liner layer 380 on sidewalls of the second device structure; an inner oxide spacer 418 (i.e., silicon oxide or silicon nitride, [0055], corresponding to material of layer 370 after etching, see Figs. 2b-2c and [0064]) on the second inner liner layer 380 and on the surface of the substrate 301, the inner oxide spacer 418 vertically extending on the second inner liner layer 380; a second outer liner layer 381 on the inner oxide spacer 418, the second outer liner layer 381 vertically extending on the inner oxide spacer 418; and an outer oxide spacer 483 (i.e., silicon oxide or silicon nitride, [0055], corresponding to material of layer 370 or layer 382 after etching, see Figs. 2b-2c and [0068]) on the second outer liner layer 381, wherein the first inner liner layer 380 and the second inner liner layer 380 comprise silicon- containing nitride material (i.e., silicon nitride which opposites with oxide material of oxide spacers, see [0055] and [0068]), and the first oxide spacer 318, the inner oxide spacer 418, and the outer oxide spacer 483 comprise silicon-containing oxide material (as discussed above), and the first outer liner layer 381 is thinner than the first oxide spacer 318, and the second outer liner layer 381 is thinner than the inner oxide spacer 418, and the second outer liner layer 381 is also thinner than the outer oxide spacer 483.
Press fails to disclose:
the inner oxide spacer … reaching the surface of the substrate, the inner oxide spacer including a bottom portion thereof horizontally extending on the surface of the substrate;
the second outer liner layer … reaching the bottom portion of the inner oxide spacer, the second outer liner layer including a bottom portion thereof horizontally extending on the bottom portion of the inner oxide spacer;
However, Thei teaches:
the inner oxide spacer ( Thei, FIG. 6, 108a; [0016], a recessed L-shaped spacer 108a ) … reaching the surface of the substrate ( Thei, FIG. 6, 100; [0013], semiconductor substrate 100 ), the inner oxide spacer ( Thei, FIG. 6, 108a ) including a bottom portion ( Thei, FIG. 6, horizontal portion H; [0016], a horizontal portion H ) thereof horizontally extending on the surface of the substrate ( Thei, FIG. 6, 100 ) ;
the second outer liner layer … reaching the bottom portion of the inner oxide spacer ( Thei, FIG. 6, 108a; [0016], a recessed L-shaped spacer 108a ), the second outer liner layer including a bottom portion thereof horizontally extending on the bottom portion ( Thei, FIG. 6, horizontal portion H; [0016], a horizontal portion H ) of the inner oxide spacer ( Thei, FIG. 6, 108a; [0016], a recessed L-shaped spacer 108a );
Press and Thei are both considered to be analogous to the claimed invention because they are forming the side wall spacer structure for transistors. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Press ( inner oxide spacer 418 vertically extending on the second inner liner layer 380 ), to incorporate the teachings of Thei ( FIG. 6, 108a; [0016], a recessed L-shaped spacer 108a ), to replace Press “ inner oxide spacer 418 and bottom portion of 380 ” by Thei “ L-shaped spacer 108a ”, to implement “ the inner oxide spacer including a bottom portion ( Thei, FIG. 6, horizontal portion H; [0016], a horizontal portion H ) thereof horizontally extending on the surface of the substrate ( Thei, FIG. 6, 100 ); and the second outer liner layer ( Press, 381 ) including a bottom portion thereof horizontally extending on the bottom portion ( Thei, FIG. 6, horizontal portion H; [0016], a horizontal portion H ) of the inner oxide spacer ( Thei, FIG. 6, 108a; [0016], a recessed L-shaped spacer 108a ); ”. Doing so would provide that the spacer widths can be better controlled, and the resistance uniformity between adjacent gates can be improved.
Regarding claims 2 and 12, Press (Figs. 2a-2d) further discloses the first outer liner layer 381 and the second outer liner layer 381 comprise silicon-containing nitride material (i.e., silicon nitride which opposites with oxide material of oxide spacers, see [0055] and [0068]).
Claims 4-7, 9-11, 14 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Press, in view of Thei, further in view of Iwata et al (US2019/0296012).
Regarding claims 5-7 and 21, Press and Thei do not disclose: the first oxide spacer, the inner oxide spacer, the outer oxide spacer, the first inner liner layer, the second inner liner layer, the first outer liner layer, and the second outer liner layer each have a thickness in a range as claimed.
However, Iwata (Fig. 12) teaches a semiconductor structure, comprising: a first device structure 101 on a surface of a substrate (10, 12); a second device structure 102 on the surface of the substrate 10; a first sidewall spacer on sidewalls of the first device structure 101, and a second sidewall spacer on sidewalls of the second device structure 102. Iwata further teaches: the first oxide spacer 761 has a thickness of between 6 nm and 8 nm ([0055]), the inner oxide spacer 761 has a thickness of between 6 nm and 8 nm ([0055]), and the outer oxide spacer 763 has a thickness of between 8 nm and 10 nm ([0059]); the first inner liner layer 756 and the second inner liner layer 756 each have a thickness of between 5 nm and 8 nm ([0054]); and the first outer liner layer 762 and the second outer liner 762 layer each have a thickness of between 1 nm and 5 nm ([0056]). Furthermore, the thickness range would have been obvious to an ordinary artisan practicing the invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 233, 235 (CCPA 1955).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the first oxide spacer, the inner oxide spacer, the outer oxide spacer, the first inner liner layer, the second inner liner layer, the first outer liner layer, and the second outer liner layer each have a thickness in a range as claimed, because such thicknesses could be optimized during routine experimentation depending upon the desired dielectric materials of the liner layers and the spacers, and the properties of the etch processes that are used for etching the liner layers and the spacers. It appears that these changes produce no functional differences of the first and second sidewalls as the diffusion barrier layers and therefore would have been obvious.
Regarding claims 4 and 14, Iwata (Fig. 12) further teaches: the thickness of the first sidewall spacers including: the thicknesses of the first inner liner layer 756 (i.e., 5 - 50 nm, [0054]), the first oxide spacer 761 (i.e., 1 - 10 nm, [0055]) and the first outer liner layer 762 (i.e., 2-20 nm, [0056]), and the sum of these thicknesses is within a claimed thickness range of the first oxide spacer. Iwata also teaches the thickness of the second sidewall spacers including: the thicknesses of the second inner liner layer 756 (i.e., 5 - 50 nm, [0054]), the inner oxide spacer 761 (i.e., 1 - 10 nm, [0055]), the second outer liner layer 762 (i.e., 2-20 nm, [0056]) and the outer oxide spacer 763 (i.e., 10 – 70 nm, [0059]), and the sum of these thicknesses is within a claimed thickness range of the second oxide spacer.
Regarding claims 9-10, Press (Fig. 2d) further discloses the first device structure and the second device structure each comprise a gate dielectric 305/405 on the surface of the substrate, a gate layer 306/406 on the gate dielectric 305/405.
Press does not disclose: a metal layer on the gate layer and a cap layer on the metal layer (claim 9); the gate dielectric, the gate layer, the metal layer and the cap layer each having a material as claimed (claim 10).
However, Iwata (Fig. 12) further teaches: the first device structure 101 and the second device structure 102 each comprise a gate dielectric 750 on the surface of the substrate, a gate layer 752 on the gate dielectric, a metal layer 754 ([0051]) on the gate layer, and a cap layer 758 on the metal layer; the gate dielectric 750 comprises a dielectric material having a dielectric constant greater than that of silicon dioxide (i.e., dielectric metal oxide, [0050]), the gate layer 752 comprises conductively-doped silicon-containing material ([0050]), the metal layer 754 comprises tungsten ([0050]), and the cap layer 758 comprises silicon nitride ([0050]). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first and second devices of Press with the gate structures having materials as set forth above because such gate structures are well known for improving the threshold voltages and reducing the leakage currents of the transistors.
Regarding claim 11, Press (Fig. 2d) discloses the substrate comprises doped regions 416 (i.e., extended source/drain, [0054]) outside of the second inner liner layer, but does not disclose the doped regions are lightly doped.
However, Iwata (Fig. 12) further teaches the substrate comprises lightly-doped regions 731 ([0052]) outside of the second inner liner layer 756 (also see Fig. 1). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the doped regions 416 (i.e., extended source/drain) of Press with lightly doping because as is well known, such lightly doped regions would reduce the electric fields in the channel region of the transistor device.
Response to Arguments
Applicant’s arguments with respect to independent claim(s) 1 and 8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Specifically, applicant's remarks regarding Claim 1 ( Currently Amended ): page 9, line 1, cited “ The Examiner compares Press's items 301, 380, 418, 381, and 483 with the substrate, the second inner liner layer, the inner oxide spacer, the second outer liner layer, and the outer oxide spacer of the Applicant's claimed semiconductor structure, respectively. However, arguendo, applying the Examiner's interpretation and comparison, while the inner oxide spacer as currently amended vertically extends on the second inner liner layer and reaches the surface of the substrate (see FIG. 2B of Applicant's application, for example), Press's item 418 does not reach the surface of item 301. Also, the inner oxide spacer as currently amended includes a bottom portion thereof horizontally extending on the surface of the substrate. In contrast, Press's item 418 does not include such a bottom portion.
Furthermore, since Press 's item 418 does not include a bottom portion that extends horizontally on the surface of the substrate, Press's item 381 does not have a structure equivalent to the structure of the second outer liner layer as currently amended that vertically extends on the inner oxide spacer and reaches the bottom portion of the inner oxide spacer. The second outer liner layer includes a bottom portion thereof horizontally extending on the surface of the bottom portion of the inner oxide spacer, which Press' item 381 does not have. ”.
Examiner’s response: Please refer to the Claim Rejections - 35 USC § 103 for claim 1 (Currently Amended) in this office action, cited “
Press fails to disclose:
the inner oxide spacer … reaching the surface of the substrate, the inner oxide spacer including a bottom portion thereof horizontally extending on the surface of the substrate;
the second outer liner layer … reaching the bottom portion of the inner oxide spacer, the second outer liner layer including a bottom portion thereof horizontally extending on the bottom portion of the inner oxide spacer;
However, Thei teaches:
the inner oxide spacer ( Thei, FIG. 6, 108a; [0016], a recessed L-shaped spacer 108a ) … reaching the surface of the substrate ( Thei, FIG. 6, 100; [0013], semiconductor substrate 100 ), the inner oxide spacer ( Thei, FIG. 6, 108a ) including a bottom portion ( Thei, FIG. 6, horizontal portion H; [0016], a horizontal portion H ) thereof horizontally extending on the surface of the substrate ( Thei, FIG. 6, 100 ) ;
the second outer liner layer … reaching the bottom portion of the inner oxide spacer ( Thei, FIG. 6, 108a; [0016], a recessed L-shaped spacer 108a ), the second outer liner layer including a bottom portion thereof horizontally extending on the bottom portion ( Thei, FIG. 6, horizontal portion H; [0016], a horizontal portion H ) of the inner oxide spacer ( Thei, FIG. 6, 108a; [0016], a recessed L-shaped spacer 108a );
Press and Thei are both considered to be analogous to the claimed invention because they are forming the side wall spacer structure for transistors. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Press ( inner oxide spacer 418 vertically extending on the second inner liner layer 380 ), to incorporate the teachings of Thei ( FIG. 6, 108a; [0016], a recessed L-shaped spacer 108a ), to replace Press “ inner oxide spacer 418 and bottom portion of 380 ” by Thei “ L-shaped spacer 108a ”, to implement “ the inner oxide spacer including a bottom portion ( Thei, FIG. 6, horizontal portion H; [0016], a horizontal portion H ) thereof horizontally extending on the surface of the substrate ( Thei, FIG. 6, 100 ); and the second outer liner layer ( Press, 381 ) including a bottom portion thereof horizontally extending on the bottom portion ( Thei, FIG. 6, horizontal portion H; [0016], a horizontal portion H ) of the inner oxide spacer ( Thei, FIG. 6, 108a; [0016], a recessed L-shaped spacer 108a ); ”. Doing so would provide that the spacer widths can be better controlled, and the resistance uniformity between adjacent gates can be improved. ”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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