DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on November 10, 2025 has been entered. Claim(s) 13-16 has/have been canceled and claim(s) 25-32 has/have been added. Therefore, claim(s) 1, 3-12 and 25-32 are pending in the application.
Claim Objections
Claim(s) 25-28 is/are objected to because of the following informalities.
With respect to claim 25, as currently presented the claim recites “wherein the line-space duty cycle is calculated the average of width of the interconnect lines divided by an average of the line pitches”. An “as” appears to be missing before “the average” and “the average” should read “an average”. Claims 26-28, which either directly or indirectly depend from claim 25 and which inherit issues of claim 25 are objected to for similar reasons.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 3, 28 and 31-32 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claim 3, as currently amended the claim recites “adjacent ones of those interconnect line”, in line 2. It is unclear to which line of the interconnect lines recited in claim 1, “those interconnect lines” are referring to. Moreover, as currently amended the claim recites that “the sum of width of the interconnect lines divided by the sum of the width plus a sum of space between the interconnect lines is not more than 0.5%. It is unclear if this limitation, is attempting to further narrow the line-space duty cycle recited in claim 1, or define a new parameter. Review of the specification, and in particular paragraph [0033] of the specification as published, seems to suggest that a sum of width of the interconnect lines divided by a sum of line pitches and the sum of width of the interconnect line divided by the sum of the width plus a sum of spaces between the interconnect line” are both referring to a line-space duty cycle. For purpose of compact prosecution, it will be assumed that “those interconnect lines” are referring to immediately adjacent interconnect lines and that the line-space duty cycles is further limited to not more than 0.5%. Claims 31-32 which either directly or indirectly depend from claim 3 and which inherit issues of claim 3 are rejected for similar reasons.
With respect to claim 28, as currently presented the claim recites “adjacent ones of those interconnect line”, in line 2. It is unclear to which line of the interconnect lines recited in claim 1, “those interconnect lines” are referring to. Moreover, as currently amended the claim recites that “the sum of width of the interconnect lines divided by the sum of the width plus a sum of space between the interconnect lines is not more than 0.5%. It is unclear if this limitation, is attempting to further narrow the line-space duty cycle recited in claim 1, or define a new parameter. Review of the specification, and in particular paragraph [0033] of the specification as published, seems to suggest that a sum of width of the interconnect lines divided by a sum of line pitches and the sum of width of the interconnect line divided by the sum of the width plus a sum of spaces between the interconnect line” are both referring to a line-space duty cycle. For purpose of compact prosecution, it will be assumed that “those interconnect lines” are referring to immediately adjacent interconnect lines and that the line-space duty cycles is further limited to not more than 0.5%.
Claim Rejections - 35 USC § 102/103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 7 and 10-11 is/are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Choi et al. (US 2017/0365504, hereinafter “Choi”, previously cited).
Regarding claim 1, Choi teaches in Fig. 1-7 (Fig. 7 shown below) and related text, an integrated circuit (IC) die (200, Fig. 7 and ¶[0026]), comprising:
a plurality of transistors (¶[0014]); and
an interconnect layer (e.g. 112, Fig. 7 and ¶[0015]) above the transistors (Fig. 1), the interconnect layer comprising one or more dielectric materials (e.g. 122, 124, Fig. 1 and ¶[0015]) and interconnect lines (e.g. 140, 142, Figs. 1, 7 and ¶[0016]) embedded therein (Fig. 1), wherein, all of the interconnect lines with one or more line pitches of not more than 75 nm (i.e. Choi teaches that P is less than approximately 25 nm, Fig. 7 and ¶[0017]) also have a line-space duty cycle of not more than 1%, and wherein the line-space duty cycle is calculated as a sum of widths of the interconnect lines divided by a sum of the line pitches (i.e. Choi teaches that pitch P is less than approximately 25 nm (Fig. 7 and ¶[0017]) and the line width W is less than approximately 10 nm, (Fig. 7 and ¶[0017]), which for the line widths of less than 0.25 nm (covered by Choi’s range), would result in the line-space duty cycle of not more than 1%. It is noted that there is no allegation of criticality or any evidence demonstrating any difference across the broader range. In fact, applicant’s own disclosure of the broader range (similar to that of Choi), clearly demonstrates that the different portions of the broader range would not work differently (see ClearValue Inc. v. Pearl River Polymers Inc., 668 F.3d 1340, 101 USPQ2d 1773 (Fed. Cir. 2012)). Alternatively, assuming Choi does not disclose a line-space duty cycle of not more than 1%, modifying ranges of the interconnect line widths and pitches disclosed by Choi so that the line-space duty cycle is not more than 1% would have been within capabilities of an ordinary skill in the art, as it would amount to nothing other than selecting, for example, interconnect line widths from the lower end of the Choi’s interconnect line widths range, in order to meet specific design requirements.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select, for example, interconnect line widths from the lower end of the Choi’s interconnect line widths range, in order to meet specific design requirements.
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Regarding claim 3 (2), Choi teaches wherein for a plurality of adjacent pitches between immediately adjacent ones of those interconnect lines, the sum of the width of the interconnect lines divided by the sum of the widths plus a sum of spaces between the interconnect lines is not more than 0.5 % (i.e. for line width of less than 0.08 nm (covered by Choi’s range) and line spacing of less than approximately 15 nm, the line-space duty cycle, calculated by dividing the sum of the width of the interconnect lines by the sum of the width plus a sum of spaces between the interconnect lines disclosed by Choi would not be more than 0.5%).
Regarding claim 7 (1), Choi teaches wherein the interconnect lines comprise at least one of ruthenium or tungsten (¶[0016]).
Regarding claim 10 (1), Choi teaches wherein one or more of the interconnect lines is on an interface layer (172, Figs. 1, 5 and ¶¶[0016]-[0024]) above a dielectric layer (122, Fig. 1 and ¶[0015]).
Regarding claim 11 (10), Choi teaches wherein the interface layer comprises titanium or tantalum (¶[0016]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi as applied to claim 1 above, and further in view of Lin et al. (US 2020/0286685, hereinafter “Lin `685”, previously cited).
Regarding claim 4 (1), teaching of Choi was discussed above in the rejection of claim 1 and includes wherein the interconnect lines comprise aluminum or copper, within a refractory metal liner such as titanium or titanium nitride for aluminum, or tantalum or tantalum nitride for copper, cobalt (Co), ruthenium (Ru), manganese (Mn), tungsten (W), iridium (Ir), rhodium (Rh) and platinum (Pt) (¶[0016]). While Choi does not explicitly teach that the interconnect lines comprise graphene, Lin, in a similar field of endeavor teaches that the interconnect materials and graphene are art recognized equivalent interconnect materials (¶[0045]). Therefore, because these materials were art-recognized equivalents before the effective filing date of the claimed invention, one of ordinary skill in the art would have found it obvious to substitute graphene for the interconnect materials disclosed by Choi.
Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi as applied to claim 1 above, and further in view of Lee et al. (US 2022/0139880, hereinafter “Lee `880”, previously cited).
Regarding claim 5 (1), teaching of Choi was discussed above in the rejection of claim 1 and includes wherein the interconnect lines include metal (e.g. copper, ¶[0016]). While Choi does not explicitly teach that the interconnect lines comprise at least one of sulfur, selenium, or tellurium in addition to the metal, including, for example tellurium, along with copper in the interconnect lines disclosed by Choi would be obvious to one of ordinary skill in the art as doing so would amount to nothing other than using equivalent known materials for their intended purpose as evidenced by Lee `880 (¶[0026]). Namely, Lee `880 in a similar field of endeavor teaches that interconnect lines, such as those disclosed by Choi can be made of aluminum (Al), gold (Au), cobalt (Co), copper (Cu), nickel (Ni), lead (Pb), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), or a combination thereof (¶[0026]).
Accordingly, using copper and tellurium, instead of copper, as material of the interconnect lines would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention as doing so would amount to nothing more than using a known interconnect material for its intended purpose as such materials were art recognized equivalents.
Regarding claim 6 (5), the combined teaching of Choi and Lee `880 discloses wherein the metal comprises copper (Choi, ¶[0016]).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi as applied to claim 1 above, and further in view of et Lee et al. (US 2023/0011088, hereinafter “Lee`088”, previously cited).
Regarding claim 8 (1), teaching of Choi was discussed above in the rejection of claim 1. Choi, however, does not explicitly teach that a first of the interconnect lines has a bottom width proximal the transistors greater than a top width distal from the transistors.
Lee `088, in a similar field of endeavor teaches that the interconnect lines (210, Fig. 2 and ¶[0026]) similar to those disclosed by Choi, can have a bottom width (A1, Fig. 2 and ¶[0032]) proximal transistors (i.e. substrate 101, Fig. 2 includes transistors, ¶[0027]) greater than a top width (A2, Fig. 2 and ¶[0032]) distal from the transistors in order to meet specific design requirements for the device.
Accordingly, since the prior art teaches all of the claimed elements , using such elements would lead to predictable results, and as such it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the invention pertains to use the interconnect lines that have a bottom width proximal the transistors greater than a top width distal from the transistors as disclosed by Lee `088 in the IC die disclosed by Choi in order to meet specific design requirement for the IC die.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi as applied to claim 1 above, and further in view of et Kabir et al. (US 2023/0230919, hereinafter “Kabir”, previously cited).
Regarding claim 9 (1), teaching of Choi was discussed above in the rejection of claim 1. Choi, however, does not explicitly teach wherein an adjacent pair of the interconnect lines have inner sidewall heights greater than outer sidewall heights.
Kabir, in a similar field of endeavor, teaches in Fig. 1B and related text, that interconnect lines, similar to those disclosed by Choi, can includes adjacent pair of the interconnect lines (e.g. four interconnect lines on the left side of Fig. 1B and ¶¶[0034] and [0037]) that have inner sidewall heights greater than outer sidewall heights in order to meet specific manufacturing requirements when forming the IC die.
Accordingly, since the prior art teaches all of the claimed elements, using such elements would lead to predictable results, and as such, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the invention pertains to form the interconnect lines disclosed by Choi using the technique disclosed by Kabir, such that the adjacent pair of the interconnect lines have inner sidewall heights greater than the outer sidewall heights, in order to meet specific manufacturing requirements.
Claim(s) 12 and 29-32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi as applied to claims 1 and 3 above, and further in view of et Yee et al. (US 2022/0375869, hereinafter “Yee”, previously cited).
Regarding claim 12 (1), teaching of Choi was discussed above in the rejection of claim 1. Choi, however, does not explicitly teach that the IC die further comprises a cooling structure operable to remove heat from the IC die to achieve an operating temperature at or below -25°C. Nonetheless, using a cooling structure with the IC die disclosed by Choi in order to remove heat from the IC die to achieve an operating temperature at or below -25°C would have with the capabilities of one of ordinary skill in the art as evidenced by Yee. Namely, Yee in the similar field of endeavor teaches that in order to cool devices within a substrate, cooling structures, such as, cold plates or a heat pipe configured to use liquid nitrogen or some other liquefied gas (132, 134, Fig. 1 and ¶¶[0014] and [0027]) might be placed on top and/or bottom of the devices (Fig. 1), in order for the device to operate below -25°C (i.e. 10K=-263ºC and 77K=-196ºC, ¶¶[0014] and [0027]).
Accordingly, since the prior art teaches all of the claimed elements, using such elements would lead to predictable results, and as such it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the invention pertains to use the cooling structure disclosed by Yee in the IC die disclosed by Choi in order to remove heat from the IC die and operate the IC die at a desired temperature.
Regarding claim 29 (1), teaching of Choi was discussed above in the rejection of claim 1. Choi, however, does not explicitly teach that the IC die further comprises a cooling structure operable to remove heat from the IC die to achieve an operating temperature at or below -50°C. Nonetheless, using a cooling structure with the IC die disclosed by Choi in order to remove heat from the IC die to achieve an operating temperature at or below -50°C would have with the capabilities of one of ordinary skill in the art as evidenced by Yee. Namely, Yee in the similar field of endeavor teaches that in order to cool devices within a substrate, cooling structures, such as, cold plates or a heat pipe configured to use liquid nitrogen or some other liquefied gas (132, 134, Fig. 1 and ¶¶[0014] and [0027]) might be placed on top and/or bottom of the devices (Fig. 1), in order for the device to operate below -25°C (i.e. 10K=-263ºC and 77K=-196ºC, ¶¶[0014] and [0027]).
Accordingly, since the prior art teaches all of the claimed elements, using such elements would lead to predictable results, and as such it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the invention pertains to use the cooling structure disclosed by Yee in the IC die disclosed by Choi in order to remove heat from the IC die and operate the IC die at a desired temperature.
Regarding claim 30 (29), the combined teaching of Choi and Yee discloses wherein the plurality of transistors is to be operated at a temperature below -100°C (Yee, i.e. 10K=-263ºC and 77K=-196ºC, ¶¶[0014] and [0027]).
Regarding claim 31 (3), teaching of Choi was discussed above in the rejection of claim 3. Choi, however, does not explicitly teach that the IC die further comprises a cooling structure operable to remove heat from the IC die to achieve an operating temperature at or below -50°C. Nonetheless, using a cooling structure with the IC die disclosed by Choi in order to remove heat from the IC die to achieve an operating temperature at or below -50°C would have with the capabilities of one of ordinary skill in the art as evidenced by Yee. Namely, Yee in the similar field of endeavor teaches that in order to cool devices within a substrate, cooling structures, such as, cold plates or a heat pipe configured to use liquid nitrogen or some other liquefied gas (132, 134, Fig. 1 and ¶¶[0014] and [0027]) might be placed on top and/or bottom of the devices (Fig. 1), in order for the device to operate below -25°C (i.e. 10K=-263ºC and 77K=-196ºC, ¶¶[0014] and [0027]).
Accordingly, since the prior art teaches all of the claimed elements, using such elements would lead to predictable results, and as such it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the invention pertains to use the cooling structure disclosed by Yee in the IC die disclosed by Choi in order to remove heat from the IC die and operate the IC die at a desired temperature.
Regarding claim 32 (31), the combined teaching of Choi and Yee discloses wherein the plurality of transistors is to be operated at a temperature below -100°C (Yee, i.e. 10K=-263ºC and 77K=-196ºC, ¶¶[0014] and [0027]).
Claim(s) 25-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Choi et al. (US 2017/0365504, hereinafter “Choi”, previously cited) in view of Yee et al. (US 2022/0375869, hereinafter “Yee”, previously cited).
Regarding claim 25, Choi teaches in Figs. 1-7 (Fig. 7 shown above) and related text an integrated circuit (IC) die, comprising:
a plurality of transistors (¶[0014]); and
an interconnect layer (e.g. 112, Fig. 7 and ¶[0015]) above the transistors, the interconnect layer comprising one or more dielectric materials (e.g. 122, 124, Fig. 1 and ¶[0015]) and interconnect lines (e.g. 140, 142, Figs. 1, 7 and ¶[0016]) embedded therein (Fig. 1), wherein, adjacent and parallel ones of the interconnect lines (Fig. 7) having line pitches of not more than 75 nm (i.e. Choi teaches that P is less than approximately 25 nm, Fig. 7 and ¶[0017]) further have a line-space duty cycle of not more than 1%, wherein the line-space duty cycle is calculated the average of width of the interconnect lines divided by an average of the line pitches (i.e. Choi teaches that pitch P is less than approximately 25 nm (Fig. 7 and ¶[0017]) and the line width W is less than approximately 10 nm, (Fig. 7 and ¶[0017]), which for the line widths of less than 0.25 nm (covered by Choi’s range), would result in the line-space duty cycle of not more than 1%. It is noted that there is no allegation of criticality or any evidence demonstrating any difference across the broader range. In fact, applicant’s own disclosure of the broader range (similar to that of Choi), clearly demonstrates that the different portions of the broader range would not work differently (see ClearValue Inc. v. Pearl River Polymers Inc., 668 F.3d 1340, 101 USPQ2d 1773 (Fed. Cir. 2012)).
Choi, however, does not explicitly teach that the plurality of transistors are to be operated at a temperature below -25°C. Nonetheless, using a cooling structure with the IC die disclosed by Choi in order to remove heat from the IC die to achieve an operating temperature at or below -25°C would have with the capabilities of one of ordinary skill in the art as evidenced by Yee. Namely, Yee in the similar field of endeavor teaches that in order to cool devices within a substrate, cooling structures, such as, cold plates or a heat pipe configured to use liquid nitrogen or some other liquefied gas (132, 134, Fig. 1 and ¶¶[0014] and [0027]) might be placed on top and/or bottom of the devices (Fig. 1), in order for the device to operate below -25°C (i.e. 10K=-263ºC and 77K=-196ºC, ¶¶[0014] and [0027]).
Accordingly, since the prior art teaches all of the claimed elements, using such elements would lead to predictable results, and as such it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the invention pertains to use the cooling structure disclosed by Yee in the IC die disclosed by Choi in order to remove heat from the IC die and operate the IC die at a desired temperature.
Regarding claim 26 (25), the combined teaching of Choi and Yee discloses wherein the plurality of transistors is to be operated at a temperature below -50°C (Yee, i.e. 10K=-263ºC and 77K=-196ºC, ¶¶[0014] and [0027]).
Regarding claim 27 (26), the combined teaching of Choi and Yee discloses wherein the plurality of transistors is to be operated at a temperature below -100°C (Yee, i.e. 10K=-263ºC and 77K=-196ºC, ¶¶[0014] and [0027]).
Regarding claim 28 (27), the combined teaching of Choi and Yee discloses wherein for a plurality of adjacent pitches between immediately adjacent ones of those interconnect lines, the sum of the width of the interconnect lines divided by the sum of the widths plus a sum of spaces between the interconnect lines is not more than 0.5 % (i.e. for line width of less than 0.08 nm (covered by Choi’s range) and line spacing of less than approximately 15 nm, the line-space duty cycle, calculated by dividing the sum of the width of the interconnect lines by the sum of the width plus a sum of spaces between the interconnect lines disclosed by Choi would not be more than 0.5%).
Response to Arguments
Applicant's arguments filed November 10, 2025 have been fully considered but they are not persuasive. Specifically, on pages 6-7 of the filed response the applicant argues that “Choi’s own dimensional disclosure yield a duty cycle on the order of 40% (for a two-line/one-pitch example: W / P ≈ 10 / 25 ≈ 0.4), which is nowhere near the "not more than 1%" limitation recited in claim 1. Since Choi not only fails to disclose such widths; but expressly targets widths under approximately 10 nm at pitches under approximately 25 nm in its exemplary regime, there is no direct disclosure or suggestion in Choi of a line-space duty cycle ≤1% at a line pitch ≤75 nm, when the metric is calculated according to the Applicant's recited definition. The examiner respectfully disagrees with this line of reasoning.
To begin with, the line widths and the pitches disclosed by the applicant are overlapping the ranges disclosed by Choi. Specifically, in paragraph [0027] of the specification as published, the applicant discloses that the widths of the interconnect lines can be “less than 10 nm, and potentially 1 nm, or less” and the interconnect pitches can be “no more than 75 nm, and potentially 25 nm, or less”. These ranges are identical with the width of the interconnect lines disclosed by Choi of “less than approximately 10 nm” and fully cover the pitches disclosed by Choi of “less than approximately 25 nanometers (nm)”. While the ranges of the amended claim focus on the lower end of the disclosed ranges, such ranges are still nonetheless disclosed by Choi. Applicant’s selection of the highest possible values of the range disclosed by Choi, to argue that it does not cover the lowest disclosed values seems misguided. Namely, even if at the highest point of the range disclosed by Choi, the line-space duty cycle might be 40%, as argued by the applicant, at the lower end of the range disclosed by Choi the line-space duty cycle would be no more than 1%. Since there is no allegation of criticality or any evidence demonstrating any difference across the broader range, and applicant’s own disclosure of broader range clearly demonstrates that the different portions of the broader range would not work differently, Choi can be considered as disclosing every element of claim 1. In other words, in the absence of any evidence that the different portions of the broader range disclosed by Choi would work differently, Choi can be considered as disclosing every element of claim 1.
Additionally, with respect to Yee reference, on page 8 the applicant recognizes that Yee discloses “cryogenic interconnect system and cooling infrastructure” but then notes that Yee “does not appreciate the architecture changes of an IC die operated at such temperatures disclosed and claimed in the instant application”. The examiner respectfully disagrees.
As discussed above, Yee clearly recognizes that IC dies that includes plurality of transistors and various interconnect structures, similar to those disclosed by Choi, can be operated at low temperatures by utilizing different cooling structures, in order to meet specific design requirements. Accordingly, applying cooling systems disclosed by Yee to the IC die disclosed by Choi would have been within capabilities of one of ordinary skill in the art in order to remove heat from the IC die and operate the IC die at a desired temperature.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.B.C/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893