DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 21-25 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention/species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 8.19.2025.
Specification
The disclosure (amendment filed 5.12.2026) is objected to because of the following informalities:
(a) There are no amendment markings to [0018] as required by MPEP 714; it is unclear what was amended.
(b) Paragraph [0050] introduces new matter; for example: any reference to surface dies 208 and 216 is unsupported by the original disclosure.
The amendment to the disclosure filed 5.12.2026 is denied entry. Appropriate correction is required.
The disclosure (originally filed 4.1.2022) is objected to because of the following informalities: [0080] states die 422’ is provided with its backside facing 427 and 422” is provided with its front end facing 427. However, in Fig. 4C both dies 422’ and 422” have backsides facing 427. Appropriate correction is required.
Drawings
Replacement drawings for Figs. 1-3 and 4C-4E were received on 5.12.2026. These drawings are unacceptable and denied entry because:
(a) Fig. 2 includes new matter, for example: position and details of 208 and 216.
(b) Figs. 4C-4E include new matter, for example: different die orientations. In addition per [0080] it appears only 422’ should be inverted and not 422’’ with respect to the originally filed drawings.
Appropriate correction is required.
Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to because in, originally filed Figs. 4C-4E, the bridge dies 422” and 422’ are not identical (see 422’ above 439 and 445 for an unlabeled layer). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, (a) the caps and related structure of claim 6, (b) the adhesive and related structure of claim 11, and, (c) the pair of surface dies and related structure of claim 14, and, (d) the PCB, ICs, surface dies and related structure of claim 18 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Recall Fig. 2 is elected and the claimed subject matter must be present in Fig. 2 to be elected.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102 and 35 USC § 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 7-8 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nickerson (of record, US 20140159250 A1).
Regarding claim 1, Nickerson discloses a microelectronic structure, comprising:
a substrate (375A to 375B) defining a cavity (occupied by 345A to 350A) therein (Figs. 6-7);
a bridge die (340A+) within the cavity, the bridge die to (capable; MPEP 2111, 2112 and/or 2114) electrically couple a pair of dies to be provided (not required by the claim) on a surface of the substrate (not required by the claim); and
an electrical coupling layer (350A/352A+) between a top (relative to underlying layers; see also applicant’s Fig. 2 where the top surface 227 of the cavity 225 has underlying layers) surface of the cavity and a bottom (relative to 352A; see also applicant’s Fig. 2 where “bridge dies 222a and 222b are shown as having been embedded into cavities 225 such that their backsides face the top surface 227”) surface of the bridge die (Figs. 6-7), the electrical coupling layer including:
a non-conductive component (350A, “adhesive 350A”) including a die bonding film (350A) and defining holes (occupied by 352A) therein; and
electrically conductive structures (352A+, “solder connections 352A”) in the holes, the electrically conductive structures electrically coupling the substrate with the bridge die (Figs. 6-7).
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Regarding claim 2, Nickerson discloses the microelectronic structure of claim 1, further including electrical contact pads (bottommost of 385A) at the bottom surface of the bridge die (Fig. 6), the electrical contact pads in (partly, from a top-down perspective) the holes of the non-conductive component (350A), and in registration with corresponding ones of the electrically conductive structures (352. In a top-down view, 385A overlaps at least partly with holes of 350A; as such, the bottommost of 385A is at least partly in, from a top-down view, the holes as claimed).
Regarding claim 7, Nickerson discloses the microelectronic structure of claim 1, wherein the electrically conductive structures (352A+) include contact pads (bottommost of 385A) at the bottom surface of the bridge die (Fig. 6).
Regarding claim 8, Nickerson discloses the microelectronic structure of claim 1, wherein the electrically conductive structures (352A+) include solder ([0031] – “solder connections 352A”).
Regarding claim 12, Nickerson discloses the microelectronic structure of claim 1, wherein the substrate (375A to 375B) includes electrically conductive features therein including through (layer) vias (some 325A) and bridge vias (other 325A. Fig. 6), wherein the electrically conductive structures (352A+) are in registration with the bridge vias (two 325A under 340A) to electrically couple the substrate with the bridge die (Figs. 6-7).
Claims 1-3, 7-8, 12 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Deshpande et al. (US 20170330835 A1) in view of Nickerson (US 20140159250 A1).
Regarding claim 1, Deshpande discloses (Fig. 1) a microelectronic structure, comprising:
a substrate (110) defining a cavity (112) therein;
a bridge die (150) within the cavity, the bridge die to (capable; MPEP 2111, 2112 and/or 2114) electrically couple a pair of dies (170) to be provided on a (top) surface of the substrate; and
an electrical coupling layer (124+) between a top surface (at 1322; see also applicant’s Fig. 2 where the top surface 227 of the cavity 225 has underlying layers) of the cavity and a bottom surface (abutting 124+; see also applicant’s Fig. 2 where “bridge dies 222a and 222b are shown as having been embedded into cavities 225 such that their backsides face the top surface 227”) of the bridge die (Fig. 1), the electrical coupling layer including: electrically conductive structures (124+).
Deshpande fails to disclose the electrical coupling layer including: a non-conductive component including a die bonding film and defining holes therein; and electrically conductive structures in the holes, the electrically conductive structures electrically coupling the substrate with the bridge die.
Nickerson discloses the electrical coupling layer including: a non-conductive component (350A, “adhesive 350A”) including a die bonding film (350A) and defining holes (occupied by 352A) therein; and electrically conductive structures (352A+, “solder connections 352A”) in the holes, the electrically conductive structures electrically coupling the substrate with the bridge die (340A, Figs. 6-7).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the electrical coupling layer of Nickerson in Deshpande and arrive at the claimed invention so as to securely attach a die on a substrate.
Regarding claim 2, Deshpande/Nickerson (together) discloses the microelectronic structure of claim 1, further including electrical contact pads (184) at the bottom surface of the bridge die (150, Deshpande Fig. 1), the electrical contact pads in the holes of the non-conductive component (once the non-conductive component 350A of Nickerson at Fig. 6 is applied to Fig. 1 of Deshpande, 184 is in the holes of 350A), and in registration with corresponding ones of the electrically conductive structures (as 124, Fig. 1 of Deshpande).
Regarding claim 3, Deshpande/Nickerson discloses the microelectronic structure of claim 1, wherein the electrically conductive structures (124+; meaning 124+184) include liquid metal (in 184, “interconnects 184, such as reflowable solder bumps or balls”).
Regarding claim 7, Deshpande/Nickerson discloses the microelectronic structure of claim 1, wherein the electrically conductive structures (124+; meaning 124+184) include contact pads (184) at the bottom surface of the bridge die (150, Fig. 1).
Regarding claim 8, Deshpande/Nickerson discloses the microelectronic structure of claim 1, wherein the electrically conductive structures (124+; meaning 124+184) include solder (in 184, “interconnects 184, such as reflowable solder bumps or ball”).
Regarding claim 12, Deshpande/Nickerson discloses the microelectronic structure of claim 1, wherein the substrate includes electrically conductive features (136) therein including through (layer) vias (outer 136) and bridge vias (inner 136), wherein the electrically conductive structures (124+) are in registration with the bridge vias (inner 136) to electrically couple the substrate with the bridge die (Fig. 1)
Regarding claim 14, Deshpande discloses a (Fig. 1) semiconductor package, comprising:
a microelectronic structure (110+) including:
a substrate (110) defining a cavity (112) therein;
a bridge die (150) within the cavity;
an electrical coupling layer (124+) between a top surface (at 1322; see also applicant’s Fig. 2 where the top surface 227 of the cavity 225 has underlying layers) of the cavity and a bottom surface (abutting 124+; see also applicant’s Fig. 2 where “bridge dies 222a and 222b are shown as having been embedded into cavities 225 such that their backsides face the top surface 227”) of the bridge die, the electrical coupling layer including: electrically conductive structures (124+); and
a pair of surface dies (170) on a (top) surface of the microelectronic structure and electrically coupled to the bridge die (per 156 for example) such that the bridge die provides an electrical coupling (per 156 for example) between the pair of surface dies (Fig. 1).
Deshpande fails to disclose the electrical coupling layer including: a non-conductive component including a die bonding film and defining holes therein; and electrically conductive structures in the holes, the electrically conductive structures electrically coupling the substrate with the bridge die.
Nickerson discloses the electrical coupling layer including: a non-conductive component (350A, “adhesive 350A”) including a die bonding film (350A) and defining holes (occupied by 352A) therein; and electrically conductive structures (352A+, “solder connections 352A”) in the holes, the electrically conductive structures electrically coupling the substrate with the bridge die (340A, Figs. 6-7).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the electrical coupling layer of Nickerson in Deshpande and arrive at the claimed invention so as to securely attach a die on a substrate.
Regarding claim 15, Deshpande/Nickerson (together) discloses the semiconductor package of claim 14, further including electrical contact pads (184, Fig. 1 of Deshpande) at the bottom surface of the bridge die (150), the electrical contact pads in the holes of the non-conductive component (once the non-conductive component 350A of Nickerson at Fig. 6 is applied to Fig. 1 of Deshpande, 184 is in the holes of 350A), and in registration with corresponding ones of the electrically conductive structures (as 124, Fig. 1 of Deshpande).
Regarding claim 16, Deshpande/Nickerson discloses the semiconductor package of claim 14, wherein the electrically conductive structures (124+; meaning 124+184) include liquid metal (in 184, “interconnects 184, such as reflowable solder bumps or balls”).
Claims 4-6 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Deshpande et al. (US 20170330835 A1) in view of Nickerson (US 20140159250 A1) as applied to claims 3 and 16 above, and further in view of Sylvestre et al. (US 9761542 B1).
Regarding claims 4 and 5, Deshpande/Nickerson fails to disclose (claim 4) the microelectronic structure of claim 3, wherein the liquid metal includes gallium, or an alloy of gallium, and, (claim 5) the microelectronic structure of claim 4, wherein the alloy of gallium includes at least one of an alloy of gallium and indium, a eutectic alloy of gallium, indium, and tin, or a eutectic alloy of gallium, indium, and zinc.
Sylvestre discloses (claim 4) the microelectronic structure of claim 3, wherein the liquid metal (114/514) includes gallium, or an alloy of gallium (Figs. 1 and 5, “the solder joints are comprised of gallium, or a gallium indium alloy”), and, (claim 5) the microelectronic structure of claim 4, wherein the alloy of gallium includes at least one of an alloy of gallium and indium (“the solder joints are comprised of gallium, or a gallium indium alloy”), a eutectic alloy of gallium, indium, and tin, or a eutectic alloy of gallium, indium, and zinc.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the liquid metal of Sylvestre in Deshpande/Nickerson and arrive at the claimed invention so as to “allows a softer underfill to be used, which in turn reduces stresses during operation and thermal cycling that are caused by the different coefficient of thermal expansion (CTE) of the electronic circuit chip and the circuit board substrate” per the Abstract of Sylvestre.
Regarding claim 6, Deshpande/Nickerson discloses (Fig. 1) the microelectronic structure of claim 3, wherein the substrate (110) includes first electrically conductive features (136) therein, and the bridge die includes second electrically conductive features (160) therein, the microelectronic structure further including caps (e.g., 158)
Deshpande/Nickerson fails to disclose caps comprising nickel or tungsten.
Sylvestre discloses caps comprising nickel or tungsten (110/112, “the material for the UBM pads 112 and the surface mount pads 110 may include, but is not limited to, tungsten, tantalum, nickel, niobium, titanium, and/or molybdenum”, Figs. 1 and 5).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the caps of Sylvestre in Deshpande/Nickerson and arrive at the claimed invention so as to employ liquid interconnections which “allows a softer underfill to be used, which in turn reduces stresses during operation and thermal cycling that are caused by the different coefficient of thermal expansion (CTE) of the electronic circuit chip and the circuit board substrate” per the Abstract of Sylvestre.
Regarding claim 17, Deshpande/Nickerson fails to disclose the semiconductor package of claim 16, wherein the liquid metal includes gallium, or an alloy of gallium.
Sylverstre discloses wherein the liquid metal includes gallium, or an alloy of gallium (Figs. 1 and 5, “the solder joints are comprised of gallium, or a gallium indium alloy”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the liquid metal of Sylvestre in Deshpande/Nickerson and arrive at the claimed invention so as to “allows a softer underfill to be used, which in turn reduces stresses during operation and thermal cycling that are caused by the different coefficient of thermal expansion (CTE) of the electronic circuit chip and the circuit board substrate” per the Abstract of Sylvestre.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Deshpande et al. (US 20170330835 A1) in view of Nickerson (US 20140159250 A1) as applied to claim 1 above, and further in view of Ayotte et al. (US 20090256268 A1).
Regarding claims 9-10, Deshpande/Nickerson fails to disclose (claim 9) the microelectronic structure of claim 1, wherein the non-conductive component includes a polymer, and, (claim 10) the microelectronic structure of claim 1, wherein the non-conductive component includes at least one of: epoxy, polyimide, bismaleimide, acrylate, silicone, cyanate ester, silica, alumina, aluminum hydroxide, mica, glass, polyethylene terephthalate polyolefin, copolymer polypropylene, block copolymer polypropylene, homopolypropylene, polybutene, polymethylpentene, ethylene-vinylacetate copolymer, ionomer resin, ethylene(meth)acrylic acid copolymer, ethylene(meth)acrylic acid ester (random or alternating) copolymer, ethylene-butene copolymer, ethylene-hexene copolymer, polyurethane, polyester, polyethyleneterephthalate, polyethylenenaphthalate, polycarbonate, polyetheretherketone, polyetherimide, polyamide, whole aromatic polyamide, polyphenylsulfide, fluorine resin, polyvinyl chloride, polyvinylidene chloride, or a cellulose resin.
Ayotte discloses (claim 9) the microelectronic structure of claim 1, wherein the non-conductive component (140) includes a polymer (“underfill layer 140 comprises a material selected from the group consisting of epoxy, silica filled epoxy, silicone, acrylic resin, poly vinyl chloride resin, a thermosetting resin and a thermoplastic”, [0013]), and, (claim 10) the microelectronic structure of claim 9, wherein the non-conductive component (140, [0013]) includes at least one of: epoxy (“epoxy”), polyimide, bismaleimide, acrylate, silicone (“silicone”), cyanate ester, silica, alumina, aluminum hydroxide, mica, glass, polyethylene terephthalate polyolefin, copolymer polypropylene, block copolymer polypropylene, homopolypropylene, polybutene, polymethylpentene, ethylene-vinylacetate copolymer, ionomer resin, ethylene(meth)acrylic acid copolymer, ethylene(meth)acrylic acid ester (random or alternating) copolymer, ethylene-butene copolymer, ethylene-hexene copolymer, polyurethane, polyester, polyethyleneterephthalate, polyethylenenaphthalate, polycarbonate, polyetheretherketone, polyetherimide, polyamide, whole aromatic polyamide, polyphenylsulfide, fluorine resin, polyvinyl chloride, polyvinylidene chloride, or a cellulose resin.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the material of Ayotte in Deshpande/Nickerson and arrive at the claimed invention so as to enable means from protecting and/or providing mechanical support to interconnect structures since the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Deshpande et al. (US 20170330835 A1) in view of Nickerson (US 20140159250 A1) as applied to claim 1 above, and further in view of Kiuchi et al. (US 20100279491 A1).
Regarding claim 11, Deshpande/Nickerson fails to disclose the microelectronic structure of claim 1, further including an adhesive on the non-conductive component to bond the non-conductive component to the bridge die at one surface thereof and to the top surface of the cavity at another surface thereof.
Kiuchi discloses “The die attach film 3…may have a multilayer structure of two or more layers by appropriately combining, in addition to the epoxy resin, thermosetting resins differing in the glass transition temperature or thermosetting resins differing in the thermosetting temperature” ([0137], emphasis added).
The examiner takes the position that Kiuchi discloses an embodiment with a die attach film (3) comprising three layers wherein the outer layers qualify as adhesives per MPEP 2111. Said die attach film (3) is employed to bond a chip (7) to a die pad (10). Hence, Kiuchi discloses further including an adhesive (outer layer) on the non-conductive component (middle layer) to bond the non-conductive component to the bridge die (7) at one surface thereof and to the top surface of a substrate (10) at another surface thereof (Fig. 3).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include an adhesive as claimed in Deshpande/Nickerson and arrive at the claimed invention in view of Kiuchi so as to ensure proper adhesion is achieved and prevent delamination or mechanical failure.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Deshpande et al. (US 20170330835 A1) in view of Nickerson (US 20140159250 A1) as applied to claim 1 above, and further in view of Roy et al. (US 20140174807 A1).
Regarding claim 13, Deshpande/Nickerson fails to disclose the microelectronic structure of claim 1, wherein the substrate includes glass, silicon or an organic material.
Roy discloses wherein the substrate (302) includes glass, silicon or an organic material (“Substrate 302 may be a package substrate 302, such as that manufactured by substrate manufacturing process 102 of FIG. 1 and may comprise an organic polymer such as an epoxy.”, [0020]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the substrate material of Roy in Deshpande/Nickerson and arrive at the claimed invention because said material is well-known and commonly used in semiconductor packaging and would have yielded predictable results since the use of conventional materials to perform their known function is prima-facie obvious (See MPEP 2144.07).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Deshpande et al. (US 20170330835 A1) in view of Nickerson (US 20140159250 A1) and Liff et al. (US 20200098692 A1).
Regarding claim 18, Deshpande discloses an integrated circuit (IC) device (Fig. 1) assembly including:
a microelectronic structure (110+) including:
a substrate (110) defining a cavity (112) therein;
a bridge die (150) within the cavity;
an electrical coupling layer (124+) between a top surface (at 1322; see also applicant’s Fig. 2 where the top surface 227 of the cavity 225 has underlying layers) of the cavity and a bottom surface (abutting 124+; see also applicant’s Fig. 2 where “bridge dies 222a and 222b are shown as having been embedded into cavities 225 such that their backsides face the top surface 227”) of the bridge die, the electrical coupling layer including: electrically conductive structures (124+); and
a pair of surface dies (170) on a surface (top) of the microelectronic structure and electrically coupled (via, e.g., 156) to the bridge die such that the bridge die provides an electrical coupling (via, e.g., 156) between the pair of surface dies (Fig. 1).
Deshpande fails to disclose (a) a printed circuit board; and a plurality of integrated circuit components coupled to the printed circuit board, individual ones of the integrated circuit components including one or more semiconductor packages, individual ones of the semiconductor packages including a microelectronic assembly, and, (b) the electrical coupling layer including: a non-conductive component including a die bonding film and defining holes therein; and electrically conductive structures in the holes, the electrically conductive structures electrically coupling the substrate with the bridge die.
Nickerson discloses (b) the electrical coupling layer including: a non-conductive component (350A, “adhesive 350A”) including a die bonding film (350A) and defining holes (occupied by 352A) therein; and electrically conductive structures (352A+, “solder connections 352A”) in the holes, the electrically conductive structures electrically coupling the substrate with the bridge die (340A, Figs. 6-7).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the electrical coupling layer of Nickerson in Deshpande and arrive at the claimed invention so as to securely attach a die on a substrate.
Liff discloses (a) a printed circuit board (1702, Fig. 10); and a plurality of integrated circuit components (1720/1724/1726/1732) coupled to the printed circuit board, individual ones of the integrated circuit components including one or more semiconductor packages (each of 1720/1724/1726/1732), individual ones of the semiconductor packages including a microelectronic assembly (Fig. 10).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the arrangement of Liff in Deshpande/Nickerson and arrive at the claimed invention so as to provide an IC device with high density integration and expanded functionality since the use of conventional materials (IC elements in this case) to perform their known function is prima-facie obvious (MPEP 2144.07).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Deshpande et al. (US 20170330835 A1) in view of Nickerson (US 20140159250 A1) and Liff et al. (US 20200098692 A1) as applied to claim 18 above, and further in view of Sylvestre et al. (US 9761542 B1).
Regarding claim 19, Deshpande/Nickerson/Liff fails to disclose the IC device assembly of claim 18, wherein the electrically conductive structures include liquid metal, the liquid metal including gallium, or an alloy of gallium.
Sylvestre discloses wherein the electrically conductive structures include liquid metal, the liquid metal including gallium, or an alloy of gallium (Figs. 1 and 5, “the solder joints are comprised of gallium, or a gallium indium alloy”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the liquid metal of Sylvestre in Deshpande/Nickerson/Liff and arrive at the claimed invention so as to “allows a softer underfill to be used, which in turn reduces stresses during operation and thermal cycling that are caused by the different coefficient of thermal expansion (CTE) of the electronic circuit chip and the circuit board substrate” per the Abstract of Sylvestre.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Deshpande et al. (US 20170330835 A1) in view of Nickerson (US 20140159250 A1) and Liff et al. (US 20200098692 A1) as applied to claim 18 above, and further in view of Ayotte et al. (US 20090256268 A1).
Regarding claim 20, Deshpande/Nickerson fails to disclose the microelectronic assembly of claim 18, wherein the non-conductive component includes at least one of: epoxy, polyimide, bismaleimide, acrylate, silicone, cyanate ester, silica, alumina, aluminum hydroxide, mica, glass, polyethylene terephthalate polyolefin, copolymer polypropylene, block copolymer polypropylene, homopolypropylene, polybutene, polymethylpentene, ethylene-vinylacetate copolymer, ionomer resin, ethylene(meth)acrylic acid copolymer, ethylene(meth)acrylic acid ester (random or alternating) copolymer, ethylene-butene copolymer, ethylene-hexene copolymer, polyurethane, polyester, polyethyleneterephthalate, polyethylenenaphthalate, polycarbonate, polyetheretherketone, polyetherimide, polyamide, whole aromatic polyamide, polyphenylsulfide, fluorine resin, polyvinyl chloride, polyvinylidene chloride, or a cellulose resin.
Ayotte discloses wherein the non-conductive component (140, [0013]) includes at least one of: epoxy (“epoxy”), polyimide, bismaleimide, acrylate, silicone (“silicone”), cyanate ester, silica, alumina, aluminum hydroxide, mica, glass, polyethylene terephthalate polyolefin, copolymer polypropylene, block copolymer polypropylene, homopolypropylene, polybutene, polymethylpentene, ethylene-vinylacetate copolymer, ionomer resin, ethylene(meth)acrylic acid copolymer, ethylene(meth)acrylic acid ester (random or alternating) copolymer, ethylene-butene copolymer, ethylene-hexene copolymer, polyurethane, polyester, polyethyleneterephthalate, polyethylenenaphthalate, polycarbonate, polyetheretherketone, polyetherimide, polyamide, whole aromatic polyamide, polyphenylsulfide, fluorine resin, polyvinyl chloride, polyvinylidene chloride, or a cellulose resin.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the material of Ayotte in Deshpande/Nickerson/Liff and arrive at the claimed invention so as to enable means from protecting and/or providing mechanical support to interconnect structures since the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Response to Arguments
Applicant's arguments filed 5.12.2026 have been fully considered but they are not persuasive.
Applicant alleges [0017], [0018], [0050], [0058], [0061], [0065], [0067], [0073] and [0080] have been amended to overcome objections to the specification/drawings of the previous Office Action. See pg. 14-17 of the reply filed 5.12.2026.
The amendments to the specification filed 5.12.2026 have not been entered for containing new matter and the specification is still objected to. See objections above for details.
Applicant alleges Figs. 1, 2-3 and 4C-4E have been amended to overcome objections to the specification/drawings of the previous Office Action. See pg. 14-17 of the reply filed 5.12.2026.
The amendments to the drawings filed 5.12.2026 have not been entered for containing new matter and the drawings are still objected to. See objections above for details.
Applicant alleges, pg. 18-20 of the replied filed 5.12.2026, that the 35 USC 112 rejections of the previous Office Action are overcome; the examiner agrees and withdraws the 35 USC 112 rejections of the previous Office Action.
Applicant alleges “there is no pre-formed cavity in a substrate into which a die is placed”, “There is no pre-formed substrate cavity, no cavity sidewalls, and no defined top surface of a cavity anywhere in Nickerson”, “The Examiner's mapping of "375A to 375B" as the substrate is not supported by Nickerson's disclosure:….” and “Because Nickerson discloses no cavity, it cannot disclose a bridge die within a cavity or an electrical coupling layer between a top surface of the cavity and a bottom surface of the bridge die, as required by claim 1.”.
This is not persuasive because “a substrate defining a cavity” is not a process step in which a pre-formed cavity is required. Furthermore, “substrate” is a broad term in which any group of layers that provide a base are interpreted as a substrate per MPEP 2111.
Applicant alleges “The region "occupied by 345A to 350A" therefore spans from the top face to the bottom face of die 340A itself -- that is, the die body and its immediately attached elements on both faces, fully encapsulated within the BBUL build-up stack as plainly shown in Fig. 6 of Nickerson. The Examiner is treating the die and its attached elements as a "cavity in a substrate," which finds no support anywhere in Nickerson's disclosure or figures”.
This is not found persuasive because the bridge die (340A) occupies a volume of the substrate (375A to 375B) which amounts to a cavity as claimed.
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Applicant alleges solder connections 352A “are independent conductive structures and are nowhere described in Nickerson as being positioned within holes of adhesive 350A”.
This is not persuasive because per MPEP 2125, 352A is positioned in holes of 350A. See Fig. 6 wherein there is a discontinuity in 350A for the placement of 352A; that amounts to holes as claimed.
Applicant alleges “The Examiner's reliance on a "top-down perspective" overlap between the bottommost ends of vias 385A and the alleged holes of 350A is not a showing that those elements are physically "in the holes" of the non-conductive component as claim 2 requires”.
This is not persuasive because from a top down perspective the bottommost of 385A overlaps with an area of 352A where the holes are defined. The claim does not preclude this interpretation and should recite the claimed features with respect to a cross-sectional view to overcome the examiners position.
Applicant alleges “elements 385A in Nickerson are vias as described [0031] of Nickerson, not contact pads at the bottom surf ace of the bridge die”.
This is not persuasive because while 385A are vias, a bottommost thereof are contact pads as they contact 352A. Said bottommost is a surface of 385A on plane into the page since 385A is a three-dimensional structure.
Applicant alleges “Applicant does not dispute that Nickerson discloses solder connections 352A, but as argued above, those solder connections are not electrically conductive structures in the holes of a non-conductive die bonding film as required by claim 1 from which claim 8 depends”.
This is not persuasive because per MPEP 2125, 352A is positioned in holes of 350A. See Fig. 6 wherein there is a discontinuity in 350A for the placement of 352A; that amounts to holes as claimed.
Applicant alleges “Applicant further notes that the Examiner's mapping relies on a distinction between "some 325A" and "other 325A" as through vias and bridge vias respectively -- a distinction that Nickerson itself does not make”.
This is not found persuasive as the claim language does not preclude separating multiple elements 325A into different classifications.
Applicant alleges:
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Applicant is reminded that exceptions under 35 USC 102(b)(2)(C) apply to prior art which qualifies as prior art only under 35 USC 102(a)(2); see, e.g., MPEP 2154.02.
In the instant case, the application has an effective filing date of 4.1.2022 and Deshpande et al. (US 20170330835 A1) has a publication date of 11.16.2017 which qualifies Deshpande et al. as prior art under 35 USC 102(a)(1).
Finally, the 35 USC 102(b)(2)(C) exception is not applicable to prior art under 35 USC 102(a)(1).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andres Munoz/Primary Examiner, Art Unit 2818
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