DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 5, 7, 8, 12, 16, 18, 19, 23, and 25 have been amended.
Claims 4 and 15 have been cancelled.
Claims 1-3, 5-14, and 16-25 have been examined.
The drawing objections in the previous Office Action have been addressed and are withdrawn.
The double patenting rejection in the previous Office Action has been addressed and is withdrawn.
The § 112 rejections in the previous Office Action have been addressed and are maintained.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 8 recites, at lines 4-5, “said all fetch operations that are to be retained in the pipeline stage for said one or more cycles.” There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this limitation is interpreted as, “ the fetch operation[[s]] that [[are]]is to be retained in the pipeline stage for said one or more cycles.” Claim 19 has similar language and is similarly rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-9, 12-14,16-20, and 23-25 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication No. 2015/0100763 by Holm (hereinafter referred to as “Holm”) in view of US Patent No. 6,385,715 by Merchant et al. (hereinafter referred to as “Merchant”) in view of US Patent No. 6,604,190 by Tran (hereinafter referred to as “Tran”).
Regarding claims 1, 12, and 23, taking claim 1 as representative, Holm discloses:
an apparatus comprising: a first instruction storage, wherein the first instruction storage is a level 0 (L0) cache (Holm discloses, at Figure 1 and related description, an apparatus having a first instruction storage, e.g., uop cache 20.);
a second instruction storage (Holm discloses, at Figure 1 and related description, a second instruction storage, e.g., uop queues 6.); and
a fetch unit coupled with the first and second instruction storage, the fetch unit including a plurality of sets of fetch circuitry, including a first set of fetch circuitry, each of the sets of fetch circuitry spanning a same plurality of pipeline stages, wherein the second instruction storage has …read ports… the first set of fetch circuitry to (Holm discloses, at Figure 1 and related description, a fetch unit having multiple sets of fetch circuitry spanning a same plurality of pipeline stages, e.g., fetch units 8. Holm also discloses, at Figure 6 and related description, reading from a second instruction storage, which discloses at least one read port.):
initiate a fetch operation for a block of instructions, the fetch operation to have an indication that the block of instructions is to be read from the second instruction storage (Holm discloses, at Figure 6 and related description, initiating a fetch request to the uop cache, which discloses an indication to read from the second instruction storage.);
retain the fetch operation for the block of instructions at a pipeline stage of the plurality of pipeline stages, for one or more cycles, until a hazard corresponding to the pipeline stage of the first set of fetch circuitry has been removed (Holm discloses, at Figure 6 and related description, stalling the fetch for a number of cycles in response to the uop queue filling, i.e., a hazard corresponding to the first set of fetch circuitry.); …and
once the hazard has been removed, read the block of instructions… for the fetch operation (Holm discloses, at Figure 6 and related description, unstalling the fetch in response to space becoming available.).
Holm does not explicitly disclose storing the block of instructions from the second instruction storage to the first instruction storage, during the one or more cycles; and the aforementioned read is from the first instruction storage.
However, in the same field of endeavor (e.g., instruction processing) Merchant discloses:
storing instructions from the second instruction storage to the first instruction storage, during the one or more cycles; and reading from the first instruction storage (Merchant discloses, at Figure 1 and related description, storing an instruction from an issue queue to a replay queue during a stall and then reading the instruction from the replay queue.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Holm to include the replay queue disclosed by Merchant in order to improve performance by preventing long latency instructions from needlessly consuming additional resources, e.g., through repeated execution or fetch and decode.
Holm does not explicitly disclose fewer read ports than sets of fetch circuitry.
However, in the same field of endeavor (e.g., processing) Tran discloses:
a single read port (Tran discloses, at col. 93, lines 60-62, architectures limited to a single read port.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Holm to include a single read port, as disclosed by Tran, because implementing a single read port reduces size, cost, and complexity, albeit at the cost of performance, which is one of the many well-known tradeoffs that are within the capability of those having ordinary skill in the art.
Regarding claims 2 and 13, taking claim 2 as representative, Holm, as modified, discloses the elements of claim 1, as discussed above. Holm also discloses:
the first set of fetch circuitry is further to: determine that the block of instructions is to be read from the second instruction storage; and provide the indication that the block of instructions is to be read from the second instruction storage to the fetch operation (Holm discloses, at Figure 6 and related description, initiating a fetch request to the uop cache, which discloses determining to read from the second instruction storage and providing indication to read from the second instruction storage.).
Regarding claims 3, 14, and 24, taking claim 3 as representative, Holm, as modified, discloses the elements of claim 1, as discussed above. Holm does not explicitly disclose during the one or more cycles, the first set of fetch circuitry is further to change the indication to an indication that the block of instructions is to be read from the first instruction storage.
However, in the same field of endeavor (e.g., instruction processing) Merchant discloses:
indication to read from the replay queue (Merchant discloses, at Figure 1 and related description, while stalled, determining that the instructions will be read from the replay queue, which discloses so indicating.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Holm to include the replay queue disclosed by Merchant in order to improve performance by preventing long latency instructions from needlessly consuming additional resources, e.g., through repeated execution or fetch and decode.
Regarding claims 5 and 16, taking claim 5 as representative, Holm, as modified, discloses the elements of claim 1, as discussed above. Holm also discloses:
the first instruction storage has … read ports … (Holm discloses, at Figure 1 and related description, reading from a first instruction storage, which discloses at least one read port.).
Holm does not explicitly disclose having at least as many read ports as the total number.
However, in the same field of endeavor (e.g., processing) Tran discloses:
supplying a read port for each decoder (Tran discloses, at col. 10, lines 5-6, a read port for each decoder, which discloses at least as many as a total number of front end units.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Holm to include multiple read ports, as disclosed by Tran, because implementing multiple read ports reduces access latency, albeit at the cost of size, complexity, and cost, which is one of the many well-known tradeoffs that are within the capability of those having ordinary skill in the art.
Regarding claims 6, 17, and 25, taking claim 6 as representative, Holm, as modified, discloses the elements of claim 5, as discussed above. Holm also discloses:
the total number is at least three (Holm discloses, at Figure 1 and related description, (Holm discloses, at Figure 1 and related description, at least three fetch units.).
Regarding claims 7 and 18, taking claim 7 as representative, Holm, as modified, discloses the elements of claim 1, as discussed above. Holm also discloses:
…a level 1 (L1) instruction cache (Holm discloses, at Figure 1 and related description, L1 instruction cache.).
Holm does not explicitly disclose the L1 is the second instruction storage. However, it would have been obvious to modify Holm such that the second instruction storage used the particular cache configuration claimed. Given Holm’s disclosure of a hierarchical cache, selecting which levels to use for which purpose represents obvious design choices within the capability of those having ordinary skill in the art.
Regarding claims 8 and 19, taking claim 8 as representative, Holm, as modified, discloses the elements of claim 1, as discussed above. Holm does not explicitly disclose the fetch unit is to store blocks of instructions read from the second instruction storage in the first instruction storage for all fetch operations that are to be retained in the pipeline stage for one or more cycles due to hazards associated with said all fetch operations that are to be retained in the pipeline stage for said one or more cycles.
However, in the same field of endeavor (e.g., instruction processing) Merchant discloses:
storing instructions from the second instruction storage to the first instruction storage for … fetch operations that are to be retained in the pipeline stage for one or more cycles due to hazards associated with fetch operations (Merchant discloses, at Figure 1 and related description, storing instructions from an issue queue to a replay queue during a stall.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Holm to include the replay queue disclosed by Merchant in order to improve performance by preventing long latency instructions from needlessly consuming additional resources, e.g., through repeated execution or fetch and decode.
Merchant does not explicitly disclose storing all such instructions in the replay queue. However, Merchant also discloses a replay loop. It would have been obvious to modify Merchant to store all such instructions in the replay queue and eliminate the replay loop because doing so would improve performance by reducing size and complexity of the replay circuitry.
Regarding claims 9 and 20, taking claim 9 as representative, Holm, as modified, discloses the elements of claim 1, as discussed above. Holm also discloses:
a second set of fetch circuitry, of the plurality of sets of fetch circuitry, is to advance a second fetch operation for a second block of instructions into the pipeline stage of the second set of fetch circuitry from a pipeline stage immediately preceding the pipeline stage of the second set of fetch circuitry, during an initial cycle of the one or more cycles (Holm discloses, at Figure 6 and related description, initiating a fetch request at a second fetch unit while the first is stalled, which discloses doing so from an immediately preceding pipeline stage during an initial cycle of the one or more cycles.).
Claims 10 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Holm in view of Merchant in view of US Publication No. 2021/0326141 by Tran (hereinafter referred to as “Tran ‘141”).
Regarding claims 10 and 21, taking claim 10 as representative, Holm, as modified, discloses the elements of claim 1, as discussed above. Holm does not explicitly disclose to read the block of instructions from the first instruction storage, instead of the second instruction storage, is to prevent a read port conflict.
However, in the same field of endeavor (e.g., processing) Tran ‘141 discloses:
implementing memory to prevent read port conflicts (Tran ‘141 discloses, at ¶ [0032], implementing memory to prevent read port conflicts.)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Holm to include read port conflict prevention, as disclosed by Tran ‘141, in order to improve performance by increasing memory accessibility.
Claims 11 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Holm in view of Merchant in view of US Publication No. 2015/0205725 by Al-Otoom et al. (hereinafter referred to as “Al-Otoom”).
Regarding claims 11 and 22, taking claim 11 as representative, Holm, as modified, discloses the elements of claim 1, as discussed above. Holm does not explicitly disclose to read the block of instructions from the first instruction storage is to consume less power than to read the block of instructions from the second instruction storage.
However, in the same field of endeavor (e.g., processing) Al-Otoom discloses:
an L0 that consumes less power than other memory (Al-Otoom discloses, at ¶ [0037], L0 consumes less memory than other memory.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Holm to include a lower power L0, as disclosed by Al-Otoom, in order to improve performance by reducing power consumption.
Response to Arguments
On page 1 of the response filed November 3, 2025 (“response”), the Applicant argues, “the independent claims have been amended and these amendments have not yet been considered by the Examiner for him to determine whether or not they overcome the provisional non-statutory double patenting rejection. Further, additional amendments may potentially be made before allowance of the present case that could potentially overcome any maintained provisional non-statutory double patenting rejection. Accordingly, Applicants respectfully request that the Examiner allow them to defer the decision of whether to file a Terminal Disclaimer, whether to amend the claims to overcome any maintained double- patenting rejections, or to otherwise address any maintained double patenting rejections.”
Double patenting rejections cannot be held in abeyance. See MPEP § 804. However, the double patenting rejection is withdrawn based on the claim amendments.
On page 1 of the response the Applicant argues, “Applicants respectfully submit that claims 8 and 19 have been amended to overcome the rejection. Accordingly, Applicants respectfully request that the Examiner withdraw the rejection of claims 8 and 19.”
Though fully considered, the Examiner respectfully disagrees. The amendments read on a plurality of fetch operations, but claim 1 only recites a single fetch operation. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On page 3 of the response the Applicant argues, “The Office Action has relied upon the uop cache 20 of Holm to reject the claimed first instruction storage. However, the uop cache 20 is not a level 0 (LO) instruction cache.”
Though fully considered, the Examiner respectfully disagrees. Holm explicitly discloses, e.g., at ¶ [0053], the uop cache is a level 0 instruction cache. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On page 3 of the response the Applicant argues, “he Office Action has also relied upon storing an instruction from an issue queue to a replay queue of Merchant to reject the claimed store the block of instructions from the second instruction storage to the first instruction storage (i.e., a level 0 (LO) instruction cache). However, the replay queue is not a level 0 (LO) instruction cache and there seems no apparent reason why storing from the issue queue to the replay queue of Merchant would make it obvious to store from the second instruction storage to a level 0 (LO) instruction cache.”
Though fully considered, the Examiner respectfully disagrees. The Applicant is arguing references individually, which is not persuasive when the rejection is based on a combination of references. See MPEP § 2145. Merchant discloses that it is known to move instructions from one memory to another when there is a stall to allow processing to advance. It would have been obvious to apply these teachings to Holm for the same reason. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On pages 3-5 of the response the Applicant argues the remaining claims are allowable for similar reasons.
Though fully considered, the Examiner respectfully disagrees. The reasons set forth in the remarks and rejections presented above, including those regarding the independent claims, are applicable to these claims.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/
Primary Examiner, Art Unit 2183