DETAILED ACTION
Response to Amendment
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-13 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claims do not fall within at least one of the four categories of patent eligible subject matter because the claims are directed to a signal per se and mere information in the form of data. More specifically, the claims are directed to “a machine-readable medium” (see Claim 1, line 1). However, the instant specification does not define a “machine-readable medium”. Rather, it only states “machine-readable storage media may include, without limitation, non-transitory, tangible arrangements of articles manufactured or formed by a machine or device, including storage media such as hard disks, any other type of disk including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), phase change memory (PCM), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.” paragraph 0080. “A claim whose BRI [broadest reasonable interpretation] covers both statutory and non-statutory embodiments embraces subject matter that is not eligible for patent protection and therefore is directed to non-statutory subject matter.” MPEP § 2106.03(II). “For example, the BRI of machine readable media can encompass non-statutory transitory forms of signal transmission, such as a propagating electrical or electromagnetic signal per se.” Id. Accordingly, the claims are directed to non-statutory subject matter. Applicant is advised to add the limitation “non-transitory” to the claims in order to overcome this 35 USC § 101 rejection. See 1351 OG 212.
Applicant states “the 101 rejections are overcome by the amendments to the independent claims”. Response, page 5. However, it is noted that no such amendment was made to the claims. Accordingly, this rejection remains.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8, 9, 12, and 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Swarbrick (U.S. Patent Application Publication Number 2019/0266125), Capalija et al. (U.S. Patent Application Publication Number 2020/0401402), and Kim et al. (U.S. Patent Number 11,074,207).
Regarding Claims 1 and 14, Swarbrick discloses a machine-readable medium (MRM) comprising:
a design of an apparatus to be manufactured (paragraph 0042), the apparatus to include:
one or more cores (Figure 1, item 110A, paragraph 0017; i.e., a processor contains at least one core), and
a network-on-chip (NoC) (Figure 1, item 105) having at least one port of a first type (Figure 1, item 115 connected to logic block 110A) and at least one port of a second type (Figure 1, item 115 connected to logic block 110B), wherein the first type is to communicate with the one or more cores according to a first protocol and the second type is to communicate with an intellectual property (IP) block (paragraph 0017; i.e., IP blocks commonly take the form of processors or digital signal processing blocks) according to an open-standard protocol (paragraph 0022; i.e., the two ingress logic blocks 115 can each be programmed to operate according to two different protocols [including AXI, which is an open-standard protocol - paragraph 0019] at the same time).
Swarbrick does not expressly disclose the first protocol is a proprietary protocol (although does state that any protocol can be used to facilitate communication between the logic blocks and NoC - paragraph 0019); and
a clock controller to bring the IP block out of reset before bringing the one or more cores out of reset.
In the same field of endeavor (e.g., processor communications over a NoC), Capalija teaches a port is to communicate with one or more cores according to a proprietary protocol (paragraphs 0013 and 0027).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Capalija’s teachings of processor communications over a NoC with the teachings of Swarbrick, for the purpose of allowing for specialized, optimized communication and control between system components which can lead to increased efficiency, reduced complexity, and potentially higher performance in specific applications.
Also in the same field of endeavor (e.g., processor communications in an integrated circuit), Kim teaches a clock controller (Figure 1, item 120; i.e., item 120 can work with other components 440 and 460 [Figure 14] to perform the reset functions) to bring the IP block (Figure 1, item 160; see also Figure 14, items FB) out of reset before bringing the one or more cores (Figure 1, items 112a; see also Figure 14, item 420) out of reset (Figure 1, Column 12, lines 47-52 and Column 13, lines 19-23; i.e., item 120 can cause the IP block 160 to reset [which would include bringing it out of reset as required by the claim] before the processor cores 112a are reset; as shown in Figure 14, this functionality can be performed by a combination of items 425/440/460 [equivalent to the claimed “clock controller”], which together detect an abnormality in a clock signal and in response reset the various components in the integrated circuit 410, see Column 14, lines 53-58 and Column 15, lines 1-13).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Kim’s teachings of processor communications in an integrated circuit with the teachings of Swarbrick, for the purpose of allowing the circuit to function again in the event of an abnormality or failure by resetting all of the components after such an event.
Regarding Claims 2 and 15, Capalija teaches wherein at least one of the one or more cores is an x86 core (paragraph 0013; i.e., although the reference does not explicitly state that the CPUs have an x86 core, using the x86 architecture is well known in the art and it would have been obvious to one of ordinary skill in the art to have used it for the purpose of providing extensive software compatibility and legacy support; x86 processors have been the dominant choice for personal computers and servers for decades, resulting in a massive and diverse ecosystem of software applications, operating systems, and development tools; this legacy makes it easy to find pre-existing software and ensures that older software will still run on modern x86 systems).
Regarding Claims 3 and 16, Swarbrick discloses wherein the open-standard protocol is an Advanced Microcontroller Bus Architecture (AMBA) protocol (paragraph 0019; i.e., AXI is part of the AMBA protocol).
Regarding Claims 4 and 17, Swarbrick discloses wherein the at least one port of the first type includes circuitry to convert between messages according to the proprietary protocol and packets according to a packet protocol of the NoC (paragraph 0023).
Regarding Claims 5 and 18, Swarbrick discloses wherein the at least one port of the second type includes circuitry to convert between messages according to the open-source protocol and packets according to the packet protocol of the NoC (paragraph 0023).
Regarding Claim 8, Swarbrick discloses wherein the design is a register transfer level design or is in a hardware description language (paragraph 0042; i.e., although RTL and HDL are not mentioned in the reference, it is well known in the art that they are commonly used to program an FPGA for the purpose of providing the ability to describe hardware behavior at a high level of abstraction which allows for faster design cycles, easier verification, and greater flexibility in adapting designs to different technologies).
Regarding Claim 9, Swarbrick discloses a reset unit to control reset (i.e., rebooting) of the one or more cores (paragraphs 0015 and 0030).
Regarding Claim 12, Swarbrick discloses the IP block (paragraph 0017).
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Swarbrick, Capalija, and Kim as applied to claim 5 above, and further in view of Sindhu et al. (U.S. Patent Application Publication Number 2019/0013965).
Regarding Claim 6, Swarbrick, Capalija, and Kim do not expressly disclose a non-coherent unit connected to a port of the first type to handle x86-specific system functionality.
In the same field of endeavor (e.g., processor communications over a NoC), Sindhu teaches a non-coherent unit connected to a port of the first type to handle x86-specific system functionality (paragraph 0122).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Sindhu’s teachings of processor communications over a NoC with the teachings of Swarbrick, Capalija, and Kim, for the purpose of offering a trade-off between performance and simplicity since it allows for a faster system, with potentially greater flexibility for the software, than a fully coherent system, but it comes with the added burden of software managing coherence.
Regarding Claim 7, Sindhu teaches an interrupt and timer unit to handle interrupts and provide timer functionality (paragraphs 0141 and 0164).
Claims 10 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Swarbrick, Capalija, and Kim as applied to claim 5 above, and further in view of Rabeela et al. (U.S. Patent Application Publication Number 2014/0173093).
Regarding Claim 10, Swarbrick, Capalija, and Kim do not expressly disclose a system controller to convert messages between the proprietary protocol and a sideband protocol.
In the same field of endeavor (e.g., processor communications over a NoC), Rabeela teaches a system controller to convert messages between the proprietary protocol (Figure 5, item 512, paragraph 0024) and a sideband protocol (Figure 5, item 572, paragraph 0026).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Rabeela’s teachings of processor communications over a NoC with the teachings of Swarbrick, Capalija, and Kim, for the purpose of allowing for the integration of devices or systems using different communication standards, ensuring compatibility and facilitating data exchange across various platforms.
Regarding Claim 13, Rabeela teaches a power management unit connected to a port of the second type (Figure 1, item 120, paragraph 0012; i.e., management controller 120 manages power).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Swarbrick, Capalija, and Kim as applied to claim 5 above, and further in view of Menon et al. (U.S. Patent Application Publication Number 2016/0077905).
Regarding Claim 11, Swarbrick, Capalija, and Kim do not expressly disclose an interface, and wherein a prototype of the design is to include a representation of the interface, and wherein the prototype is to be bootable from a basic input/output system (BIOS) connected to the prototype through the representation of the interface.
In the same field of endeavor (e.g., processor communications over a NoC), Menon teaches an interface, and wherein a prototype of the design is to include a representation of the interface, and wherein the prototype is to be bootable from a basic input/output system (BIOS) connected to the prototype through the representation of the interface (paragraph 0038).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Menon’s teachings of processor communications over a NoC with the teachings of Swarbrick, Capalija, and Kim, for the purpose of ensuring that the design operates properly before manufacturing the device.
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Swarbrick, Capalija, Kim, and Menon.
Regarding Claim 19, Swarbrick discloses a method comprising:
generating, from a design (paragraph 0042) stored on a machine-readable medium, the apparatus including one or more cores (Figure 1, item 110A, paragraph 0017; i.e., a processor contains at least one core), and an intellectual property (IP) block (paragraph 0017; i.e., IP blocks commonly take the form of processors or digital signal processing blocks), and a network-on-chip (NoC) (Figure 1, item 105) having at least one port of a first type (Figure 1, item 115 connected to logic block 110A) and at least one port of a second type (Figure 1, item 115 connected to logic block 110B), wherein the first type is to communicate with the one or more cores according to a first protocol and the second type is to communicate with an the IP block according to an open-standard protocol (paragraph 0022; i.e., the two ingress logic blocks 115 can each be programmed to operate according to two different protocols [including AXI, which is an open-standard protocol - paragraph 0019] at the same time).
Swarbrick does not expressly disclose the first protocol is a proprietary protocol (although does state that any protocol can be used to facilitate communication between the logic blocks and NoC - paragraph 0019);
a clock controller to bring the IP block out of reset before bringing the one or more cores out of reset.
a prototype of the design for an apparatus;
booting the prototype; and
testing the prototype.
In the same field of endeavor (e.g., processor communications over a NoC), Capalija teaches a port is to communicate with one or more cores according to a proprietary protocol (paragraphs 0013 and 0027).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Capalija’s teachings of processor communications over a NoC with the teachings of Swarbrick, for the purpose of allowing for specialized, optimized communication and control between system components which can lead to increased efficiency, reduced complexity, and potentially higher performance in specific applications.
Also in the same field of endeavor (e.g., processor communications in an integrated circuit), Kim teaches a clock controller (Figure 1, item 120; i.e., item 120 can work with other components 440 and 460 [Figure 14] to perform the reset functions) to bring the IP block (Figure 1, item 160; see also Figure 14, items FB) out of reset before bringing the one or more cores (Figure 1, items 112a; see also Figure 14, item 420) out of reset (Figure 1, Column 12, lines 47-52 and Column 13, lines 19-23; i.e., item 120 can cause the IP block 160 to reset [which would include bringing it out of reset as required by the claim] before the processor cores 112a are reset; as shown in Figure 14, this functionality can be performed by a combination of items 425/440/460 [equivalent to the claimed “clock controller”], which together detect an abnormality in a clock signal and in response reset the various components in the integrated circuit 410, see Column 14, lines 53-58 and Column 15, lines 1-13).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Kim’s teachings of processor communications in an integrated circuit with the teachings of Swarbrick, for the purpose of allowing the circuit to function again in the event of an abnormality or failure by resetting all of the components after such an event.
Also in the same field of endeavor (e.g., processor communications over a NoC), Menon teaches a prototype of the design for an apparatus (paragraph 0038);
booting the prototype (paragraph 0039); and
testing the prototype (paragraph 0037).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Menon’s teachings of processor communications over a NoC with the teachings of Swarbrick, for the purpose of ensuring that the design operates properly before manufacturing the device.
Regarding Claim 20, Swarbrick discloses manufacturing the apparatus from the design (paragraph 0042).
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL M ZAMAN whose telephone number is (571)272-6495. The examiner can normally be reached Monday - Friday, 8 am - 5 pm, alternate Fridays.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kim Huynh can be reached at 571-272-4147. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175