DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 12, 17, and 19 have been amended.
Claim 11 has been cancelled.
Claims 1-10 and 12-20 have been examined.
Information Disclosure Statement
The applicant's submission of the Information Disclosure Statement dated July 24, 2025 is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. A copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 and 12-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites, at lines 9-11, “dynamically switch between creating the slice from one or more of the plurality of chunks and creating the slice from only one of the plurality of chunks.” This limitation covers the case of dynamically switching from creating the slice from one of the plurality of chunks to creating the slice from one of the plurality of chunks. This language is indefinite as it cannot be determined what is involved in such a switch. For purposes of examination, the limitation is interpreted as, “dynamically switch between creating the slice from [[one]] two or more of the plurality of chunks and creating the slice from only one of the plurality of chunks.” Claims 17 and 19 have similar language and are similarly rejected.
Claims 2-10, 12-16, 18, and 20 are rejected as depending from rejected base claims and failing to cure the indefiniteness of those base claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10, 12, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication No. 2018/0088596 by Combs (hereinafter referred to as “Combs”) in view of US Publication No. 2009/0019263 by Shen et al. (hereinafter referred to as “Shen”).
Regarding claim 1, Combs discloses:
an apparatus comprising: a decode cluster including a plurality of instruction decoders (Combs discloses, at Figure 22 and related description, a processor core having two decode clusters that each have two decoders.); and
chunk steering circuitry to: break a sequence of instruction bytes into a plurality of chunks (Combs discloses, at Figure 22 and related description, a cluster balancer that distributes chunks of instructions to the decode clusters. See also Figure 27 and related description, which disclose directing subsets of a stream of instructions to the decode clusters.),
create a slice from one or more of the plurality of chunks…, wherein the slice …includes a plurality of instructions and wherein the chunk steering circuitry is to dynamically switch between creating the slice from one or more of the plurality of chunks and creating the slice from only one of the plurality of chunks (Combs discloses, at ¶ [0223], a cluster decoding one or more elements a time, the elements corresponding to a plurality of instructions, which discloses creating a slice from one or more of the chunks, the slice having a plurality of instructions. Combs also discloses, at ¶ [0240], instructions sometimes cross cache line boundaries, which discloses creating a slice from a single chunk and from multiple chunks, i.e., dynamically switching between the two.), and
steer the slice to the decode cluster (Combs discloses, at Figure 27 and related description, directing the subsets of data elements to the decode clusters.).
Combs does not explicitly disclose the aforementioned creating a slice is based on one or more indications of a number of instructions in each of the one or more of the plurality of chunks and that the aforementioned slice has a variable size.
However, in the same field of endeavor (e.g., decoding) Shen discloses:
obtaining instructions from a scan window, the instructions having variable size (Shen discloses, at Figure 5B and related description, obtaining variable length instructions, which discloses being based on a number of the instructions, from a scan window and providing the variable length instructions to a decoder. See also Figure 6 and related description, which discloses steering instructions from a fetch packet to several instructions decoders.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Combs to include formation of variable sized slices based on numbers of instructions in order to efficiently and correctly decode in systems that use variable length instructions. See, e.g., Shen, ¶ [0004] et seq.
Regarding claim 2, Combs, as modified, discloses the elements of claim 1, as discussed above. Combs does not explicitly disclose each of the plurality of chunks has a fixed size, wherein the fixed size of each chunk is equal to the fixed size of every other chunk.
However, in the same field of endeavor (e.g., decoding) Shen discloses:
a scan window of predetermined size (Shen discloses, at ¶ [0022] et seq., a scan window of fixed size, which discloses a fixed size equal to the fixed size of every other scan window.)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Combs to include fixed size chunks because doing so simplifies operation of the processor.
Regarding claim 3, Combs, as modified, discloses the elements of claim 1, as discussed above. Combs also discloses:
the decode cluster also includes instruction steering circuitry to steer a first one of the plurality of instructions to a first one of the plurality of instruction decoders and to steer a second one of the plurality of instructions to a second one of the plurality of instruction decoders (Combs discloses, at Figure 22 and related description, decode clusters having multiple decoders that operate in parallel. This implicitly discloses instruction steering circuitry to steer instructions to the respective decoders.).
Regarding claim 4, Combs, as modified, discloses the elements of claim 3, as discussed above. Combs also discloses:
…a cluster chunk queue to receive …[instructions] from the chunk steering circuitry and to store the …[instructions] for instruction steering by the instruction steering circuitry (Combs discloses, at Figure 22 and related description, prefetch buffers that store instructions to be decoded.).
Combs does not explicitly disclose that the aforementioned cluster chunk queue is included in the decode cluster and stores the slice. However, it would have been obvious to modify Combs to include the prefetch buffer within the cluster and to store the slice. The particular location of the buffer is an obvious design choice.
Regarding claim 5, Combs, as modified, discloses the elements of claim 4, as discussed above. Combs also discloses:
the instruction steering circuitry is to provide up to one instruction per clock cycle to each of the plurality of instruction decoders (Combs discloses, at ¶ [0198], providing up to four instructions per cycle, which is one per cycle to each of the four decoders present in the illustrated example implementation.).
Regarding claim 6, Combs, as modified, discloses the elements of claim 1, as discussed above. Combs also discloses:
the decode cluster is one of a plurality of decode clusters, and the chunk steering circuitry is to: create a plurality of slices from the plurality of chunks, and steer each of the plurality of slices to a corresponding decode cluster of the plurality of decode clusters (Combs discloses, at Figure 22 and related description, a cluster balancer that distributes chunks of instructions to the decode clusters.).
Regarding claim 7, Combs, as modified, discloses the elements of claim 6, as discussed above. Combs also discloses:
the chunk steering circuitry is steer each of the plurality of slices to the corresponding decode cluster in round robin fashion (Combs discloses, at Figure 22 and related description, a cluster balancer that distributes chunks of instructions to the decode clusters. As disclosed at ¶ [0188], the balancer may use round robin assignment.).
Regarding claim 8, Combs, as modified, discloses the elements of claim 8, as discussed above. Combs also discloses:
each of the plurality of decode clusters includes: a plurality of instruction decoders, and instruction steering circuitry to steer each instruction of one of the plurality of slices to a corresponding one of the plurality of instruction decoders (Combs discloses, at Figure 22 and related description, decode clusters having multiple decoders that operate in parallel. This implicitly discloses instruction steering circuitry to steer instructions to the respective decoders.).
Regarding claim 9, Combs, as modified, discloses the elements of claim 1, as discussed above. Combs also discloses:
instruction fetch circuitry to provide the sequence of instruction bytes to the instruction steering circuitry (Combs discloses, at Figure 22 and related description, fetching instructions into prefetch buffers, which discloses fetch circuitry to provide the instruction bytes to instruction steering circuitry.).
Regarding claim 10, Combs, as modified, discloses the elements of claim 9, as discussed above. Combs also discloses:
the sequence of instruction bytes is one of a plurality of sequences of instruction bytes to be provided by the instruction fetch circuitry, wherein each of the plurality of sequences of instruction bytes is to include up to a fixed number of cache lines (Combs discloses, at ¶ [0170] et seq., the fetch circuitry fetches instruction streams. As disclosed at ¶ [0187], the streams may be raw cache lines, which implicitly discloses a fixed upper limit.).
Regarding claim 12, Combs, as modified, discloses the elements of claim 10, as discussed above. Combs also discloses:
the chunk steering circuitry is to dynamically switch based on a timing constraint (Combs discloses, at ¶ [0240], instructions sometimes cross cache line boundaries. Cache line size is based on timing constraints, meaning the aforementioned switching is likewise based on timing constraints.).
Regarding claim 17, Combs discloses:
a method comprising: breaking a sequence of instruction bytes into a plurality of chunks (Combs discloses, at Figure 22 and related description, a cluster balancer that distributes chunks of instructions to the decode clusters. See also Figure 27 and related description, which disclose directing subsets of a stream of instructions to the decode clusters.),
creating a slice from a one or more of the plurality of chunks …wherein the slice has …includes a plurality of instructions and wherein the chunk steering circuitry is to dynamically switch between creating the slice from one or more of the plurality of chunks and creating the slice from only one of the plurality of chunks (Combs discloses, at ¶ [0223], a cluster decoding one or more elements a time, the elements corresponding to a plurality of instructions, which discloses creating a slice from one or more of the chunks, the slice having a plurality of instructions. Combs also discloses, at ¶ [0240], instructions sometimes cross cache line boundaries, which discloses creating a slice from a single chunk and from multiple chunks, i.e., dynamically switching between the two.), and
steering the slice to the decode cluster, wherein the decode cluster includes a plurality of instruction decoders (Combs discloses, at Figure 27 and related description, directing the subsets of data elements to the decode clusters.).
Combs does not explicitly disclose the aforementioned creating a slice is based on one or more indications of a number of instructions in each of the one or more of the plurality of chunks and that the aforementioned slice has a variable size.
However, in the same field of endeavor (e.g., decoding) Shen discloses:
obtaining instructions from a scan window, the instructions having variable size (Shen discloses, at Figure 5B and related description, obtaining variable length instructions, which discloses being based on a number of the instructions, from a scan window and providing the variable length instructions to a decoder. See also Figure 6 and related description, which discloses steering instructions from a fetch packet to several instructions decoders.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Combs to include formation of variable sized slices based on numbers of instructions in order to efficiently and correctly decode in systems that use variable length instructions. See, e.g., Shen, ¶ [0004] et seq.
Regarding claim 18, Combs, as modified, discloses the elements of claim 17, as discussed above. Combs also discloses:
writing the slice to a cluster chunk queue (Combs discloses, at Figure 22 and related description, prefetch buffers that store instructions to be decoded, which discloses writing.),
reading the slice from the cluster chunk queue (Combs discloses, at Figure 22 and related description, prefetch buffers that store instructions to be decoded, which discloses reading.), and
steering a first one of the plurality of instructions to a first one of the plurality of instruction decoders and to steer a second one of the plurality of instructions to a second one of the plurality of instruction decoders (Combs discloses, at Figure 22 and related description, decode clusters having multiple decoders that operate in parallel. This implicitly discloses instruction steering circuitry to steer instructions to the respective decoders.).
Regarding claim 19, Combs discloses:
a system comprising: a plurality of processor cores, wherein at least one of the processor cores includes (Combs discloses, at Figure 5A and related description, a system with multiple cores.):
a cache to store a sequence of instruction bytes (Combs discloses, at Figure 22 and related description, and instruction cache.);
a decode cluster including a plurality of instruction decoders (Combs discloses, at Figure 22 and related description, a decode cluster that includes a plurality of decoders.); and
chunk steering circuitry to: break the sequence of instruction bytes into a plurality of chunks (Combs discloses, at Figure 22 and related description, a cluster balancer that distributes chunks of instructions to the decode clusters. See also Figure 27 and related description, which disclose directing subsets of a stream of instructions to the decode clusters.),
create a slice from a one or more of the plurality of chunks … wherein the slice …includes a plurality of instructions and wherein the chunk steering circuitry is to dynamically switch between creating the slice from one or more of the plurality of chunks and creating the slice from only one of the plurality of chunks (Combs discloses, at ¶ [0223], a cluster decoding one or more elements a time, the elements corresponding to a plurality of instructions, which discloses creating a slice from one or more of the chunks, the slice having a plurality of instructions. Combs also discloses, at ¶ [0240], instructions sometimes cross cache line boundaries, which discloses creating a slice from a single chunk and from multiple chunks, i.e., dynamically switching between the two.), and
steer the slice to the decode cluster (Combs discloses, at Figure 27 and related description, directing the subsets of data elements to the decode clusters.); and
a memory controller to provide the sequence of instruction bytes to the cache from a dynamic random-access memory (DRAM) (Combs discloses, at Figure 5A and related description, a memory controller. As disclosed at Figure 6 and related description, the memory can be DRAM.).
Combs does not explicitly disclose the aforementioned creating a slice is based on one or more indications of a number of instructions in each of the one or more of the plurality of chunks and that the aforementioned slice has a variable size.
However, in the same field of endeavor (e.g., decoding) Shen discloses:
obtaining instructions from a scan window, the instructions having variable size (Shen discloses, at Figure 5B and related description, obtaining variable length instructions, which discloses being based on a number of the instructions, from a scan window and providing the variable length instructions to a decoder. See also Figure 6 and related description, which discloses steering instructions from a fetch packet to several instructions decoders.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Combs to include formation of variable sized slices based on numbers of instructions in order to efficiently and correctly decode in systems that use variable length instructions. See, e.g., Shen, ¶ [0004] et seq.
Regarding claim 20, Combs, as modified, discloses the elements of claim 19, as discussed above. Combs also discloses:
the DRAM (Combs discloses, at Figure 6 and related description, the system can include DRAM.).
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Combs in view of Shen in view of US Patent No. 6,212,621 by Mahalingaiah (hereinafter referred to as “Mahalingaiah”).
Regarding claim 13, Combs, as modified, discloses the elements of claim 1, as discussed above. Combs does not explicitly disclose the one or more indications of a number of instructions in each of the one or more of the plurality of chunks includes one or more end-of-instruction markers.
However, in the same field of endeavor (e.g., decoding) Mahalingaiah discloses:
end bits that indicate boundaries of instructions (Mahalingaiah discloses, at col. 5, lines 11-16, end bits, which discloses indications of a number of instructions.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Combs to include using end bits, as disclosed by Mahalingaiah, because doing so is a simple way to expedite the relatively complex task of decoding variable length instructions. See Mahalingiah, columns 1-2.
Regarding claim 14, Combs, as modified, discloses the elements of claim 13, as discussed above. Combs does not explicitly disclose creating the slice is to include counting end-of- instruction markers.
However, in the same field of endeavor (e.g., decoding) Mahalingaiah discloses:
counting instructions (Mahalingaiah discloses, at col. 10, lines 60-65, counting instructions.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Combs to include counting instructions, as disclosed by Mahalingaiah, in order to facilitate out of order instruction execution. Id.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Combs in view of Shen in view of US Patent No. 6,175,908 by Pickett (hereinafter referred to as “Pickett”)
Regarding claim 15, Combs, as modified, discloses the elements of claim 1, as discussed above. Combs does not explicitly disclose creating the slice is to include masking instruction bytes between a branch instruction and a target of the branch instruction.
However, in the same field of endeavor (e.g., decoding) Pickett discloses:
ignoring bytes following a branch instruction (Pickett discloses, at col. 13, lines 19-22, ignoring bytes subsequent to a branch.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Combs to include skipping bytes following a branch, as disclosed by Pickett, in order to avoid decoding branches unnecessarily.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Combs in view of Shen in view of US Patent No. 6,175,908 by Madduri et al. (hereinafter referred to as “Madduri”).
Regarding claim 16, Combs, as modified, discloses the elements of claim 1, as discussed above. Combs does not explicitly disclose creating the slice is to include: creating a pre-slice including a fixed number of instructions, and splitting the pre-slice based on a number of chunks in the pre-slice.
However, in the same field of endeavor (e.g., decoding) Madduri discloses:
dividing a group of instructions based on chunks (Madduri discloses, at ¶ [0074], dividing instructions by how many chunks are in the group.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Combs to include dividing groups of instructions, as disclosed by Madduri, in order to facilitate efficiently decoding variable length instructions.
Response to Arguments
On page 6 of the response filed July 22, 2025 (“response”), the Applicant argues, “As noted in MPEP 707.07(d), "[t]he examiner should, as a part of the first Office action on the merits, identify any claims which he or she judges, as presently recited, to be allowable and/or should suggest any way in which he or she considers that rejected claims may be amended to make them allowable." As this was not done in the first Office action on the merits, the Applicant respectfully requests suggestions regarding allowability including claim amendment suggestions in any subsequent action. Providing prescribed guidance is in the interest of compact prosecution.”
Though fully considered, the Examiner respectfully disagrees. It is not at present apparent which part of the application could serve as a basis for a new, allowable claim.
On pages 6-7 of the response the Applicant argues, “independent claim 1, as amended, requires the chunk steering circuitry to dynamically switch between creating the slice from one or more of the plurality of chunks and creating the slice from only one of the plurality of chunks. Each of the other pending claims, by amendment or dependence, include a corresponding limitation. It is respectfully submitted that this limitation is not disclosed by Combs, despite the rejection of claim 11, at least because Combs description, in paragraph 0024, of reads crossing cache line boundaries does not mean that the chunk steering circuitry dynamically switches between creating the slice from one or more of the plurality of chunks and creating the slice from only one of the plurality of chunks.”
Though fully considered, the Examiner respectfully disagrees. The arguments state that reads crossing cache lines does not disclose dynamically switching between using multiple chunks and using a single chunk. The arguments provide no support, basis or rational for this position.
Combs discloses using both a single cache line, equated with using one chunk and using multiple cache lines, equated with using multiple chunks. See, e.g., ¶ [0240]. Disclosure of the ability to read from a single line and from multiple lines discloses dynamically switching between using a single chunk and two or more chunks. Accordingly, the Applicant’s arguments are deemed unpersuasive.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/
Primary Examiner, Art Unit 2183