Prosecution Insights
Last updated: May 29, 2026
Application No. 17/712,547

LIGHT EMITTING DEVICE AND OPTICAL MEASUREMENT APPARATUS

Non-Final OA §103
Filed
Apr 04, 2022
Priority
Sep 14, 2021 — JP 2021-149244 +1 more
Examiner
RICHTER, KARA MARIE
Art Unit
3645
Tech Center
3600 — Transportation & Electronic Commerce
Assignee
Fujifilm Business Innovation Corp.
OA Round
3 (Non-Final)
69%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 69% — above average
69%
Career Allowance Rate
11 granted / 16 resolved
+16.8% vs TC avg
Strong +38% interview lift
Without
With
+38.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 11m
Avg Prosecution
28 currently pending
Career history
60
Total Applications
across all art units

Statute-Specific Performance

§103
93.7%
+53.7% vs TC avg
§102
2.1%
-37.9% vs TC avg
§112
4.2%
-35.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 16 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Information Disclosure Statement The information disclosure statements (IDS) submitted by the applicant and listed below have been considered and are included in the file. 24 September 2025 Response to Amendment Claims 1-4, 6-7, 9-13, 15-16, 18, and 20-21 are currently pending. Independent claim(s) 1, 9 and 16 and dependent claims 6-7 and 20 have been amended and claim 21 newly added by applicant’s amendments received 16 March 2026. No new matter has been introduced. Claims 5, 14 and 19 have been canceled, and therefore the prior rejections is/are moot. Response to Arguments Applicant’s arguments, see pgs. 7-8 of Remarks, filed 16 March 2026, with respect to the rejection(s) of claim(s) 1-4, 9, 16 and 18 under 35 U.S.C. 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of a newly found prior art reference, in response to the amendments filed. Regarding claims 1, 9 and 16 applicant cites that the cited art Kondo (JP 6369613) fails to anticipate or make obvious the newly added limitations “wherein the signal line does not supply a current for causing the light emitting elements to emit light”, and “the oxide film is formed continuously along the first direction”. Additionally, the applicant notes that in view of these newly added limitations that the connection wiring (76) of Kondo equates to the signal line as claimed, as light up signal line (75) applies a current. This is persuasive, and so the prior rejections under Kondo have been withdrawn, however after search and consideration of these new limitations, new art has been found as is applied below. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-4, 6-7, 9, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki (US 20140034982 A1), and in view of Nakanishi (US 20210088928 A1). Regarding claims 1 and 9, as an oxide film acts as an insulator, Yamazaki teaches a light emitting device, comprising a semiconductor substrate (Figs 1A, 1B, 11A, 11B; substrate (100)); a light-emitting-element section formed on the semiconductor substrate and including a plurality of light emitting elements that radiate light ([0177] - [0179]; Fig. 8 which shows a pixel portion (120), which has multiple light-emitting pixels (253)); a signal line that is formed along a first direction on the semiconductor substrate and that transmits a signal to the light emitting elements ([0177] - [0179], [0253]), wherein the signal line does not supply a current for causing the light emitting elements to emit light ([0183], [0199] - [0212]; Figs. 11A, B where signal line (272) is separate from power line (273)); and an oxide film (insulator) formed between the signal line and the semiconductor substrate along an extension direction of the signal line ([0199] - [0212]), wherein and the oxide film (insulator) is formed continuously between the signal line and the semiconductor substrate over an entire region where the signal line is formed ([0199] - [0212]; Figs. 11A, B where insulating layer (oxide film) (102) occurs continuously above substrate (100) and below signal lines (272)). Yamazaki does not inherently teach that the light-emitting-element section includes a plurality of areas. Nakanishi teaches a light-emitting-element section includes a plurality of areas, and the light emitting elements are connected to the signal line in each of the plurality of areas ([0147] - [0150]; Figs. 3, 17A where element array chips (C1 to C29) each are formed as light emitting device (100) and connected via connector (270)). To one of ordinary skill in the art before the effective filing date of the claimed invention, it would have been obvious prima facie to modify Yamazaki to incorporate the teachings of Nakanishi to combine multiple light emitting sections (pixel portions), where each pixel portion has a plurality of emitting elements as taught by Yamazaki, with a reasonable expectation of success of creation of an emitter array, which is grouped into subsects of emitters. The light emitting device of Yamazaki is similar to the light emitting device taught by Nakanishi ([0037]; Fig. 2A, 2B, emitter (100)) which has a plurality of emitters on a semiconductor substrate, where the emitters are thyristors. Additionally, Yamazaki teaches use of the pixel portion within larger device arrays (Figs. 24A-E), and so the combination would have predictable results of forming a larger emitter array with separate groups of pixels/emitters. Regarding claim 2, Yamazaki as modified above teaches the light emitting device according to Claim 1, wherein the signal line transmits a signal from a terminal disposed in the semiconductor substrate to the light- emitting-element section ([0178] - [0179], [0201]; where the signal lines can occur in channel formations within the semiconductor layers). Regarding claim 3, Yamazaki as modified above teaches the light emitting device according to Claim 2, wherein a signal for causing the light emitting elements to emit light is transmitted from the terminal to the signal line ([0177] - [0179], [0281]). Regarding claim 4, Yamazaki as modified above teaches the light emitting device according to Claim 3, wherein the signal line has a same potential regardless of distances from the light emitting elements ([0194]; where the system may set the potential of the signal lines to a specific value). Regarding claim 6, Yamazaki as modified above teaches the light emitting device according to Claim 1, where a signal line is arranged along the row of LED emitters ([0177] - [0179], [0253]; Fig. 8), Yamazaki fails to teach the signal line is aligned between a plurality of areas, where each area is made up of a plurality of light emitting elements that radiate light. Nakanishi teaches a signal line which can be arranged between the areas ([0043] - [0048], [0147]; Figs. 3, 17A-C, where element array chips (C1-C29) are formed as device (100) of Fig. 3, and could be oriented so that lighting signal lines (80, 82, 84, 86) are aligned between element sections). To one of ordinary skill in the art before the effective filing date of the claimed invention, it would have been obvious prima facie to modify Yamazaki to incorporate the teachings of Nakanishi to combine multiple emitter devices, where each device has a plurality of emitting elements as taught by Yamazaki, with a reasonable expectation of success of creation of an emitter array with connective signal wiring aligned between the groups of emitters. Arrangement of the light emitting devices of Nakanishi (Fig. 17A, C1 to C29) so that the signal lines of each semiconductor light emitting device (Fig. 3, (100)) are aligned between element sections would not have modified the operation of the device of Fig. 17A, and therefore would be a predictable rearrangement of parts. Regarding claim 7, Yamazaki as modified above teaches the light emitting device according to Claim 1, wherein a width of the signal line in a short-side direction is smaller than a width of each of the areas in plan view ([0199] - [0212]; Figs. 11A, 11B where signal line (272) is narrower than width of one pixel, and therefore would be narrower than an area which includes a plurality of pixels). Regarding claim 21, Yamazaki as modified above teaches the light emitting device according to Claim 1, further comprising an anode electrode to which the current for causing the light emitting elements to emit light is supplied, wherein the signal line is a wiring different from a wiring connected to the anode electrode ([0149]; Fig. 1A, 1B where pixel electrode (106) may serve as a cathode or anode and supplies power to the light-emitting device). Claim(s) 10-13 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki (US 20140034982 A1), in view of Nakanishi (US 20210088928 A1) and further in view of Shimada et al. (hereinafter Shimada, US 20240213281 A1). Regarding claim 10, Yamazaki as modified above teaches the light emitting device according to Claim 1. Yamazaki fails to teach an optical measurement apparatus which includes a light receiver or a measurer to determine distance. Shimada teaches a distance measuring system, where a light receiver receives light emitted from the light emitting device and reflected by an object ([0267] - [0269]; Fig. 32, receiver (652)) and a measurer that measures a distance to the object based on a flight distance of light emitted from the light emitting device and received by the light receiver ([0269] - [0270]; Fig. 32, signal processing circuit (653)). To one of ordinary skill in the art before the effective filing date of the claimed invention, it would have been obvious prima facie to incorporate the emitter device of Yamazaki as modified by Nakanishi into a distance measurement system as taught by Shimada with a reasonable expectation of success. Shimada notes that the type of laser source within their system can be arbitrarily set to align with the application of the distance measuring system ([0265]). This would incorporate the emitter array of Yamazaki as modified by Nakanishi with predictable results where a distance measuring system emits light and the reflected light is received by the system, such that a time-of-flight distance measurement is obtained between the system and an object in the environment. Claim 11 is similarly rejected to claim 10. Claim 12 is similarly rejected to claim 10. Claim 13 is similarly rejected to claim 10. Claim 15 is similarly rejected to claim 14. Claim(s) 16, 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki (US 20140034982 A1), in view of Nakanishi (US 20210088928 A1) and further in view of Kondo (JP 6369613). Regarding claim 16, Yamazaki teaches a light emitting device, comprising a semiconductor substrate (Figs 1A, 1B, 11A, 11B; substrate (100)); a light-emitting-element section formed on the semiconductor substrate and including a plurality of light emitting elements that radiate light ([0177] - [0179]; Fig. 8 which shows a pixel portion (120), which has multiple light-emitting pixels (253)); a signal line that is formed along a first direction on the semiconductor substrate and that transmits a signal to the light emitting elements ([0177] - [0179], [0253]), wherein the signal line does not supply a current for causing the light emitting elements to emit light ([0183], [0199] - [0212]; Figs. 11A, B where signal line (272) is separate from power line (273)); and an oxide film (insulating layer) formed between the signal line and the semiconductor substrate along an extension direction of the signal line ([0199] - [0212]), wherein and the oxide film (insulator) is formed continuously between the signal line and the semiconductor substrate over an entire region where the signal line is formed ([0199] - [0212]; Figs. 11A, B where insulating layer (oxide film) (102) occurs continuously above substrate (100) and below signal lines (272)). Yamazaki does not inherently teach that the light-emitting-element section includes a plurality of areas, or a resistor in the circuit. Nakanishi teaches a light-emitting-element section includes a plurality of areas, and the light emitting elements are connected to the signal line in each of the plurality of areas ([0147] - [0150]; Figs. 3, 17A where element array chips (C1 to C29) each are formed as light emitting device (100) and connected via connector (270)). Kondo teaches a resistor that limits a current to the light emitting elements ([0032] - [0034], [0054]; Figs. 5,6 where light-emitting chip (C1) has resistors (Rg1) to (Rg128)); To one of ordinary skill in the art before the effective filing date of the claimed invention, it would have been obvious prima facie to modify Yamazaki to incorporate the teachings of Nakanishi to combine multiple light emitting sections (pixel portions), where each pixel portion has a plurality of emitting elements as taught by Yamazaki, and to incorporate the teachings of Kondo to explicitly include a resistor within the circuit, with a reasonable expectation of success of creation of an emitter array, which is grouped into subsects of emitters, with the currents controlled. The light emitting device of Yamazaki is similar to the light emitting device taught by Nakanishi ([0037]; Fig. 2A, 2B, emitter (100)) which has a plurality of emitters on a semiconductor substrate, where the emitters are thyristors. Yamazaki teaches use of the pixel portion within larger device arrays (Figs. 24A-E), and so the combination would have predictable results of forming a larger emitter array with separate groups of pixels/emitters. Additionally, Yamazaki notes that the system already inherently includes taking resistance of components into account ([0074]), and as resistors are well known circuit components, integration would have the predictable result of specifically controlling the current at points within the emitter array. Regarding claim 18, Yamazaki as modified above teaches the light emitting device according to Claim 16, wherein the insulating layer is further formed in a predetermined region around the region of the resistor ([0231] - [0329]; Figs. 9, 11A-B, 14, 15; wherein if the system as modified in claim 16 incorporates resistors within the circuits such as in Fig. 14, the resistors will be formed in the regions of the first transistor (261) and the second transistor (262) and therefore will be reasonably formed in an area with the insulating layer (102) underlying it). Regarding claim 20, Yamazaki as modified above teaches the light emitting device according to Claim 16, where a signal line is arranged along the row of LED emitters ([0177] - [0179], [0253]; Fig. 8), Yamazaki fails to teach the signal line is aligned between a plurality of areas, where each area is made up of a plurality of light emitting elements that radiate light. Nakanishi teaches a signal line which can be arranged between the areas ([0043] - [0048], [0147]; Figs. 3, 17A-C, where element array chips (C1-C29) are formed as device (100) of Fig. 3, and could be oriented so that lighting signal lines (80, 82, 84, 86) are aligned between element sections). To one of ordinary skill in the art before the effective filing date of the claimed invention, it would have been obvious prima facie to further modify Yamazaki and Kondo to incorporate the teachings of Nakanishi to combine multiple emitter devices, where each device has a plurality of emitting elements as taught by Yamazaki, with a reasonable expectation of success of creation of an emitter array with connective signal wiring aligned between the groups of emitters. Arrangement of the light emitting devices of Nakanishi (Fig. 17A, C1 to C29) so that the signal lines of each semiconductor light emitting device (Fig. 3, (100)) are aligned between element sections would not have modified the operation of the device of Fig. 17A, and therefore would be a predictable rearrangement of parts. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Anzaki et al. (US 5173759 A) teaches an array of light emitting devices or detectors, where the invention relates to an optical printer head using plural light emitting devices, or an image sensor or other array using plural photo detectors, and an apparatus for printing or reading using the array, method of manufacturing the array, and method of mounting the array. Lee et al. (US 12014509 B2) teaches an optical device with an emitter and receiver, where the emitter contains a plethora of light emitting units in element groups, which make up an array connected by a conductive circuit. Endo (US 20230005400 A1) teaches a light emitting apparatus, with an array of pixel includes current paths situated between the pixels all formed on a semiconductor substrate with an insulating layer. Fukutome (US 20180095336 A1) teaches a semiconductor device with an array, driver circuit, and use of oxide and insulating films within the device which may overlap with wiring. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kara Richter whose telephone number is (571)272-2763. The examiner can normally be reached Monday - Thursday, 8A-5P EST, Fridays are variable. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Helal Algahaim can be reached at (571) 270-5227. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /K.M.R./Examiner, Art Unit 3645 /HELAL A ALGAHAIM/SPE , Art Unit 3645
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Prosecution Timeline

Apr 04, 2022
Application Filed
Jul 08, 2025
Non-Final Rejection mailed — §103
Aug 25, 2025
Response Filed
Sep 16, 2025
Final Rejection mailed — §103
Mar 16, 2026
Request for Continued Examination
Mar 27, 2026
Response after Non-Final Action
May 05, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
69%
Grant Probability
99%
With Interview (+38.5%)
3y 11m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 16 resolved cases by this examiner. Grant probability derived from career allowance rate.

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