Prosecution Insights
Last updated: October 02, 2026
Application No. 17/712,738

SEMICONDUCTOR DEVICE WITH METAL SILICIDE LAYER

Non-Final OA §102
Filed
Apr 04, 2022
Examiner
ISAAC, STANETTA D
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Infineon Technologies AG
OA Round
4 (Non-Final)
86%
Grant Probability
Favorable
4-5
OA Rounds
0m
Est. Remaining
50%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
838 granted / 977 resolved
+17.8% vs TC avg
Minimal -36% lift
Without
With
+-36.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
39 currently pending
Career history
1027
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
50.9%
+10.9% vs TC avg
§102
44.3%
+4.3% vs TC avg
§112
4.3%
-35.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 977 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This office action is in response to the amendment filed on 5/11/26. Claims 1-16 and 21-24 are pending. Claims 21-24 are newly added. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 8-16 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Rodriguez Alvarez et al. (US Pub 2023/0005747, hereinafter referred to as “Alvarez”). Alvarez discloses the semiconductor method as claimed. See figures 1A-1C, and corresponding text, where Alvarez teaches, in claim 8, a method of manufacturing a semiconductor device, comprising: forming a first layer (12) over a silicon carbide (SiC) layer (101g), wherein: an electrical contact formation region of the first layer has a first surface distal the SiC layer and a second surface proximal the SiC layer, and the first layer comprises a metal; and performing a plurality of laser shots (18) on the first surface of the electrical contact formation region (101) of the first layer to form a metal silicide layer (16) from the metal of the first layer (12) and silicon of the SiC layer (101g), wherein: each laser shot of the plurality of laser shots comprises illuminating a section of the first surface with a laser pulse, each section of the first surface is illuminated via at least two laser shots of the plurality of laser shots; (figures 1A-1C; [0022-0033], examiner views that each region where there are recesses (13), damage (14), and roughness areas the illuminating section areas where plurality of shots are performed for each section) a first illumination area illuminated by a first laser shot of the plurality of laser shots overlaps a second illumination area illuminated by a second laser shot of the plurality of laser shots; (figures 1B and 1C; [0022-0033]) and at least one laser shot, of the plurality of laser shots, illuminates material of the first layer having a surface roughness. (figures 1B- 1C; [0023-0034]) Alvarez teaches, in claim 9, wherein: (figures 1A-1C; [0022-0033], examiner views that each region where there are recesses (13), damage (14), and roughness areas the illuminating section areas where plurality of shots are performed for each section) the plurality of laser shots comprise a third laser shot and a fourth laser shot, the third laser shot comprises illuminating a first section of the first surface with a first laser pulse, the fourth laser shot comprises illuminating the first section of the first surface with a second laser pulse, and a duration of time between the third laser shot and the fourth laser shot is at least a threshold duration of time. Alvarez teaches, in claim 10, wherein: (figures 1A-1C; [0022-0033], examiner views that each region where there are recesses (13), damage (14), and roughness areas the illuminating section areas where plurality of shots are performed for each section) the third laser shot melts metal of the first layer to form melted metal, the threshold duration of time is based upon a solidification time of the melted metal, and the melted metal solidifies prior to the fourth laser shot. Alvarez teaches, in claim 11, wherein: after the third laser shot and prior to the fourth laser shot, the first section of the first surface has a first surface roughness, and after the fourth laser shot, the first section of the first surface has a second surface roughness less than the first surface roughness. (figures 1A-1C; [0022-0033], examiner views that each region where there are recesses (13), damage (14), and roughness areas the illuminating section areas where plurality of shots are performed for each section) Alvarez teaches, in claim 12, wherein: (figures 1A-1C; [0022-0033], examiner views that each region where there are recesses (13), damage (14), and roughness areas the illuminating section areas where plurality of shots are performed for each section) a second section of the first surface, comprising the first section of the first surface, is illuminated with the first laser pulse, a third section of the first surface, comprising the first section of the first surface, is illuminated with the second laser pulse, the third section of the first surface is offset from the second section of the first surface, and the third section and the second section overlap at the first section. Alvarez teaches, in claim 13, comprising: (figures 1A-1C; [0022-0033], examiner views that each region where there are recesses (13), damage (14), and roughness areas the illuminating section areas where plurality of shots are performed for each section) after performing the plurality of laser shots, forming one or more metal layers over the metal silicide layer; and affixing a layer of the one or more metal layers to a lead frame (figure 3; [0038-0041]). Alvarez teaches, in claim 14, wherein: the first layer comprises silicon (figure 1A; [0022]). Alvarez teaches, in claim 15, wherein: the metal comprises nickel ([0026]). Alvarez teaches, in claim 16, wherein: the first layer is formed to have a thickness less than 200 nanometers ([0027]). Allowable Subject Matter Claims 1-7 and 21-24 are allowed over the prior art of record. The following is an examiner’s statement of reasons for allowance: The closest prior art of record and to the examiner’s knowledge does not suggest or render obvious a method of manufacturing a semiconductor device, particularly characterized by directing second thermal energy to the first surface of the metal silicide layer having the surface roughness to reduce the surface roughness of the first surface of the metal silicide layer, as detailed in claim 1. Claims 2-7 depend from claim 1. The closest prior art of record and to the examiner’s knowledge does not suggest or render obvious a method of manufacturing a semiconductor device, particularly characterized by directing second thermal energy to the first surface of the metal silicide layer having the surface roughness to reduce the surface roughness of the first surface of the metal silicide layer, as detailed in claim 21. Claims 22-24 depends from claim 1. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Response to Arguments Applicant’s arguments with respect to claim(s) 8-16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant’s amendment has necessitated new grounds of rejection. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STANETTA D ISAAC/Examiner, Art Unit 2898 July 29, 2026
Read full office action

Prosecution Timeline

Show 9 earlier events
Aug 12, 2025
Response after Non-Final Action
Sep 30, 2025
Request for Continued Examination
Oct 02, 2025
Response after Non-Final Action
Feb 25, 2026
Non-Final Rejection mailed — §102
May 06, 2026
Examiner Interview Summary
May 06, 2026
Applicant Interview (Telephonic)
May 11, 2026
Response Filed
Aug 20, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

4-5
Expected OA Rounds
86%
Grant Probability
50%
With Interview (-36.2%)
2y 5m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 977 resolved cases by this examiner. Grant probability derived from career allowance rate.

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