DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 1/5/2026 have been fully considered but they are not persuasive.
Applicant’s submission (Applicant’s Remarks pages 8-9) that the prior art of record does not teach the limitations of amended independent claims 13, 21, and 28 is acknowledged. However, the Examiner respectfully disagrees:
Regarding claim 13, US 20200373300 A1 (Zhang et al) is found to teach the amended limitation “forming a gate electrode around the first gate dielectric layer and the second gate dielectric layer while the first gate dielectric layer and the second gate dielectric layer remain present” because when the gate electrode of Zhang et al is formed (gate electrode 1306 in FIG. 13), the layers identified as the first gate dielectric layer and the second gate dielectric layer (layers 404 and 1002) are both still present in the device.
Regarding claims 21 and 28, US 20200373300 A1 (Zhang et al) teaches a gate-all-around device which either teaches the limitations of the amended claims, or the limitations are found obvious in view of other prior art documents of record (e.g. US 20170278743 A1 (Tsai et al) and US 20200105532 A1 (Liao et al)).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 13, 18, and 33 are rejected under 35 U.S.C. 103 as being unpatentable over US patent publications US 20200373300 A1 (Zhang et al hereinafter Zhang) in view of US 20170278743 A1 (Tsai et al hereinafter Tsai) and US 20100279515 A1 (Yu et al hereinafter Yu).
Regarding claim 13, Zhang discloses a method of forming a semiconductor device (a method for forming semiconductor structure 100), the method comprising: forming a channel region (FIG. 1A, channel layer 110 are formed ¶ [0039]) over a substrate (FIG. 1A, substrate 102 ¶ [0037]); forming an interfacial layer (FIG. 4, interfacial layer 402 is formed around channels 110 ¶ [0060]) around the channel region; forming a first gate dielectric layer (FIG. 4, dielectric layer 404 is formed around IL 402 ¶ [0060-0062]) around the interfacial layer by a first atomic layer deposition (dielectric layer 404 may be formed by an ALD ¶ [0060]), wherein the first gate dielectric layer comprises an oxide of a first metal (dielectric layer 404 may comprise hafnium oxide, for example ¶ [0061]);
forming a second gate dielectric layer (FIG. 10, dipole forming layer 1002 formed around dielectric layer 404 ¶ [0067]) around the first gate dielectric layer, wherein the second gate dielectric layer comprises an oxide or silicate of a second metal (dipole forming layer 1002 may be lanthanum oxide ¶ [0067]), wherein an oxygen areal density of the first gate dielectric layer is greater than an oxygen areal density of the second gate dielectric layer (the present application explicitly suggests that when the first metal is hafnium, the second metal may be lanthanum, present application ¶ [0070], so using hafnium and lanthanum as taught by Zhang would provide an oxygen areal density relationship consistent with that of the claimed process); and forming a gate electrode (FIG. 13, gate electrode 1306 is formed around second gate dielectric/dipole forming layer 1002 and dielectric layer 404 ¶ [0072]) around the first gate dielectric layer and the second gate dielectric layer while the first gate dielectric layer and the second gate dielectric layer remain present (FIG. 13, second gate dielectric/dipole forming layer 1002 and dielectric layer 404 are both still present when gate electrode 1306 is formed).
Zhang does not disclose that the interfacial layer comprises terminal hydroxyl groups or that the second gate dielectric layer has a thickness greater than a thickness of the first gate dielectric layer. Zhang does suggest a range of thicknesses for the first gate dielectric layer (¶ [0060]), but does not compare the thicknesses of the first and second gate dielectric layers, such a comparison not being of particular importance to the disclosure of their invention.
However, Tsai discloses a method of forming a semiconductor device, the method comprising: forming a first gate dielectric layer (FIG. 2A, ‘second layer’/’dielectric portion’ of gate dielectric layer 206 may be formed over the channel region of substrate 202, ¶ [0015]) over an interfacial layer (FIG. 2A, dielectric portion of layer 206 is formed over the interfacial portion of layer 206, ¶ [0015-0016]), wherein the first gate dielectric layer comprises an oxide of a first metal (‘second layer’/’dielectric portion’ of layer 206 may be formed of metal oxide such as hafnium oxide or zirconium oxide ¶ [0015]); forming a second gate dielectric layer (FIG. 2A, second gate dielectric layer 208 ¶ [0016]) over the first gate dielectric layer (FIG. 2A, layer 208 is above layer 206), wherein the second gate dielectric layer comprises an oxide or silicate of a second metal (second dielectric layer 208 is also formed of a high-k material, and Tsai taught that high-k materials were metal oxides ¶ [0015-0016]). Tsai also discloses that layer 206 (part of which includes the first dielectric layer ¶ [0015]) and second dielectric layer 208 may each range in thickness of 5-30 Å (Tsai ¶ [0015-0016]), as well as that the thicknesses of layers 206 and 208 are important to adjust to avoid both leakage current and a short-channel effect (¶ [0015-0016]); the thicknesses of layers 206 and 208 therefore constituting result-effective variables.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the thicknesses of both the first and second gate dielectric layers of Zhang, as those thicknesses have been identified by Tsai as result-effective variables. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at a set of thicknesses wherein second dielectric layer has a thickness greater than a thickness of the first dielectric layer, in order to balance the thicknesses to avoid both leakage current and a short-channel effect in the device of Zhang. MPEP 2144.05.
Furthermore, the applicant has not presented persuasive evidence that the claimed thickness relationship is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
Zhang in view of Tsai does not disclose that the interfacial layer comprises terminal hydroxyl groups.
However, Yu discloses a method of forming a semiconductor device including a silicon oxide interfacial layer (“An interfacial layer” ¶ [0025]) and a high-k gate dielectric (“The resultant ALD layer” ¶ [0025]), wherein the interfacial layer comprises terminal hydroxyl groups when it is formed with an ALD process (“a sufficiently number of hydroxyl groups over the interfacial layer” ¶ [0025]). This is achieved by using a water pulse in the ALD process to create the hydroxyl groups, and the resultant structure for the interfacial layer allows the high-k gate dielectric “ALD layer” to have increased density (¶ [0025]), which reduced the leakage current in the device (FIG. 2, ¶ [0027]).
Zhang, Tsai, and Yu all pertain to the field of methods of making semiconductor devices including high-k gate dielectrics, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would also have found it obvious to modify the process of Zhang in view of Tsai further in view of Yu to include the water-pulse step of Yu such that the interfacial layer comprises terminal hydroxyl groups, in order to increase the density of the hafnium oxide first gate dielectric layer of Tsai and reduce the leakage current in the device.
Regarding claim 18, Zhang in view of Tsai and Yu discloses the limitations of claim 13 as detailed above, and Zhang further discloses that the second gate dielectric layer is formed by a second atomic layer deposition (Zhang dipole forming layer 1002 is formed with an ALD process ¶ [0067]).
Regarding claim 33, Zhang in view of Tsai and Yu disclose the limitations of claim 13 as detailed above, and Zhang further discloses that the interfacial layer is a silicon oxide layer (interfacial layer 402 may be silicon oxide ¶ [0060]), and the first gate dielectric layer is an aluminum oxide layer (aluminum oxide is listed as an option for a high-k material for the first gate dielectric layer 404 ¶ [0059-0061]). While Zhang does not explicitly list hafnium oxide as the material for the second gate dielectric layer (¶ [0067] lists lanthanum oxide and aluminum oxide as non-exclusive options of transition metal oxides suitable for the second gate dielectric layer), a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to have the second gate dielectric layer is a hafnium oxide layer since hafnium is a transition metal oxide known to be suitable for a second gate dielectric layer (see as an example Tsai ¶ [0015-0016], which may use hafnium oxide as a second high-k gate dielectric layer), and a person of ordinary skill in the art could have been motivated to select hafnium oxide as the material in view of considerations of materials costs and changing market conditions.
Claims 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Tsai and Yu as applied to claim 13 above, and further in view of US patent publication US 20170236702 A1 (Swenberg et al hereinafter Swenberg).
Regarding claim 14, Zhang in view of Tsai and Yu disclose the limitations of claim 13 as detailed above, but they do not further disclose that the first atomic layer deposition comprises a one to three pulses of a metal precursor, wherein a duration of each pulse of the metal precursor is in a range between 0.1 seconds and 5 seconds.
However, Swenberg discloses a method of forming a semiconductor device (FIG. 1, method 100 ¶ [0012, 0018]) comprising a first atomic layer deposition process (an ALD process to form a high-k material ¶ [0018]) which comprises at least one pulse of a metal precursor (metal precursors may be used to form high-k materials such as aluminum, ¶ [0018]). Pulsing a metal precursor in an ALD process is therefore known in the art.
Zhang, Tsai, Yu, and Swenberg pertain to the field of methods for forming dielectric layers in semiconductor devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the method taught by Zhang in view of Tsai and Yu further in view of Swenberg to further include the first atomic layer deposition comprises at least one pulse of a metal precursor, in order to in order to effectively deposit the aluminum of the aluminum-oxide layer in the ALD process, providing the first layer of the gate dielectric.
Zhang in view of Tsai, Yu, and Swenberg does not disclose one to three pulses of the metal precursor, wherein a duration of each pulse of the metal precursor is in a range between 0.1 seconds and 5 seconds. However, it is known in the art that the number of pulses and their duration influence the thickness of the layer that is deposited, and providing the layer with thickness in a desired range allows the layer to provide adequate insulation to the channel region; as discussed regarding claim 13, the thickness of the dielectric layer is a result-effective variable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the number of pulses as well as their respective durations in the first ALD process, since they influence the thickness of the first gate dielectric layer and the thickness of the first gate dielectric layer has been identified as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at one to three pulses of the metal precursor with each pulse’s duration between 0.1 seconds and 5 seconds, in order to provide a thickness for the first gate dielectric layer of Zhang that is sufficient to insulate the channel region while avoiding both leakage current and a short-channel effect, as taught by Tsai. MPEP 2144.05.
Furthermore, the applicant has not presented persuasive evidence that the claimed pulse number/duration is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
Regarding claim 15, Zhang in view of Tsai, Yu, and Swenberg disclose the limitations of claim 14 as detailed above, and they further suggest that the first atomic layer deposition comprises only one pulse of the metal precursor (in view of the routine optimization discussed regarding claim 14, a single pulse of the metal precursor would also have had a reasonable expectation of success to arrive at a thickness for the first gate dielectric as it was suggested in Zhang ¶ [0060]).
Regarding claim 16, Zhang in view of Tsai, Yu, and Swenberg disclose the limitations of claim 14 as detailed above, Swenberg further discloses that the metal precursor comprises hafnium tetrachloride (Swenberg ¶ [0018]]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the method of Zhang in view of Tsai, Yu, and Swenberg further in view of Swenberg such that the metal precursor comprises hafnium tetrachloride, as it is a known metal precursor used to form a hafnium oxide layer, and could be utilized to form the hafnium oxide layer of Zhang as an obvious design choice due to changing market conditions and materials costs.
Regarding claim 17, Zhang in view of Tsai, Yu, and Swenberg discloses the limitations of claim 14 as detailed above, and Swenberg further discloses introducing the metal precursor with a carrier gas (“The first precursor may be introduced with a carrier gas, such as nitrogen”, ¶ [0018]), wherein the carrier gas comprises N2, Ar, He, or a combination thereof (nitrogen, ¶ [0018]). A person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to further modify the method taught by Zhang in view of Tsai, Yu, and Swenberg to further include introducing the metal precursor with a carrier gas, wherein the carrier gas comprises N2, in order to enable uniform distribution of the metal precursor onto the target surface during the formation of the high-k dielectric layer of Zhang.
Zhang in view of Tsai, Yu, and Swenberg do not disclose that a flow rate of the carrier gas is in a range from 100 sccm to 300 sccm; quantifying the flow rate of the carrier gas of that metal precursor not being a detail of particular importance to the disclosure of their invention. Swenberg does teach a different method (FIG. 3, method 300 ¶ [0030]) wherein a carrier gas’ flow rate may range from 200-400 sccm (¶ [0030]).
Further, it is known in the art that the flow rate of a carrier gas in a vacuum chamber affects the deposition rate and the uniformity of the layer that is deposited by the ALD process. Providing the deposited dielectric layer with thickness and uniformity in a desired range allows the layer to provide adequate insulation to the channel region; the thickness and uniformity of the dielectric layer are therefore result-effective variables.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the flow rate of the carrier gas, since the thickness and uniformity of the dielectric layer, dependent on the flow rate, are result-effective variables. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at a flow rate of 100-300 sccm, in order to achieve the desired thickness and uniformity of the dielectric layer; in addition, Swenberg already indicated that flow rate values of the claimed range are achievable by methods known in the prior art (¶ [0030]). MPEP 2144.05.
Furthermore, the applicant has not presented persuasive evidence that the claimed flow rate is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Tsai and Yu as applied to claim 18 above, and further in view of Swenberg.
Zhang in view of Tsai and Yu discloses the limitations of claim 18 as detailed above but does not further disclose that the first atomic layer deposition is performed in a process chamber, wherein the second atomic layer deposition is performed in the process chamber after the first atomic layer deposition without removing the substrate from the process chamber during a period between the first atomic layer deposition and the second atomic layer deposition.
However, Swenberg discloses a method of forming a semiconductor device (FIG. 1, method 100 [0012, 0018]) comprising a first atomic layer deposition process (FIG. 1, operation 104, an ALD process to form a high-k material ¶ [0018]) and a second atomic layer deposition process (FIG. 1, operation 106 ¶ [0019]), the first atomic layer deposition is performed in a process chamber (the processing/ALD chamber ¶ [0018]), wherein the second atomic layer deposition is performed in the process chamber after the first atomic layer deposition (¶ [0019]) without removing the substrate (FIG. 1, substrate is placed in the processing chamber in operation 102 ¶ [0018]) from the process chamber during a period between the first atomic layer deposition and the second atomic layer deposition (at no point during operations 104-106 is the substrate removed ¶ [0018-0019]). Further, a person of ordinary skill in the art before the effective filing date of the claimed invention would note that refraining from removing the substrate between the first and second atomic layer depositions would simplify the manufacturing process by avoiding adding extra steps to the process.
Zhang, Tsai, Yu and Swenberg pertain to the field of methods for forming dielectric layers in semiconductor devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the method taught by Zhang in view of Tsai and Yu further in view of Swenberg to further include that the first atomic layer deposition is performed in a process chamber, wherein the second atomic layer deposition is performed in the process chamber after the first atomic layer deposition without removing the substrate from the process chamber during a period between the first atomic layer deposition and the second atomic layer deposition, in order to simplify the manufacturing process by avoiding adding extra steps to the process.
Claims 21-23, 25, 27, and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Tsai.
Regarding claim 21, Zhang discloses a method of forming a semiconductor device (a method for forming semiconductor structure 100), the method comprising: forming a channel region (FIG. 1A, channel layer 110 are formed ¶ [0039]) over a substrate (FIG. 1A, substrate 102 ¶ [0037]); forming an interfacial layer (FIG. 4, interfacial layer 402 is formed around channels 110 ¶ [0060]) around the channel region; forming a first gate dielectric layer (FIG. 4, dielectric layer 404 is formed around IL 402 ¶ [0060-0062]) around the interfacial layer by a first deposition process (dielectric layer 404 may be formed by an ALD ¶ [0060]), wherein the first gate dielectric layer comprises a compound comprising a first metal (dielectric layer 404 may comprise hafnium oxide, for example ¶ [0061]);
forming a second gate dielectric layer (FIG. 10, dipole forming layer 1002 formed around dielectric layer 404 ¶ [0067]) around the first gate dielectric layer, wherein the second gate dielectric layer comprises a compound of a second metal different from the first metal (dipole forming layer 1002 may be lanthanum oxide ¶ [0067]), wherein an oxygen areal density of the first gate dielectric layer is greater than an oxygen areal density of the second gate dielectric layer (the present application explicitly suggests that when the first metal is hafnium, the second metal may be lanthanum, present application ¶ [0070], so using hafnium and lanthanum as taught by Zhang would provide an oxygen areal density relationship consistent with that of the claimed process); and forming a gate electrode (FIG. 13, gate electrode 1306 is formed around second gate dielectric/dipole forming layer 1002 ¶ [0072]) around the second gate dielectric layer.
Zhang does not further disclose that the second gate dielectric layer has a thickness greater than a thickness of the first gate dielectric layer (Zhang does not compare thicknesses of dielectric layer 404 and dipole forming layer 1002), or forming a source/drain contact to a source/drain region, the source/drain region being adjacent to the channel region, the forming the source/drain contact comprising a reactive ion etch.
Regarding the limitation “the second gate dielectric layer has a thickness greater than a thickness of the first gate dielectric layer”, Tsai discloses a method of forming a semiconductor device, the method comprising: forming a channel region (FIGS. 2A-2C, a channel region is formed between source/drain 218 when they are arranged in substrate 202) over a substrate (FIG. 2C, substrate 202); forming an interfacial layer (FIG. 2A, ‘first layer’ of interfacial layer 206 ¶ [0012, 0015-0016]) over the channel region (FIG. 2C, interfacial layer 206 is over the channel region); forming a first gate dielectric layer over the interfacial layer (FIG. 2A, ‘second layer’/’dielectric portion’ of layer 206 and second dielectric layer 208 ¶ [0015-0016]), wherein the first gate dielectric layer comprises a compound comprising a first metal (‘second layer’/’dielectric portion’ of layer 206 may be formed of metal oxide ¶ [0015]); forming a second gate dielectric layer (FIG. 2A, second dielectric layer 208 ¶ [0016]) over the first gate dielectric layer, wherein the second gate dielectric layer comprises compound of a second metal (second dielectric layer 208 is also formed of a high-k material, and Tsai taught that high-k materials were metal oxides ¶ [0015-0016]).
Tsai also discloses that layer 206 (part of which includes the first dielectric layer ¶ [0015]) and second dielectric layer 208 may each range in thickness of 5-30 Å (Tsai ¶ [0015-0016]), as well as that the thicknesses of layers 206 and 208 are important to adjust to avoid both leakage current and a short-channel effect (¶ [0015-0016]); the thicknesses of layers 206 and 208 therefore constituting result-effective variables. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the thicknesses of the first and second gate dielectric layers as those thicknesses have been identified as result-effective variables. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at a set of thicknesses wherein second dielectric layer has a thickness greater than a thickness of the first dielectric layer, in order to balance the thicknesses to avoid both leakage current and a short-channel effect. MPEP 2144.05.
Furthermore, the applicant has not presented persuasive evidence that the claimed thickness relationship is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
Regarding the limitation “forming a source/drain contact to a source/drain region, the source/drain region being adjacent to the channel region, the forming the source/drain contact comprising a reactive ion etch”, Tsai further discloses forming a source/drain contact (FIG. 2H, contact structure 236 ¶ [0040]) to a source/drain region (FIGS. 2C-2H, source drain features 218 ¶ [0022]), the source/drain region being adjacent to the channel region (FIG. 2H, source drain features 218 are adjacent to the channel region of the substrate), the forming the source/drain contact comprising a reactive ion etch (FIG. 2G, contact opening 226b, formed as a part of the process for forming the source drain contact structure 236, may be formed by an atomic layer etch ALE as a main etch and a reactive ion etch RIE as an over etch ¶ [0039]). Tsai also teaches that the source/drain contact structure 236 may be coupled to another device or component (¶ [0040]).
Zhang and Tsai both pertain to the field of methods for forming semiconductor devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the method of Zhang in view of Tsai to include steps of forming a source/drain contact to a source/drain region, the source/drain region being adjacent to the channel region, the forming the source/drain contact comprising a reactive ion etch, in order to have source/drain contacts that can be couple to other devices, enabling increased device functionality.
Regarding claim 22, Zhang in view of Tsai discloses the limitations of claim 21 as detailed above, and Zhang further discloses that the first gate dielectric layer comprises an oxide of the first metal (dielectric layer 404 may comprise hafnium oxide, for example ¶ [0061]).
Regarding claim 23, Zhang in view of Tsai discloses the limitations of claim 21 as detailed above, and Zhang further discloses that the second gate dielectric layer comprises an oxide or a silicate of the second metal (dipole forming layer 1002 may be lanthanum oxide ¶ [0067]).
Regarding claim 25, Zhang in view of Tsai discloses the limitations of claim 21 as detailed above, and Zhang further discloses that forming the first gate dielectric layer comprises a first atomic layer deposition process (dielectric layer 404 may be formed by an ALD ¶ [0060]).
Regarding claim 27, Zhang in view of Tsai discloses the limitations of claim 21 as detailed above, and Zhang further discloses that forming the second gate dielectric layer comprises a second ALD process (FIG. 10, dipole forming layer 1002 may be formed by an ALD ¶ [0067]).
Regarding claim 34, Zhang in view of Tsai discloses the limitations of claim 21, but do not explicitly teach that the first gate dielectric layer is one to three mono-layers of a metal oxide. However, the thickness of the first gate dielectric layer has been found to be a result-effective variable when considering the disclosure of Zhang in view of Tsai, and Zhang suggests a thickness of the first gate dielectric layer to be in a range of 5-15 Å (Zhang ¶ [0060], dielectric layer 404 being the first gate dielectric layer). In the course of optimizing the thicknesses to avoid both leakage current and a short-channel effect, a person of ordinary skill in the art could have arrived at a configuration wherein the first gate dielectric layer is one to three mono-layers of a metal oxide (in the context of Zhang in view of Tsai, 1-3 monolayers of hafnium oxide).
Furthermore, the applicant has not presented persuasive evidence that the claimed mono-layer configuration is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Tsai as applied to claim 25 above, and further in view of Swenberg.
Zhang in view of Tsai discloses the limitations of claim 25 as detailed above but does not explicitly teach that the first atomic layer deposition process comprises one or more pulses of a metal precursor, wherein the metal precursor comprises trimethylaluminum, aluminum trichloride, dimethylzinc, diethylzinc, trimethylgallium, triethylgallium, hafnium tetrachloride, Hf(NO3)4, Hf[N(CH3)2]4, Hf[N(C2H5)2]4, Hf[N(CH3)(C2H5)]4, or a combination thereof.
However, Swenberg discloses a method of forming a semiconductor device (FIG. 1, method 100 ¶ [0012, 0018]) comprising a first atomic layer deposition process (an ALD process to form a high-k material ¶ [0018]) which comprises one or more pulses of a metal precursor (“The first precursor may be pulsed into the processing chamber” implies at least one pulse ¶ [0018]), wherein the metal precursor comprises trimethylaluminum, aluminum trichloride, dimethylzinc, diethylzinc, trimethylgallium, triethylgallium, hafnium tetrachloride, Hf(NO3)4, Hf[N(CH3)2]4, Hf[N(C2H5)2]4, Hf[N(CH3)(C2H5)]4, or a combination thereof (hafnium tetrachloride, ¶ [0018]).
Zhang, Tsai, and Swenberg pertain to the field of methods for forming dielectric layers in semiconductor devices. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the method taught by Zhang in view of Tsai further in view of Swenberg to include that the first atomic layer deposition process comprises one or more pulses of a metal precursor, wherein the metal precursor comprises hafnium tetrachloride, in order to effectively deposit the hafnium of the hafnium-oxide layer in the ALD process, providing a high-k dielectric for the gate dielectric.
Claims 28-31 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of US patent publication US 20200105532 A1 (Liao et al hereinafter Liao) and Tsai.
Regarding claim 28, Zhang discloses a method of forming a semiconductor device (a method for forming semiconductor structure 100), the method comprising: forming a channel region (FIG. 1A, channel layer 110 are formed ¶ [0039]) over a substrate (FIG. 1A, substrate 102 ¶ [0037]); forming an interfacial layer (FIG. 4, interfacial layer 402 is formed around channels 110 ¶ [0060]) around the channel region; forming a gate dielectric layer (FIGS. 4 and 10, dielectric layer 404 and dipole forming layer 1002 may together constitute a gate dielectric layer and are formed around interfacial layer 402 ¶ [0060-0062, 0067]) around the interfacial layer, wherein forming the gate dielectric layer comprises: performing a first atomic layer deposition process to form a first dielectric layer (FIG. 4, dielectric layer 404 may be formed by an ALD around IL 402 ¶ [0060-0062]), wherein the first dielectric layer comprises an oxide of a first metal (dielectric layer 404 may comprise hafnium oxide, for example ¶ [0061]);
and performing a second atomic layer deposition process (FIG. 10, dipole forming layer 1002 may be formed by an ALD ¶ [0067]) to form a second dielectric layer (FIG. 10, dipole forming layer 1002 formed around dielectric layer 404 ¶ [0067]); and forming a gate electrode (FIG. 13, gate electrode 1306 is formed over second gate dielectric/dipole forming layer 1002 ¶ [0072]) over the second gate dielectric layer.
Zhang does not further disclose that the second dielectric layer comprises a silicate of a second metal (suggested materials for dipole forming layer 1002 are lanthanum oxide and aluminum oxide ¶ [0067]), wherein an oxygen areal density of the first dielectric layer is greater than an oxygen areal density of the second dielectric layer, wherein the second dielectric layer has a thickness greater than a thickness of the first dielectric layer.
Regarding the limitations “the second dielectric layer comprises a silicate of a second metal, wherein an oxygen areal density of the first dielectric layer is greater than an oxygen areal density of the second dielectric layer”, Liao discloses a method of forming a semiconductor device (FIG. 1, the operations of process 8 ¶ [0014]) wherein a gate dielectric layer (FIGS. 1 and 6, high-k gate dielectric 62 ¶ [0028]) may be formed by an ALD process (¶ [0028]) and aluminum oxide, lanthanum oxide, and lanthanum silicate are all considered interchangeable high-k materials for the gate dielectric layer (¶ [0028]). Further, the present application explicitly suggests that when the first metal is hafnium, the second metal may be lanthanum (present application ¶ [0070]), so using hafnium oxide and lanthanum silicate would provide an oxygen areal density relationship consistent with that of the claimed process.
Zhang and Liao both pertain to the field of methods for forming dielectric layers in semiconductor devices. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the method taught by Zhang in view of Liao to use lanthanum silicate as the material of the second dielectric layer, thereby having the second dielectric layer comprises a silicate of a second metal, wherein an oxygen areal density of the first dielectric layer is greater than an oxygen areal density of the second dielectric layer, since Liao has demonstrated lanthanum silicate to be an interchangeable material, which may prove beneficial in view of consideration of materials costs and changing market conditions.
Regarding the limitation “the second dielectric layer has a thickness greater than a thickness of the first dielectric layer”, Tsai discloses a method of forming a semiconductor device, the method comprising: forming a channel region (FIGS. 2A-2C, a channel region is formed between source/drain 218 when they are arranged in substrate 202) over a substrate (FIG. 2C, substrate 202); forming an interfacial layer (FIG. 2A, ‘first layer’ of interfacial layer 206 ¶ [0012, 0015-0016]) over the channel region (FIG. 2C, interfacial layer 206 is over the channel region); forming a first dielectric layer over the interfacial layer (FIG. 2A, ‘second layer’/’dielectric portion’ of layer 206 and second dielectric layer 208 ¶ [0015-0016]), wherein the first dielectric layer comprises a compound comprising a first metal (‘second layer’/’dielectric portion’ of layer 206 may be formed of metal oxide ¶ [0015]); forming a second dielectric layer (FIG. 2A, second dielectric layer 208 ¶ [0016]) over the first dielectric layer, wherein the second gate dielectric layer comprises compound of a second metal (second dielectric layer 208 is also formed of a high-k material, and Tsai taught that high-k materials were metal oxides ¶ [0015-0016]).
Tsai also discloses that layer 206 (part of which includes the first dielectric layer ¶ [0015]) and second dielectric layer 208 have thicknesses which are important to adjust to avoid both leakage current and a short-channel effect (¶ [0015-0016]); the thicknesses of the first and second dielectric layers therefore constituting result-effective variables. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the thicknesses of the first and second dielectric layers as those thicknesses have been identified as result-effective variables. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at a set of thicknesses wherein second dielectric layer has a thickness greater than a thickness of the first dielectric layer, in order to balance the thicknesses to avoid both leakage current and a short-channel effect. MPEP 2144.05.
Furthermore, the applicant has not presented persuasive evidence that the claimed thickness relationship is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
Regarding claim 29, Zhang in view of Liao and Tsai discloses the limitations of claim 28 as detailed above, and they further disclose that the first metal is different than the second metal (Zhang ¶ [0060-0067] in view of Liao ¶ [0028], the first metal is hafnium and the second metal is lanthanum).
Regarding claim 30, Zhang in view of Liao and Tsai discloses the limitations of claim 28 as detailed above, and they further disclose that the first metal is selected from aluminum, zinc, gallium, or hafnium (in this case hafnium, Zhang ¶ [0060-0061]).
Regarding claim 31, Zhang in view of Liao and Tsai discloses the limitations of claim 28 as detailed above, and they further disclose that the second metal comprises hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, yttrium, or combinations thereof (in this case lanthanum, Liao ¶ [0028).
Regarding claim 35, Zhang in view of Liao and Tsai disclose the limitations of claim 28 as detailed above, but they do not explicitly state that a difference in a first capacitance equivalent thickness (CET) of the second dielectric layer and a second CET of a combined layer of the first dielectric layer and the second dielectric layer is in a range from about 0.04 nm to about 0.29 nm. However, the thicknesses of the two gate dielectric layers have already been identified as result-effective variables, in order to balance the thicknesses to avoid both leakage current and a short-channel effect (Tsai ¶ [0015-0016]). Since a person of ordinary skill in the art before the effective filing date of the claimed invention has been motivated to adjust the thicknesses of the first and second gate dielectric layers, the values of the first CET and second CET would also be adjusted since they are dependent on the first and second gate dielectric layers’ thicknesses. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to vary the difference in a first capacitance equivalent thickness (CET) of the second dielectric layer and a second CET of a combined layer of the first dielectric layer and the second dielectric layer during the optimization of the thicknesses of the first and second gate dielectric layers of Tsai, and would have had a reasonable expectation of success to arrive at a difference in a first capacitance equivalent thickness (CET) of the second dielectric layer and a second CET of a combined layer of the first dielectric layer and the second dielectric layer is in a range from about 0.04 nm to about 0.29 nm, in order to balance the thicknesses to avoid both leakage current and a short-channel effect (Tsai ¶ [0015-0016]).
Furthermore, the applicant has not presented persuasive evidence that the claimed CET is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US patent publication US 20200395455 A1 and US patents US 12471354 B2 and US 12396217 B2.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.R.C./Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813