DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 22 December 2025 has been entered. Applicant’s amendments to the claims have overcome the claims objections previously set forth in the Non-Final Office Action filed 24 September 2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-6, 8-9, 11-12, 14-15, 17-18, 20-26 are rejected under 35 U.S.C. 103 as being unpatentable over US 11586910 B1 Duong et al. (hereinafter “Duong”) in view of Patterson, David A., and John L. Hennessy. Computer Organization and Design: The Hardware/Software Interface (5th Edition). Morgan Kaufmann, 2013. (hereinafter “Patterson”).
Apparatus claims 8-9, 11-12, 23-24 will be addressed first, followed by method claims 1-3, 5-6, 21-22, followed by computer product claims 14-15, 17-18, 20, 25-26.
Regarding claim 8, Duong discloses a device comprising:
a memory controller (Fig. 14, memory control, Col. 30, lines 10-23, 45-51) configurable to:
obtain a first signed data value (Fig. 20, 2005, Col. 41, lines 21-23; Fig. 23, 2300, Col. 44, lines 45-50 having a first set of bits (Fig. 23, 10 entries in 2300);
convert the first signed data value to an unsigned data value having a second set of bits (Fig. 23, 2120 “0(x6)|1|6|3|4|9|3|8|10|15|13”, Col. 44, lines 45-54);
obtain a pointer (Fig. 23 “2115” co. 44 ln. 41-44) to a destination address (Fig. 20 “2040” co. 43 ln. 19-26 previous write address) of a memory (Fig. 23 “2100” co. 44 ln. 41-44, 51-54) where the unsigned data value is stored (Fig. 23 “2215” co. 43 ln. 48-65, co. 44 ln. 55-67; Fig. 20 “2020, 2030” co. 42 ln. 33-36, co. 43 ln. 11-21); and
adjust the pointer (Fig. 23, 2130 and 2115, 2115 pointer is updated, Col. 45, lines 4-15) based on a difference in a number of bits (Col. 45, lines 5-15; previous example mentioned is referenced in Fig. 22, Col. 44, lines 1-17) between the first set of bits (Fig. 23, 10 entries in 2300) and the second set of bits (Fig. 23, 16 entries in 2100 after shifting, Col. 44, lines 51-54) to obtain a second signed data value (Fig. 23 “2315” co. 44 ln. 67-co. 45 ln.1-3); and
a processor (Fig. 4, 415a-h, Col. 14, lines 46-54) coupled to the memory controller, wherein the processor is configurable to:
perform a computation (Col. 32, lines 13-21; Col. 30, lines 45-61, dot product computations) based on the second signed data value (Fig. 23 “2315” co. 44 ln. 67-co. 45 ln.1-3) to obtain an adjusted output value (Fig. 14, partial dot products, Col. 32, lines 13-21; output from core, Col. 15, lines 50-63); and
perform a shift operation on the adjusted output value (Col. 22, lines 17-20; Fig. 7, 720 connected to 730 cores (of cluster) of dot product cores 415a-h) based on the difference (Col. 45, lines 5-15; previous example mentioned is referenced in Fig. 22, Col. 44, lines 1-17) in the number of bits between the first set of bits (Fig. 23, 10 entries in 2300 propagated during operations to be output from core as partial dot product) and the second set of bits (Fig. 23, 16 entries in 2100 after shifting, Col. 44, lines 51-54) to obtain an output value (Col. 22, lines 17-20, right shifted output values).
Duong discloses the processing of the input and output values, and discloses signed and unsigned values with respect to the dot product operations (Col. 34, lines 38-58). However, it appears they are silent with disclosing a first signed data value, an unsigned data value, and second signed data value with respect to the “obtaining”, “converting”, “adjusting”, and “performing the computation”.
Patterson discloses signed (Pg. 75, Para. 4) and unsigned (Pg. 74, Para. 3-4) data values.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Duong’s system with Patterson’s unsigned/signed feature because they are in the claimed invention’s same field of endeavor of computer architecture (Pg. 76, Hardware/Software Interface Section). Although Duong generally discloses processing the input and output values, they are silent with explicitly describing them as unsigned/signed. It would have been obvious to one of ordinary skill in the art to implement them as unsigned/signed format as they are a well-known technique for data representation (Pg. 77, Hardware/Software Interface Section), and doing so would have yielded predictable results when implemented. Using the known data representation to provide a predictable outcome in Duong would have been obvious to one of ordinary skill in the art, since one of ordinary skill in the art would recognize the potential benefits associated with this modification, such as safeguarding against overflow (Pg. 74, Para. 7) and/or avoiding negative addressing by configuring the program to deal with numbers positive or negative and sometimes only positive (Pg. 77, Hardware/Software Interface Section).
Regarding claim 9, in addition to the teachings addressed in the claim 8 analysis, the rejection of claim 8 is incorporated and Duong discloses wherein the memory controller (see claim 8 mapping):
includes an electronic circuit to perform unsigned bit up-conversions (Fig. 23, 2120, Col. 44, lines 45-54, 60-67).
Duong discloses the processing of the input and output values, and discloses signed and unsigned values with respect to the dot product operations (Col. 34, lines 38-58). However, it appears they are silent with disclosing unsigned.
Patterson discloses unsigned (Pg. 74, Para. 3-4) data values.
The motivation to combine provided with respect to claim 8 similarly applies.
Regarding claim 11, in addition to the teachings addressed in the claim 8 analysis, the rejection of claim 8 is incorporated and Duong discloses wherein the computation (see claim 8 mapping):
is a linear computation (Col. 15, lines 64-67, Col. 16, lines 1-12).
Regarding claim 12, in addition to the teachings addressed in the claim 8 analysis, the rejection of claim 8 is incorporated and Duong discloses wherein the memory controller (see claim 8 mapping):
is configured to convert the first signed data value (Fig. 20, 2005, Col. 41, lines 21-23; Fig. 23, 2300, Col. 44, lines 45-50) by
writing the first signed data value and a number of zeros (Fig. 23, 0 (x6) and 0 (x16), Col. 44, lines 45-54, number of nibbles) to the destination address of the memory (Fig. 23 “2215” co. 43 ln. 48-65, co. 44 ln. 55-67; Fig. 20 “2020, 2030” co. 42 ln. 33-36, co. 43 ln. 11-21), wherein the number of zeros is based on the difference (co. 44 ln. 45-54, 60-67; Col. 45, lines 5-15; previous example mentioned is referenced in Fig. 22, Col. 44, lines 1-17) in the numbers of bits between the first set of bits (Fig. 23, 10 entries in 2300 propagated during operations to be output from core as partial dot product) and the second set of bits (Fig. 23, 16 entries in 2100 after shifting, Col. 44, lines 51-54).
Duong discloses the processing of the input and output values, and discloses signed and unsigned values with respect to the dot product operations (Col. 34, lines 38-58). However, it appears they are silent with disclosing a first signed data value, an unsigned data value, and second signed data value with respect to the “obtaining”, “converting”, “adjusting”, and “performing the computation”.
Patterson discloses signed (Pg. 75, Para. 4) and unsigned (Pg. 74, Para. 3-4) data values.
The motivation to combine provided with respect to claim 8 similarly applies.
Regarding claim 23, in addition to the teachings addressed in the claim 12 analysis, the rejection of claim 12 is incorporated and Duong discloses wherein:
the number of zeros is written to a left of the first signed data value (Fig. 23 0 (x6) co. 44 ln. 51-54), wherein the memory is configurable to store data (Fig. 23 “2215” co. 43 ln. 48-65, co. 44 ln. 55-67; Fig. 20 “2020, 2030” co. 42 ln. 33-36, co. 43 ln. 11-21) in big endian format, and wherein the shift operation on the adjusted output value is a right shift operation (Col. 22, lines 17-20; Fig. 7, 720 connected to 730 cores (of cluster) of dot product cores 415a-h).
Duong discloses the processing of the input and output values, and discloses signed and unsigned values with respect to the dot product operations (Col. 34, lines 38-58). However, it appears they are silent with disclosing a first signed data value with respect to the “obtaining” and “converting”. Further, Duong is silent with disclosing storing in big endian format.
Patterson discloses signed (Pg. 75, Para. 4) data values.
The motivation to combine provided with respect to claim 8 similarly applies.
In a separate section of Patterson, Patterson discloses storing in big endian format (Pg. A-43 “Byte Order” big-endian order).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Duong’s system with Patterson’s endian feature because they are in the claimed invention’s same field of endeavor of processor-based execution (Pg. A-43, “Byte Order” processors). Although Duong generally discloses storing, they are silent with explicitly describing them as being stored in big endian format. It would have been obvious to one of ordinary skill in the art to store them using big endian format as this is a well-known technique for data storage representation (Pg. A-43 “Byte Order” big-endian; Pg. 70 big end), and doing so would have yielded predictable results when implemented. Using the known data storage representation to provide a predictable outcome in Duong would have been obvious to one of ordinary skill in the art, since one of ordinary skill in the art would recognize the potential benefits associated with this modification, such as providing greater configurability and control over how data is stored (Pg. A-43 “Byte Order”).
Regarding claim 24, in addition to the teachings addressed in the claim 12 analysis, the rejection of claim 12 is incorporated and Duong discloses wherein:
the number of zeros is written to a right of the first signed data value (Fig. 23 0 (x16) co. 44 ln. 51-54), wherein the memory is configurable to store data (Fig. 23 “2215” co. 43 ln. 48-65, co. 44 ln. 55-67; Fig. 20 “2020, 2030” co. 42 ln. 33-36, co. 43 ln. 11-21) in little endian format, and wherein the shift operation on the adjusted output value is a left shift operation (Col. 22, lines 17-20; Fig. 7, 720 connected to 730 cores (of cluster) of dot product cores 415a-h).
Duong discloses the processing of the input and output values, and discloses signed and unsigned values with respect to the dot product operations (Col. 34, lines 38-58). However, it appears they are silent with disclosing a first signed data value with respect to the “obtaining” and “converting”. Duong is silent with disclosing storing in little endian format. Further, while Duong discloses a right shift operation (Col. 22, lines 17-20; Fig. 7, 720 connected to 730 cores (of cluster) of dot product cores 415a-h), they appear to be silent with disclosing the shift operation as a left shift.
Patterson discloses signed (Pg. 75, Para. 4) data values.
The motivation to combine provided with respect to claim 8 similarly applies.
In a separate section of Patterson, Patterson discloses storing in little endian format (Pg. A-43 “Byte Order” little-endian order) and left shifting (Pg. 64, Fig. 2.1 ‘shift left logical’).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Duong’s system with Patterson’s endian feature because they are in the claimed invention’s same field of endeavor of processor-based execution (Pg. A-43, “Byte Order” processors). Although Duong generally discloses storing, they are silent with explicitly describing them as being stored in little endian format. It would have been obvious to one of ordinary skill in the art to store them using little endian format as this is a well-known technique for data storage representation (Pg. A-43 “Byte Order” little-endian; Pg. 70 little end), and doing so would have yielded predictable results when implemented. Using the known data storage representation to provide a predictable outcome in Duong would have been obvious to one of ordinary skill in the art, since one of ordinary skill in the art would recognize the potential benefits associated with this modification, such as providing greater configurability and control over how data is stored (Pg. A-43 “Byte Order”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Duong’s system with Patterson’s left shifting feature because they are in the claimed invention’s same field of endeavor of computer-based execution (Pg. 63, “Operations of the Computer Hardware” assembly language). Although Duong generally discloses shifting, they are silent with explicitly describing left shifting. It would have been obvious to one of ordinary skill in the art to shift using a left-based approach as this is a well-known technique for performing arithmetic in computers (Pg. 63 “Operations of the Computer Hardware” instructions; Pg. 64 “MIPS assembly language”), and doing so would have yielded predictable results when implemented. Using the known data instructions for performing arithmetic to provide a predictable outcome in Duong would have been obvious to one of ordinary skill in the art, since one of ordinary skill in the art would recognize the potential benefits associated with this modification, such as providing greater configurability and control over how data is shifted (Pg. 64, Fig. 2.1 “Logical”).
Claims 1-3, 5-6, 21-22 are directed to a method that would be performed by the apparatus of claims 8-9, 11-12, 23-24. The claims 8, 9, 11, 12, 23, 24 analysis equally applies to 1 and 3, 2, 5, 6, 21, 22, respectively, and claims 1-3, 5-6, 21-22 are similarly rejected.
Claims 14-15, 17-18, 25-26 are directed to a computer program product that would be executed by the apparatus of claims 8-9, 11-12, 23-24. The claims 8-9, 11-12, 23-24 analysis equally applies to 14-15, 17-18, 25-26, respectively, and claims 14-15, 17-18, 25-26 are similarly rejected.
Additionally in claim 14, Duong discloses instructions further causing one or more processors (Col. 14, lines 55-67, instructions).
Regarding claim 20, in addition to the teachings addressed in the claim 14 analysis, the rejection of claim 14 is incorporated and Duong discloses wherein
the instructions (Col. 14, lines 55-67, instructions) further comprise:
instructions to cause the one or more processors (Fig. 4, 415a-h, Col. 14, lines 46-54) to
transmit an indication (Col. 32, lines 4-21, core controller 1440 sends values to 1425) to the memory controller (Fig. 14, memory control, Col. 30, lines 10-23, 45-51) to convert the first signed data value (Fig. 20, 2005, Col. 41, lines 21-23; Fig. 23, 2300, Col. 44, lines 45-50); and
instructions (co. 20 ln. 38-41) to cause the memory controller to transmit an indication (Col. 20, lines 61-64, indicates which cores each output value is delivered; Col. 22, lines 7-10, carried to another core in another cluster) to the one or more processors to perform the shift operation (Col. 22, lines 17-20).
Duong discloses the processing of the input and output values, and discloses signed and unsigned values with respect to the dot product operations (Col. 34, lines 38-58). However, it appears they are silent with disclosing a first signed data value with respect to the “obtaining” and “converting”.
Patterson discloses signed (Pg. 75, Para. 4) data values.
The motivation to combine provided with respect to claim 8 similarly applies.
Response to Arguments
Claims Objections. The claims objections are withdrawn based upon the amendments to the claims.
35 USC 103. Applicant's arguments filed 22 December 2025 have been fully considered but they are not persuasive.
Applicant argues the following in substance:
Applicant asserts that, Duong does not teach or suggest whether each output value (nibble) is signed or unsigned data value. Duong does not teach or suggest converting a signed data value to an unsigned data value with a different set of bits (Remarks p. 9 ⁋ 3 – p. 10 ⁋ 1). Duong does not teach or suggest adjusting the pointer to obtain another signed data value (Remarks p. 10 ⁋ 1).
Examiner respectfully disagrees. Duong is not relied upon in the rejection to disclose signed or unsigned data values, instead Patterson is relied upon to disclose these aspects of the limitations. Duong provides the architectural and functional framework for which to execute the obtaining, converting, adjusting, performing computations, and shifting operations, primarily with respect to Figs. 4, 14, and 23.
The write controller and cache “1425” of Fig. 14 contains operations described with respect to Figs. 20-24 (co. 32 ln. 19-21). Fig. 14 illustrates the data flow within one dot product core of embodiments for a dot product computation (co. 29 ln. 66-67 – co. 30 ln. 1-9), and of which the computation circuits are described with reference to Fig. 15. Further, Fig. 4 provides an illustration of an exemplary embodiment of dot product cores (co. 14 ln. 46-57). Although Fig. 15 is not explicitly relied upon in the rejection due to the manner in which the claims are recited, Fig. 15 provides further disclosure with respect to Fig. 14 relating to handling signed and unsigned values (co. 34 ln. 49-58). Although not explicitly describing the values with respect to Figs. 4, 14, and 23, as unsigned or signed, Duong generally discloses embodiments of a neural network computation fabric for performing inferences using signed and unsigned values, therefore, it would have been obvious to one of ordinary skill in the art to look to Patterson and modify with Patterson’s teachings.
Applicant asserts that, Patterson does not teach or suggest adjusting a pointer to an unsigned data value to obtain a signed data value (Remarks p. 10 ⁋ 2).
Examiner respectfully disagrees. Patterson is not relied upon to teach the entire limitation, only the signed and unsigned feature as discussed in response to Argument 1) and 35 USC 103 rejection. Further, it is the combination of Duong in view of Patterson which discloses adjusting a pointer to an unsigned data value to obtain a signed data value.
Applicant asserts that, none of Duong and Pattern teaches or suggests "obtaining a pointer to a destination address where the unsigned data value is stored; adjusting the pointer based on a difference between the first set of bits and the second set of bits to obtain a second signed data value." (Remarks p. 10 ⁋ 3).
Examiner respectfully disagrees. Duong in view of Patterson discloses obtaining a pointer to a destination address where the unsigned data value is stored; adjusting the pointer based on a difference between the first set of bits and the second set of bits to obtain a second signed data value, as discussed in response to Argument 1) and 35 USC 103 rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151