DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s reply filed on 22 September 2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 28 August 2025 is in compliance with the provisions of 37 CFR 1.97 and has been considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 and 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih (U.S. Pub. 2018/0102311) in view of Hu (U.S. Pub. 2017/0229409).
Claim 1: Shih discloses a multi-chip package, in annotated Fig. 14 below and in paragraphs 27, 39, 49, 56 and 60, comprising:
an interconnect bridge (101) having a first contact pad and a second contact pad thereon, the interconnect bridge (101) comprising a silicon die;
a conductive structure (lower portion of 510) laterally spaced apart from the interconnect bridge (101);
a second dielectric layer (202 and 550) over the interconnect bridge (101) and over the conductive structure (lower portion of 510);
a first via in the second dielectric layer (202 and 550), the first via coupled to the first contact pad;
a second via in the second dielectric layer (202 and 550), the second via coupled to the second contact pad;
a third via (upper portion of 510) in the second dielectric layer (202 and 550), the third via (upper portion of 510) above and coupled to the conductive structure (lower portion of 510);
a third dielectric layer (912) on the second dielectric layer (502 and 550), the third dielectric layer (912) over the interconnect bridge (101) and over the conductive structure (lower portion of 510);
a first die (11) over the third dielectric layer (912), the first die (11) over the interconnect bridge (101) and over the conductive structure (lower portion of 510); and
a second die (12) over the interconnect bridge (101), the second die (12) coupled to the first die (11) by the interconnect bridge (101).
PNG
media_image1.png
532
868
media_image1.png
Greyscale
Shih appears not to explicitly disclose the conductive structure has an uppermost surface above a bottommost surface of the interconnect bridge,
a first dielectric layer, the first dielectric layer laterally adjacent the interconnect bridge, and the first dielectric layer laterally adjacent and in contact with the conductive structure,
the second dielectric layer on the first dielectric layer,
wherein the third via is separate and distinct from the conductive structure, and
wherein the third via has a center laterally offset from a center of the conductive structure.
Hu, however, in Fig. 6 (enlarged portion of Fig. 6 provided below) and in paragraphs 30, 37 and 38, discloses the conductive structure has an uppermost surface above a bottommost surface of the interconnect bridge (20),
a first dielectric layer, the first dielectric layer laterally adjacent the interconnect bridge (20), and the first dielectric layer laterally adjacent and in contact with the conductive structure,
the second dielectric layer on the first dielectric layer,
wherein the third via is separate and distinct from the conductive structure, and
wherein the third via has a center laterally offset from a center of the conductive structure.
PNG
media_image2.png
512
944
media_image2.png
Greyscale
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Shih with the disclosure of Hu to have made the conductive structure has an uppermost surface above a bottommost surface of the interconnect bridge,
a first dielectric layer, the first dielectric layer laterally adjacent the interconnect bridge, and the first dielectric layer laterally adjacent and in contact with the conductive structure, and the second dielectric layer on the first dielectric layer,
wherein the third via is separate and distinct from the conductive structure, and
wherein the third via has a center laterally offset from a center of the conductive structure in order to be able to route electrical signals to different parts of the package.
Claim 2: Shih in view of Hu discloses the multi-chip package of claim 1, and in Fig. 14 and in paragraph 56, Shih discloses further comprising:
one or more through silicon vias (110) in the silicon die.
Claim 3: Shih in view of Hu discloses the multi-chip package of claim 1, and in Fig. 14, Shih further discloses wherein the conductive structure (lower portion of 510) has a vertical length greater than a vertical length of each of the first via and the second via.
Claim 4: Shih in view of Hu discloses the multi-chip package of claim 1, and in Fig. 14, Shih further discloses wherein the conductive structure (lower portion of 510) has a vertical length greater than a vertical length of each of the first contact pad and the second contact pad.
Claim 11: Shih discloses a multi-chip package, in annotated Fig. 14 below and in paragraphs 27, 39, 49, 56 and 60, comprising:
an interconnect bridge (101) having a first contact pad and a second contact pad thereon, the interconnect bridge (101) having one or more through vias (110);
a conductive structure (lower portion of 510) laterally spaced apart from the interconnect bridge (101);
a second dielectric layer (202 and 550) over the interconnect bridge (101) and over the conductive structure (lower portion of 510);
a first via in the second dielectric layer (202 and 550), the first via coupled to the first contact pad;
a second via in the second dielectric layer (202 and 550), the second via coupled to the second contact pad;
a third via (upper portion of 510) in the second dielectric layer (202 and 550), the third via (upper portion of 510) above and coupled to the conductive structure (lower portion of 510);
a third dielectric layer (912) on the second dielectric layer (202 and 550), the third dielectric layer (912) over the interconnect bridge (101) and over the conductive structure (lower portion of 510);
a first die (11) over the third dielectric layer (912), the first die (11) over the interconnect bridge (101) and over the conductive structure (lower portion of 510); and
a second die (12) over the interconnect bridge (101), the second die (12) coupled to the first die (11) by the interconnect bridge (101).
PNG
media_image3.png
510
895
media_image3.png
Greyscale
Shih appears not to explicitly disclose the conductive structure has an uppermost surface above a bottommost surface of the interconnect bridge,
a first dielectric layer, the first dielectric layer laterally adjacent the interconnect bridge, and the first dielectric layer laterally adjacent and in contact with the conductive structure,
the second dielectric layer on the first dielectric layer, and
wherein the third via is separate and distinct from the conductive structure, and
wherein the third via has a center laterally offset from a center of the conductive structure.
Hu, however, in Fig. 6 (enlarged portion of Fig. 6 provided below) and in paragraphs 30, 37 and 38, discloses the conductive structure has an uppermost surface above a bottommost surface of the interconnect bridge (20),
a first dielectric layer, the first dielectric layer laterally adjacent the interconnect bridge (20), and the first dielectric layer laterally adjacent and in contact with the conductive structure,
the second dielectric layer on the first dielectric layer,
wherein the third via is separate and distinct from the conductive structure, and
wherein the third via has a center laterally offset from a center of the conductive structure.
PNG
media_image2.png
512
944
media_image2.png
Greyscale
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Shih with the disclosure of Hu to have made the conductive structure has an uppermost surface above a bottommost surface of the interconnect bridge,
a first dielectric layer, the first dielectric layer laterally adjacent the interconnect bridge, and the first dielectric layer laterally adjacent and in contact with the conductive structure, and the second dielectric layer on the first dielectric layer,
wherein the third via is separate and distinct from the conductive structure, and
wherein the third via has a center laterally offset from a center of the conductive structure in order to be able to route electrical signals to different parts of the package.
Claim 12: Shih in view of Hu discloses the multi-chip package of claim 11, and in annotated Fig. 14 above, Shih discloses further comprising:
a conductive via vertically beneath the interconnect bridge (101).
Claim 13: Shih in view of Hu discloses the multi-chip package of claim 11, and in Fig. 14, Shih further discloses wherein the conductive structure (lower portion of 510) has a vertical length greater than a vertical length of each of the first via and the second via.
Claim 14: Shih in view of Hu discloses the multi-chip package of claim 11, and in Fig. 14, Shih further discloses wherein the conductive structure (lower portion of 510) has a vertical length greater than a vertical length of the first contact pad and the second contact pad.
Claim(s) 5-10 and 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih in view of Hu as applied to claims 1 and 11 above, and further in view of Braunisch et al. (U.S. Pub. 2010/0327424).
Claim 5: Shih in view of Hu discloses the multi-chip package of claim 1.
Shih in view of Hu appears not to explicitly disclose a cavity laterally between the interconnect bridge and the first dielectric layer.
Braunisch et al., however, in Fig. 6 and in paragraph 49 and 62, discloses a cavity (615) laterally between the interconnect bridge (540) and the first dielectric layer (610) in order to prevent underfillings of dies from being disturbed.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Shih in view of Hu with the disclosure of Braunisch et al. to have made a cavity laterally between the interconnect bridge and the first dielectric layer in order to prevent underfillings of dies from being disturbed (paragraph 49 of Braunisch).
Claim 6: Shih in view of Hu discloses the multi-chip package of claim 1.
Shih in view of Hu appears not to explicitly disclose wherein the interconnect bridge is laterally spaced apart from the first dielectric layer.
Braunisch et al., however, in Fig. 6 and in paragraph 49 and 62, discloses the interconnect bridge (540) is laterally spaced apart from the first dielectric layer (610) in order to prevent underfillings of dies from being disturbed.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Shih in view of Hu with the disclosure of Braunisch et al. to have made the interconnect bridge is laterally spaced apart from the first dielectric layer in order to prevent underfillings of dies from being disturbed (paragraph 49 of Braunisch).
Claims 7 and 8: Shih in view of Hu discloses the multi-chip package of claim 1.
Shih in view of Hu appears not to explicitly disclose wherein the first die is a main die, and the second die is a secondary die; and
wherein the main die is a die selected from the group consisting of a central processing unit (CPU) die, a graphics processing unit (GPU) die, and an application-specific integrated circuit (ASIC) die, and wherein the secondary die is a die selected from the group consisting of a memory die and a transceiver die.
Braunisch et al., however, in paragraph 74, discloses the first die (1120) is a main die, and the second die (1130) is a secondary die; and
wherein the main die (1120) is a die selected from the group consisting of a central processing unit (CPU) die, a graphics processing unit (GPU) die, and an application-specific integrated circuit (ASIC) die, and wherein the secondary die (1130) is a die selected from the group consisting of a memory die and a transceiver die.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Shih in view of Hu with the disclosure of Braunisch et al. to have made the first die is a main die, and the second die is a secondary die; and
wherein the main die is a die selected from the group consisting of a central processing unit (CPU) die, a graphics processing unit (GPU) die, and an application-specific integrated circuit (ASIC) die, and wherein the secondary die is a die selected from the group consisting of a memory die and a transceiver die in order to for the package to have functionality.
Claims 9 and 10: Shih in view of Hu discloses the multi-chip package of claim 1.
Shih in view of Hu appears not to explicitly disclose wherein the first die is coupled to the interconnect bridge by a first plurality of conductive bumps having a first pitch, and wherein the first die further comprises a second plurality of conductive bumps having a second pitch greater than the first pitch; and
wherein the second die is coupled to the interconnect bridge by a third plurality of conductive bumps having a third pitch, and wherein the second die further comprises a fourth plurality of conductive bumps having a fourth pitch greater than the third pitch.
Braunisch et al., however, in Fig. 6 and in paragraphs 22, 46, 48 and 51, discloses the first die (520) is coupled to the interconnect bridge (540) by a first plurality of conductive bumps (bumps between 520 and 540) having a first pitch (fine pitch), and wherein the first die further comprises a second plurality of conductive bumps (bumps between 520 and 610) having a second pitch (course pitch) greater than the first pitch; and
wherein the second die (530) is coupled to the interconnect bridge (540) by a third plurality of conductive bumps (bumps between 530 and 510) having a third pitch (fine pitch), and wherein the second die further comprises a fourth plurality of conductive bumps (bumps between 530 and 610) having a fourth pitch (course pitch) greater than the third pitch in order to increase communication bandwidth.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Shih in view of Hu with the disclosure of Braunisch et al. to have made the first die is coupled to the interconnect bridge by a first plurality of conductive bumps having a first pitch, and wherein the first die further comprises a second plurality of conductive bumps having a second pitch greater than the first pitch; and
the second die is coupled to the interconnect bridge by a third plurality of conductive bumps having a third pitch, and wherein the second die further comprises a fourth plurality of conductive bumps having a fourth pitch greater than the third pitch in order to increase communication bandwidth (paragraph 22).
Claim 15: Shih in view of Hu discloses the multi-chip package of claim 11
Shih in view of Hu appears not to explicitly disclose a cavity laterally between the interconnect bridge and the first dielectric layer.
Braunisch et al., however, in Fig. 6 and in paragraph 49 and 62, discloses a cavity (615) laterally between the interconnect bridge (540) and the first dielectric layer (610) in order to prevent underfillings of dies from being disturbed.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Shih in view of Hu with the disclosure of Braunisch et al. to have made a cavity laterally between the interconnect bridge and the first dielectric layer in order to prevent underfillings of dies from being disturbed (paragraph 49 of Braunisch).
Claim 16: Shih in view of Hu discloses the multi-chip package of claim 11.
Shih in view of Hu appears not to explicitly disclose wherein the interconnect bridge is laterally spaced apart from the first dielectric layer.
Braunisch et al., however, in Fig. 6 and in paragraph 49 and 62, discloses the interconnect bridge (540) is laterally spaced apart from the first dielectric layer (610) in order to prevent underfillings of dies from being disturbed.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Shih in view of Hu with the disclosure of Braunisch et al. to have made the interconnect bridge is laterally spaced apart from the first dielectric layer in order to prevent underfillings of dies from being disturbed (paragraph 49 of Braunisch).
Claims 17 and 18: Shih in view of Hu discloses the multi-chip package of claim 11.
Shih in view of Hu appears not to explicitly disclose wherein the first die is a main die, and the second die is a secondary die; and
wherein the main die is a die selected from the group consisting of a central processing unit (CPU) die, a graphics processing unit (GPU) die, and an application-specific integrated circuit (ASIC) die, and wherein the secondary die is a die selected from the group consisting of a memory die and a transceiver die.
Braunisch et al., however, in paragraph 74, discloses the first die (1120) is a main die, and the second die (1130) is a secondary die; and
wherein the main die (1120) is a die selected from the group consisting of a central processing unit (CPU) die, a graphics processing unit (GPU) die, and an application-specific integrated circuit (ASIC) die, and wherein the secondary die (1130) is a die selected from the group consisting of a memory die and a transceiver die.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Shih in view of Hu with the disclosure of Braunisch et al. to have made the first die is a main die, and the second die is a secondary die; and
wherein the main die is a die selected from the group consisting of a central processing unit (CPU) die, a graphics processing unit (GPU) die, and an application-specific integrated circuit (ASIC) die, and wherein the secondary die is a die selected from the group consisting of a memory die and a transceiver die in order to for the package to have functionality.
Claims 19 and 20: Shih in view of Hu discloses the multi-chip package of claim 11.
Shih in view of Hu appears not to explicitly disclose wherein the first die is coupled to the interconnect bridge by a first plurality of conductive bumps having a first pitch, and wherein the first die further comprises a second plurality of conductive bumps having a second pitch greater than the first pitch; and
wherein the second die is coupled to the interconnect bridge by a third plurality of conductive bumps having a third pitch, and wherein the second die further comprises a fourth plurality of conductive bumps having a fourth pitch greater than the third pitch.
Braunisch et al., however, in Fig. 6 and in paragraphs 22, 46, 48 and 51, discloses the first die (520) is coupled to the interconnect bridge (540) by a first plurality of conductive bumps (bumps between 520 and 540) having a first pitch (fine pitch), and wherein the first die further comprises a second plurality of conductive bumps (bumps between 520 and 610) having a second pitch (course pitch) greater than the first pitch; and
wherein the second die (530) is coupled to the interconnect bridge (540) by a third plurality of conductive bumps (bumps between 530 and 510) having a third pitch (fine pitch), and wherein the second die further comprises a fourth plurality of conductive bumps (bumps between 530 and 610) having a fourth pitch (course pitch) greater than the third pitch in order to increase communication bandwidth.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Shih in view of Hu with the disclosure of Braunisch et al. to have made the first die is coupled to the interconnect bridge by a first plurality of conductive bumps having a first pitch, and wherein the first die further comprises a second plurality of conductive bumps having a second pitch greater than the first pitch; and
the second die is coupled to the interconnect bridge by a third plurality of conductive bumps having a third pitch, and wherein the second die further comprises a fourth plurality of conductive bumps having a fourth pitch greater than the third pitch in order to increase communication bandwidth (paragraph 22).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN LIN whose telephone number is (571)270-1274. The examiner can normally be reached Monday-Friday 10am-6pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JAY C KIM/Primary Examiner, Art Unit 2815
/J.L/ Examiner, Art Unit 2815