DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/08/2026 has been entered.
Response to Arguments
Applicant’s amendments and the accompanying arguments with respect to the first base die and the second base die being laterally between the first metal functional connection and the second metal functional connection, in claims 1 and 15, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Woychik et al. (US 2016/0049383).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-9, 11-19, and 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 2015/0171006) in view of Woychik et al. (US 2015/0270209), Koide et al. (US 2011/0089579), Shen et al. (US 2015/0327367), and Woychik et al. (US 2016/0049383).
In reference to claim 1, Hung et al. (US 2015/0171006), hereafter “Hung,” discloses a chip package, with reference to Figures 35A and 35B, comprising:
a first base die 100 in a molding material 34, the first base die comprising interconnections, paragraphs 12, 18, and 33;
a first metal functional connection 32 in the molding material, the first metal functional connection laterally adjacent to the base die, paragraph 16;
a first chip 200 electrically coupled to the first base die;
a second chip 200 electrically coupled to the first base die, wherein one of the first chip or the second chip has first terminations and second terminations, paragraph 25; and
a dielectric material 56 between and in contact with the first chip and the second chip, paragraph 26.
Hung does not disclose the first base die comprising die-to-die interconnections,
the second chip electrically coupled to the first chip by the die-to-die interconnections in the first base die
the second terminations having a pitch less than a pitch of the first terminations, and wherein the second terminations are coupled to the die-to die interconnections of the first base die,
the dielectric material having an upper surface co-planar with an upper surface of the first chip, or
a second base die in the molding material, the second base die comprising die-to-die interconnections, and the second base die laterally spaced apart from the first base die, wherein the molding material is laterally between the second base die and the first base die, or
a second metal functional connection in the molding material, the second metal functional connection laterally adjacent to the second base die, wherein the first base die and the second base die are laterally between the first metal functional connection and the second metal functional connection.
Woychik et al. (US 2015/0270209), hereafter “Woychik,” discloses a chip package including teaching a base die, 340 in Figure 6F-1, comprising die-to-die interconnections, a second chip 302, electrically coupled to a first chip 301 by the die-to-die interconnections in the base die 340, paragraphs 41 and 43. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first base die to comprise die-to-die interconnections, the second chip to be electrically coupled to the first chip by the die-to-die interconnections in the first base die. One would have been motivated to do so in order to provide die-to-die interconnection in a 3D-IC package, paragraphs 41 and 42.
Koide et al. (US 2011/0089579), hereafter “Koide,” discloses a semiconductor device package including teaching wherein one of the first chip or the second chip, 30A in Figure 1, has first terminations 32b and second terminations 32a, the second terminations 32a having a pitch less than a pitch of the first terminations, and wherein the second terminations are coupled to the die-to-die interconnections of the base die, Figure 2 and paragraphs 17, 20, and 22. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the second terminations to have a pitch less than a pitch of the first terminations, wherein the second terminations are coupled to the die-to-die interconnections of the first base die. One would have been motivated to do so in order to form wiring between chips that is the same as wiring within the chip in order to suppress a decrease in transmission efficiency between chips, paragraphs 27 and 30.
Woychik further teaches a dielectric material, 322 in Figure 6F-1, having an upper surface co-planar with an upper surface of the first chip 301, paragraphs 46 and 59. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the dielectric material to have an upper surface co-planar with an upper surface of the first chip. One would have been motivated to do so in order to dissipate heat from an upper surface of the chip, paragraph 40.
Shen et al. (US 2015/0327367), hereafter “Shen,” discloses a semiconductor chip package including a first base die, ITP 120 in Figure 1, a second base die, ITP 120, in the molding material (not pictured), the second base die laterally spaced apart from the first base die, wherein the molding material is laterally between the second base die and the first base die, paragraph 4. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a second base die to be in the molding material, the second base die laterally spaced apart from the first base die, wherein the molding material is laterally between the second base die and the first base die. To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. In this case to duplicate the base die of Hung within a single semiconductor device package to expand the number of dies incorporated in the device and, thereby naturally result in the molding material 34 of Hung being located laterally between the second base die and the first base die.
Shen further teaches the second base die, ITP 120 comprising die-to-die interconnections 120I, paragraph 5. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the second base die to comprise die-to-die interconnections. One would have been motivated to do so in order to provide an additional interconnect level to supplement other electrical connections, paragraph 5.
Woychik et al. (US 2016/0049383), hereafter “Woychik 2016,” disclose a semiconductor device package including teaching a first metal functional connection, 140 (at left) in Figure 1, in the molding material 150, the first metal functional connection laterally adjacent to the first base die, a second metal functional connection 140 (at right) in the molding material, the second metal functional connection laterally adjacent to the second base die, wherein the first base die and the second base die are laterally between the first metal functional connection and the second metal
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[AltContent: textbox (1st base die)][AltContent: textbox (2nd base die)][AltContent: textbox (1st metal functional connection)][AltContent: textbox (2nd metal functional connection)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow]functional connection, paragraph 25, see also annotated Figure 1 below.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the second metal functional connection to be laterally adjacent to the second base die, wherein the first base die and the second base die are laterally between the first metal functional connection and the second metal functional connection. One would have been motivated to do so in order to interconnect and distribute power throughout the package, paragraph 26.
In reference to claim 2, Hung discloses the first metal functional connection 32 has a height at least equal to a thickness of the molding material 34, Figure 35B and paragraph 19.
In reference to claim 3, Hung discloses the first base die is in direct contact with the molding material, and wherein the first metal functional connection is in direct contact with the molding material, Figure 35B and paragraph 18.
In reference to claim 4, Hung discloses a layer comprising interconnections, the layer vertically beneath the first base die, paragraph 28.
In reference to claim 6, Shen discloses a third chip IC 110 electrically coupled to the second base die, paragraph 4.
In reference to claim 7, Hung does not disclose the first base die comprises a plurality of through interconnections.
Woychik teaches a base die 340 comprising a plurality of through interconnections 18, paragraph 43. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first base die to comprise a plurality of through interconnections. One would have been motivated to do so in order to connect the base die to other components, paragraph 29.
In reference to claim 8, Hung does not disclose the first base die is a passive die.
Woychik teaches a base die 340 is a passive die, paragraphs 40 and 44. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first base die to be a passive die. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B.
In reference to claim 9, Hung discloses the first base die is an active die, paragraph 12.
In reference to claim 11, Woychik discloses the upper surface of the dielectric material is co-planar with an upper surface of the second chip, Figure 6F-1 and paragraphs 46 and 59.
In reference to claim 12, Hung discloses the first chip 200 and the second chip 200 are entirely within a footprint of the first base die 100, Figure 35A.
In reference to claim 13, Hung discloses the first chip is a first node chip, and the second chip is a second node chip, the chips being inherently of a node.
In reference to claim 14, Hung discloses a plurality of conductive interconnections beneath the first base die, paragraphs 28 and 29.
In reference to claim 15, Hung discloses a chip package, with reference to Figures 35A and 35B, comprising:
a first base die 100 in a molding material 34, the base die comprising interconnections paragraphs 12, 18, and 33;
a first metal functional connection 32 in the molding material, the first metal functional connection laterally adjacent to the first base die, paragraph 16;
a first chip 200 electrically coupled to the first base die;
a second chip 200 electrically coupled to the first base die, wherein one of the first chip or the second chip has first terminations and second terminations, paragraph 25;
an underfill material 54 between the first chip and the first base die and between the second chip and the first base die, paragraph 26; and
a dielectric material 56 laterally adjacent to the first chip and the second chip, paragraph 26.
Hung does not disclose the first base die comprising die-to-die interconnections,
the second chip electrically coupled to the first chip by the die-to-die interconnections in the first base die,
the second terminations having a pitch less than a pitch of the first terminations, and wherein the second terminations are coupled to the die-to-die interconnections of the first base die, or
a second base die in the molding material, the second base die comprising die-to-die interconnections, and the second base die laterally spaced apart from the first base die, wherein the molding material is laterally between the second base die and the first base die, or
a second metal functional connection in the molding material, the second metal functional connection laterally adjacent to the second base die, wherein the first base die and the second base die are laterally between the first metal functional connection and the second metal functional connection.
Woychik discloses a chip package including teaching a first base die, 340 in Figure 6F-1, comprising die-to-die interconnections, a second chip 302, electrically coupled to a first chip 301 by the die-to-die interconnections in the base die 340, paragraphs 41 and 43. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first base die to comprise die-to-die interconnections, the second chip to be electrically coupled to the first chip by the die-to-die interconnections in the first base die. One would have been motivated to do so in order to provide die-to-die interconnection in a 3D-IC package, paragraphs 41 and 42.
Koide discloses a semiconductor device package including teaching wherein one of the first chip or the second chip, 30A in Figure 1, has first terminations 32b and second terminations 32a, the second terminations 32a having a pitch less than a pitch of the first terminations, and wherein the second terminations are coupled to the die-to die interconnections of the base die, Figure 2 and paragraphs 17, 20, and 22. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the second terminations to have a pitch less than a pitch of the first terminations, wherein the second terminations are coupled to the die-to-die interconnections of the first base die. One would have been motivated to do so in order to form wiring between chips that is the same as wiring within the chip in order to suppress a decrease in transmission efficiency between chips, paragraphs 27 and 30.
Shen discloses a semiconductor chip package including a first base die, ITP 120 in Figure 1, a second base die, ITP 120, in the molding material (not pictured), the second base die laterally spaced apart from the first base die, wherein the molding material is laterally between the second base die and the first base die, paragraph 4. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a second base die to be in the molding material, the second base die laterally spaced apart from the first base die, wherein the molding material is laterally between the second base die and the first base die. To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. In this case to duplicate the base die of Hung within a single semiconductor device package to expand the number of dies incorporated in the device and, thereby naturally result in the molding material 34 of Hung being located laterally between the second base die and the first base die.
Shen further teaches the second base die, ITP 120 comprising die-to-die interconnections 120I, paragraph 5. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the second base die to comprise die-to-die interconnections. One would have been motivated to do so in order to provide an additional interconnect level to supplement other electrical connections, paragraph 5.
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[AltContent: textbox (1st base die)][AltContent: textbox (2nd base die)][AltContent: textbox (1st metal functional connection)][AltContent: textbox (2nd metal functional connection)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow]Woychik 2016 discloses a semiconductor device package including teaching a first metal functional connection, 140 (at left) in Figure 1, in the molding material 150, the first metal functional connection laterally adjacent to the first base die, a second metal functional connection 140 (at right) in the molding material, the second metal functional connection laterally adjacent to the second base die, wherein the first base die and the second base die are laterally between the first metal functional connection and the second metal functional connection, paragraph 25, see also annotated Figure 1 below.
[AltContent: textbox (1st base die)]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the second metal functional connection to be laterally adjacent to the second base die, wherein the first base die and the second base die are laterally between the first metal functional connection and the second metal functional connection. One would have been motivated to do so in order to interconnect and distribute power throughout the package, paragraph 26.
In reference to claim 16, Hung discloses the first metal functional connection 32 has a height at least equal to a thickness of the molding material 34, Figure 35B and paragraph 19.
In reference to claim 17, Hung does not disclose the first base die comprises a plurality of through interconnections.
Woychik teaches a base die 340 comprising a plurality of through interconnections 18, paragraph 43. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first base die to comprise a plurality of through interconnections. One would have been motivated to do so in order to connect the base die to other components, paragraph 29.
In reference to claim 18, Hung does not disclose the first base die is a passive die.
Woychik teaches a base die 340 is a passive die, paragraphs 40 and 44. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first base die to be a passive die. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B.
In reference to claim 19, Hung discloses the first base die is an active die, paragraph 12.
In reference to claims 21 and 22, Hung does not disclose the dielectric material has an upper surface co-planar with an upper surface of the first chip and the second chip.
Woychik teaches a dielectric material, 322 in Figure 6F-1, having an upper surface co-planar with an upper surface of the first chip 301 and co-planar with an upper surface of the second chip 302, paragraphs 46 and 59. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the dielectric material to have an upper surface co-planar with an upper surface of the first chip and an upper surface of the second chip. One would have been motivated to do so in order to dissipate heat from an upper surface of the chip, paragraph 40.
In reference to claim 23, Hung discloses the first chip 200 and the second chip 200 are entirely within a footprint of the first base die 100, Figure 35A.
In reference to claim 24, Hung discloses the first chip is a first node chip, and the second chip is a second node chip, the chips being inherently of a node.
In reference to claim 25, Hung discloses a plurality of conductive interconnections beneath the first base die, paragraphs 28 and 29.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYAN R. JUNGE whose telephone number is (571)270-5717. The examiner can normally be reached M-F 8:00-4:30 CT.
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/BRYAN R JUNGE/Primary Examiner, Art Unit 2897
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