DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 16, 2025 has been entered.
Status of Claims
Claims 12, 15-21 examined.
Claims 1-11, 22-27 withdrawn
Claims 13-14 cancelled.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 12, 15-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 12. Claim 12 recites the limitation "the lower plugs" in the last line of the claim language. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of expediting examination and compact prosecution, examiner shall interpret “the lower plugs” to be “the lower plug layers”.
Claims 15-21 are rejected for dependence upon a 112(b) rejected instance claim.
Regarding claims 17-21. Claims 17-21 are rejected for the same analogous reasons as claim 12 above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 12, 16, 21 are rejected under 35 U.S.C. 103 as being unpatentable over Park (U.S. 2022/0085158), and Kim (U.S. 2016/0163594).
Regarding claim 12. Park discloses a method for fabricating a semiconductor device (FIG. 4G-4R), comprising:
forming a plurality of bit line structures (FIG. 4F, item BL) over a semiconductor substrate (FIG. 4F, item 11);
forming a first spacer (FIG. 4G, item 26) on both sidewalls ([0083], i.e. The bit line spacer 26 may be positioned on the sidewalls of the bit line contact plug 22 and the bit line 23) of each of the bit line structures (FIG. 4F, item BL);
forming plug isolation layers (FIG. 4H, item 27) and initial contact openings (FIG. 4L, item 31) that are positioned between the bit line structures (FIG. 4H, item BL) over the first spacer (FIG. 4H, item 26);
trimming ([0093], i.e. As described above, the opening 31 may be formed by depositing the sacrificial layer 27, forming the plug isolation portion 29, forming the plug isolation layer 30, and removing the sacrificial layer 27 sequentially) the plug isolation layers (FIG. 4K, item 27) and the initial contact openings (FIG. 4L, item 31) to form contact openings (FIG. 4M, item 31) which are wider ([0095]) than the initial contact openings (FIG. 4L, item 31) ([0095], i.e. Referring to FIGS. 4M and 5M, a portion of the plug isolation layer 30 and a portion of the bit line spacer 26 may be etched to increase the width of the opening 31.);
forming sacrificial spacers (FIG. 4O, item 33A) surrounding sidewalls of the contact openings (FIG. 4N, item 31);
forming lower plug layers (FIG. 4R, items 32 and 35) partially filling the contact openings ([0097] Referring to FIGS. 4N and 5N, a pad 32 may be formed to fill a portion of the recess 31R; [0113], i.e. Referring to FIGS. 4R and 5R, a first plug 35 filling the lower portion of the opening 31);
Park fails to explicitly disclose
removing the sacrificial spacers to form air gaps surrounding the lower plugs;
and selectively oxidizing exposed surfaces of the lower plug layers to form second spacers filling the air gaps and surrounding the lower.
However Kim teaches
removing the sacrificial spacers (FIG 1D, item 14) to form air gaps (FIG. 1E, item 16) surrounding the lower plugs (FIG. 1E, item 15C); and selectively oxidizing ([0036], i.e. Referring to FIG. 1G, after the thermal process 17 is performed, the air gap 16 may be filled with a third layer 18. The third layer 18 may include an insulating material. The third layer 18 may include silicon oxide.) exposed surfaces ([0036], i.e. the air gap 16) of the lower plug layers (FIG. 1F, item 15) to form second spacers (FIG. 1G, item 18) filling ([0036]) the air gaps (FIG. 1F, item 16) and surrounding the lower plugs (FIG. 1G, item 15).
Since Park and Kim teach contacts, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method for fabricating a semiconductor device as disclosed to modify Park with the teachings of removing the sacrificial spacers to form air gaps surrounding the lower plugs and selectively oxidizing exposed surfaces of the lower plug layers to form second spacers filling the air gaps and surrounding the lower as disclosed by Kim. The use of the air gap may be filled with a third layer in Kim provides for forming a void-free polysilicon layer pattern (Kim,[0035]).
Regarding claim 16. Park and Kim discloses all the limitations of the method of claim 12 above.
Park further discloses wherein the first spacer includes silicon nitride ([0085], i.e. The bit line spacer 26 may be formed of or include, for example, .. silicon nitride), and
Kim discloses the second spacer includes silicon oxide (FIG. 1G, item 18; [0036], i.e. The third layer 18 may include silicon oxide).
Regarding claim 21. Park and Kim discloses all the limitations of the method of claim 12 above.
Kim further discloses wherein the sacrificial spacer includes titanium nitride ([0031], i.e. the sacrificial spacer 14 includes titanium nitride).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Park ‘158 (U.S. 2022/0085158), and Kim ‘594 (U.S. 2016/0163594) as applied to claim 12 above, and further in view of Park et al (U.S. 2017/0005166).
Regarding claim 15. Park (‘158) and Kim discloses all the limitations of the method of claim 12 above.
Park (‘158) and Kim fail to explicitly disclose wherein the second spacer is formed to be thicker than the first spacer.
However, Park et al teaches wherein the second spacer ([0081], i.e. The second spacer layer 32A) is formed to be thicker ([0081], i.e. The second spacer layer 32A may have a larger thickness than the first spacer layer 30A) than the first spacer ([0081], i.e. the first spacer layer 30A)
Since Park (‘158), Kim and Park et al teach contact structures, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method for fabricating a semiconductor device as disclosed to modify Park (‘158) and Kim with the teachings of wherein the second spacer is formed to be thicker than the first spacer as disclosed by Park et al. The use of the second spacer layer may have a larger thickness than the first spacer layer in Park et al provides for a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures (Park et al, [0007]).
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Park (U.S. 2022/0085158), and Kim ‘594 (U.S. 2016/0163594) as applied to claim 12 above, and further in view of Kim et al (U.S. 2015/0214146).
Regarding claim 17. Park and Kim (‘594) discloses all the limitations of the method of claim 12 above.
Park and Kim (‘594) fail to explicitly disclose further comprising: forming upper plugs having a greater line width than the upper width of the lower plugs over the lower plugs.
However, Kim et al teaches further discloses further comprising: forming upper plugs (FIG. 6, item 170B) having a greater line width (FIG. 9, item W2 and W1; [0083]) than the upper width (FIG. 6, upper width of item 170A) of the lower plugs (FIG. 6, upper part of item 170A) over the lower plugs (FIG. 6, item 170A)
Since Park, Kim (‘594) and Kim et al teach contact structures, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method for fabricating a semiconductor device as disclosed to modify Park and Kim (‘594) with the teachings of further comprising: forming upper plugs having a greater line width than the upper width of the lower plugs over the lower plugs as disclosed by Kim et al. The use of the width of the second size W2 may be greater than the width of the first size W1 in Kim et al provides for enhancing a reliability of the semiconductor device (Kim et al, [0068]).
Regarding claim 18. Park, Kim (‘594), and Kim et al disclose all the limitations of the method of claim 17 above.
Kim et al further discloses wherein the lower plugs (FIG. 6, item 170a) and the upper plugs (FIG. 6, item 170B) include polysilicon ([0100], i.e. The contact conductive layer 170B may be formed of the same material as that of the contact plug 170A. For example, the contact conductive layer 170B may be formed of poly silicon).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Park (U.S. 2022/0085158), and Kim (U.S. 2016/0163594) as applied to claim 12 above, and further in view of Ahn et al (U.S. 2019/0097007).
Regarding claim 19. Park and Kim discloses all the limitations of the method of claim 12 above.
Kim and Park fail to explicitly disclose further comprising: forming upper plugs having a greater line width than the lower plugs over the lower plugs; forming a landing pad over the upper plugs; and forming a capacitor over the landing pad.
However, Ahn et al teaches Kim further discloses further comprising: forming upper plugs (FIG. 2A, item 154) having a greater line width ([0050], i.e. the width of the top surface 154T of the enlarged conductive plug 154 may be greater than a width of the top surface 150T of the lower conductive plug 150, in the X direction) than the lower plugs (FIG. 2A, item 150) over the lower plugs (FIG. 2A, item 150); forming a landing pad (FIG. 2A, item 190) over the upper plugs (FIG. 2A, item 154); and forming a capacitor over ([0178], i.e. the plurality of capacitor bottom electrodes, which may be electrically connected to the plurality of conductive landing pads LP, may be formed on the insulating film 180) the landing pad (FIG. 2A, item 190).
Since Park, Kim and Ahn et al teach contact structures, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method for fabricating a semiconductor device as disclosed to modify Park and Kim with the teachings of further comprising, forming upper plugs having a greater line width than the lower plugs over the lower plugs, forming a landing pad over the upper plugs; and forming a capacitor over the landing pad as disclosed by Ahn et al. The use of the width of the top surface of the enlarged conductive plug greater than a width of the top surface of the lower conductive plug in Ahn et al provides for integrated circuit devices having a structure which may ensure a sufficient contact area to support a plurality of contact plugs arranged between a plurality of wiring lines (Ahn et al, [0004]).
Regarding claim 20. Park and Kim discloses all the limitations of the method of claim 19 above.
Kim further discloses wherein the lower plugs (FIG. 2A, item 150) and the upper plugs (FIG. 2A, item 154) include polysilicon ([0050], i.e. Each of the lower conductive plug 150 and the enlarged conductive plug 154 may include doped polysilicon), and the landing pad (FIG. 2A, item 190; [0058], i.e. the conductive landing pad 190 includes a conductive barrier film and a conductive layer) includes a metal material ([0058], i.e. The conductive barrier film may include a Ti/TiN stacked structure).
Response to Arguments
Applicant's arguments filed December 16, 2025 have been fully considered but they are not persuasive.
On page 14 of applicant’s remarks, applicant appears to argue that Park, Kim do not teach the claim limitation of the selectively oxidizing exposed surfaces of the lower plug layers to form second spacers filling the air gaps and surrounding the lower.
Examiner respectfully disagrees with applicant’s assertion.
Examiner respectfully points out that Park and Kim discloses applicant’s amended claim 12 limitations.
On page 14 of applicant’s remarks, applicant appears to argue that the combination of Park, Kim, and Ahn fail to disclose the features of the claim 12 and supported by cancelled claim 13 and therefore allowable.
Examiner makes notes that claim 13 is cancelled which was rejected for dependence upon a 112(a) and 112(b) rejected instance claim in the prior office action.
Examiner respectfully further points out that Applicant did not include all the limitations of canceled claim 13, such as for the reasons as explained above for claims 12 and 13.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jeon et al (U.S. 20220406789) discloses methods of manufacturing semiconductor devices.
Yoon (U.S. 2019/0103302) discloses a method for fabricating a semiconductor device.
Lee et al (U.S. 2014/0175659) discloses semiconductor device including air gaps and method of fabricating the same.
Lee et al (U.S. 2014/0179101) discloses semiconductor device including air gaps and method of fabricating the same.
Joung et al (U.S. 2014/0179102) discloses semiconductor device including air gaps and method of fabricating the same.
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/S.E.B./ Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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