DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
In view of Applicant’s amendments, the prior drawing objections are withdrawn.
Claim Rejections - 35 USC § 112
In view of Applicant’s amendments, the prior 112 based rejections are withdrawn.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-2, 5-7, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2021/0082914), of record.
(Re Claim 1) Lee teaches a semiconductor device comprising: an active pattern (FA; Fig. 15A) disposed on a substrate (110; Fig. 15A); a source/drain pattern (140; Fig. 15A) disposed on the active pattern; a channel pattern (plurality of NS; Fig. 15A) connected to the source/drain pattern, wherein the channel pattern comprises semiconductor patterns (each NS1, NS2, and NS3; Fig. 15A) stacked on each other and spaced apart from each other (Fig. 15A); and a gate electrode (120M; Fig. 15A) disposed on the channel pattern.
Lee does not teach verbatim the remainder of the claimed invention.
However, Lee does teach conformal deposition of the gate electrode 120M and a layer 128 in a recess GS formed after removal of layers DGL and DGI (Fig. 13B, 14A, and 15A, ¶105).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious for the gate electrode to appear in the plan view of Fig. 13B within the space formerly occupied up by DGL and DGI while also having a trapezoidal shape due to conformal deposition on the layer 132, as newly deposited layers will conform to the shape of underlying layers.
With the above understood, Lee teaches a semiconductor device wherein the gate electrode includes:
a gate electrode (120M; Fig. 15A) disposed on the channel pattern and extending in a first direction (Y axis from the top to the bottom; Fig. 13B markup); and
a gate spacer (130; Fig. 13B) disposed in on a sidewall (left) of the gate electrode; a channel neighboring part (Fig. 13B markup) adjacent to a first sidewall (Fig. 13B markup) of a first semiconductor pattern (NS3; Fig. 13B) of the stacked semiconductor patterns; and a body part (Fig. 13B markup) spaced apart from the first semiconductor pattern, wherein the channel neighboring part is disposed between the body part and the first semiconductor pattern (Fig. 13B markup),
wherein the source/drain pattern comprises:
a first semiconductor layer (142; Fig. 13B) in contact with the first semiconductor pattern; and
a second semiconductor layer (144; Fig. 13B) disposed on the first semiconductor layer,
wherein the channel neighboring part is spaced apart from the source/drain pattern (Fig. 13B markup), and the gate spacer is disposed between the channel neighboring part and the source/drain pattern (Fig. 13B markup),
wherein the gate spacer is in contact with a portion of the first semiconductor layer that protrudes outwardly from the first sidewall of the first semiconductor pattern in the first direction (Fig. 13B markup showing protrusion),
wherein the first sidewall of the first semiconductor pattern has a first width along a second direction perpendicular to the first direction (the widths are immediately below their respective labels and indicated by lines terminating in arrow heads; Fig. 13B markup), wherein the channel neighboring part has a second width along the second direction less than the first width (Fig. 13B markup), and wherein the body part has a third width greater than the second width (Fig. 13B).
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(Re Claim 2) Modified Lee teaches the semiconductor device of claim 1, wherein the body part includes a second sidewall extending substantially perpendicularly to the first sidewall (Fig. 13B markup).
(Re Claim 5) Modified Lee teaches a semiconductor device of claim 4, further comprising: a gate insulating layer (128; Fig. 15A) disposed between the first semiconductor pattern and the gate electrode (deposition location is between 132 and the black outline of the gate electrode as seen in the Fig. 13B markup), wherein the gate insulating layer covers the first sidewall of the first semiconductor pattern (Fig. 13B markup), and wherein the gate spacer covers at least a portion of the first sidewall of the first semiconductor pattern (Fig. 13B).
(Re Claim 6) Modified Lee teaches semiconductor device of claim 4, wherein the gate spacer comprises: a first spacer (132, corresponding to 80+94 of Chen; Fig. 13B); and a second spacer (134, corresponding to 86 of Chen; Fig. 13B) disposed on the first spacer, wherein the first spacer is in contact with the first semiconductor layer (Fig. 13B), and wherein the second spacer is in contact with the second semiconductor layer (Fig. 13B).
(Re Claim 7) Modified Lee teaches the semiconductor device of claim 1, wherein the second width of the channel neighboring part decreases as the first semiconductor pattern is approached (Fig. 13B markup and discussion in view of Chen in the rejection of claim 1).
(Re Claim 9) Modified Lee teaches the semiconductor device of claim 1, wherein the gate electrode fills a space (GS+GSS as seen in Fig. 14B; Fig. 15A) between the semiconductor patterns stacked on each other.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2021/0082914), Chen et al. (US 2021/0359109), and Cheon et al. (US 2019/0312049), all of record, and Cheng (US 2021/0375698), as applied to claim 1 above, and further in view of Kim et al. (US 2021/0118880) of record.
(Re Claim 10) Modified Lee teaches a semiconductor device of claim 1, further comprising: an active contact (166; Fig. 2A) connected to the source/drain pattern.
Modified Lee does not explicitly demonstrate a gate contact connected to the gate electrode; and a first metal layer comprising interconnection lines electrically connected to the active contact and the gate contact, respectively.
Kim teaches a gate contact (GC; Fig. 2D) connected to a gate electrode (GE; Fig. 2D); and a first metal layer (IL+130; Fig. 2D) comprising interconnection lines (IL; 2D) electrically connected to an active contact (AC; Fig. 2C) and the gate contact, respectively (¶51).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form a gate contact connected to the gate electrode 120M of modified Lee, and a first metal layer comprising interconnection lines electrically connected to the active contact and the gate contact, respectively, of modified Lee, as taught by Kim. Lee teaches that a first metal layer and a via may be connected to the active contact 166 and the gate electrode 120 (Lee: ¶59) and so already contemplates additional connections to interact with the semiconductor device, while the gate contact, first metal layer, and associated electrical connections taught by Kim will have the predictable effect of providing electrical connections to the source/drain and gate of the transistor device of modified Lee, allowing for useful interaction. See KSR, 550 U.S. at 416, 82 USPQ2d at 1395.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2021/0082914) as applied to claim 1 above, and further in view of Chen et al. (US 2021/0359109), of record.
(Re Claim 8) Modified Lee teaches the semiconductor device of claim 1, but has not been shown to teach the semiconductor device wherein the second width of the channel neighboring part decreases and then increases toward the first semiconductor pattern.
Chen teaches an embodiment of a gate spacer configuration (94+80+86; “The sidewall 95 shown in Fig. 17D includes a convex region”; Fig. 17D, ¶68) where, in a plan view of the semiconductor device (compare Fig. 16B, 16C, and 17A-17D) after conformal deposition of a gate insulating layer and gate electrode, a second width of a channel neighboring part of a deposited gate electrode (98; Fig. 18C) decreases and then increases as a first semiconductor pattern (58; Fig. 18C) is approached.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the gate spacers of Lee in the manner taught by Chen, as these spacer geometries can be applied to nanostructure transistors (Chen: ¶19), and the spacer geometry of Fig. 17D allows for parasitic capacitance between the gate electrode 120M and the source/drain patterns 140 to be reduced, improving device performance (Chen: ¶¶61, 68).
Conformal deposition of the gate electrode results in the pattern of modified Lee’s gate spacers transferring to the gate electrode, such that second sidewall of the channel neighboring part includes a concave surface that protrudes towards an inner region of the channel neighboring part along the second direction (Compare Chen’s Fig. 17D with Lee’s Fig. 13B).
This concave surface protrusion results in the second width of the channel neighboring part decreasing and then increasing towards the first semiconductor pattern (Chen: Fig. 17D).
Claims 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2021/0082914), and Chang et al. (US 2017/0179117), both of record.
(Re Claim 11) Lee teaches a semiconductor device comprising: an active pattern (FA; Fig. 15A) disposed on a substrate (110; Fig. 15A); a source/drain pattern (140; Fig. 15A) disposed on the active pattern; a channel pattern (plurality of NS; Fig. 15A) connected to the source/drain pattern, wherein the channel pattern comprises semiconductor patterns (each NS1, NS2, and NS3) stacked on each other and spaced apart from each other; and a gate electrode (120M; Fig. 15A) disposed on the channel pattern and extending in a direction (Z direction; Fig. 15A).
Lee does not teach verbatim the remainder of the claimed invention.
However, Lee does teach conformal deposition of the gate electrode 120M and a layer 128 in a recess GS formed after removal of layers DGL and DGI (Fig. 13B, 14A, and 15A, ¶105).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious for the gate electrode to appear in the plan view of Fig. 13B within the space formerly occupied up by DGL and DGI while also having a trapezoidal shape due to conformal deposition on the layer 132, as newly deposited layers will conform to the shape of underlying layers.
With the above understood, Lee teaches the semiconductor device comprising:
a gate spacer (130; Fig. 13B) disposed on a sidewall (left) of the gate electrode;
wherein the gate electrode includes: a first channel neighboring part adjacent to a first sidewall (WT; Fig. 2C) of a first semiconductor pattern (NS3 on the right; Fig. 1, and 2C) of the stacked semiconductor patterns along a second direction (Z axis from top to bottom; Fig. 2C); and a first body part (Fig. 2C markup) spaced apart from the first semiconductor pattern, wherein the first channel neighboring part is disposed between the first body part and the first semiconductor pattern (Fig. 2C markup),
a second channel neighboring part adjacent to a second semiconductor pattern (NS3 on the left; Fig. 1 and 2C; Fig. 13B markup) of the stack semiconductor patterns along the first direction (Y direction from top to bottom; Fig. 13B); and
a second body part (Fig. 13B markup) spaced apart from the second semiconductor pattern, wherein the second channel neighboring part is disposed between the second body part and the second semiconductor pattern (Fig. 13B markup),
wherein the first channel neighboring part includes a second sidewall (Fig. 2C markup), wherein the first body part includes a third sidewall extending substantially perpendicularly to the first sidewall (Fig. 2C markup),
wherein the second semiconductor pattern includes a fourth sidewall facing the second channel neighboring part in the first direction (Fig. 13B markup),
wherein the source/drain pattern comprises:
a first semiconductor layer (142; Fig. 13B) in contact with the first semiconductor pattern; and
a second semiconductor layer (144; Fig. 13B) disposed on the first semiconductor layer,
wherein the second channel neighboring part is spaced apart from source/drain pattern (Fig. 13B markup), and the gate spacer is disposed between the second channel neighboring part and the source/drain pattern (Fig. 13B markup), and
wherein the gate spacer is in contact with a portion of the first semiconductor layer that protrudes outwardly from the fourth sidewall of the second semiconductor pattern in the first direction (Fig. 13B markup showing protrusion).
Lee does not explicitly teach the semiconductor device wherein the first channel neighboring part includes a second sidewall extending diagonally with respect to the first sidewall, and wherein an angle between the first sidewall and the second sidewall ranges from about 30° to about 80°.
Chang teaches tuning the angle between a second sidewall (172s; Fig. 3B) and a bottom sidewall (172b; Fig. 3B) of a gate electrode (172; Fig. 3B, ¶34).
A PHOSITA would find it obvious to form the second sidewall of the first channel neighboring part of Lee such that it extends diagonally with respect to the first sidewall after adopting the diagonal sidewall configuration of Chang, as forming a gate spacer between the gate electrode and source/drain patterns reduces parasitic capacitance or leakage current, and shaping the profile of sacrificial material used to form the opening of the gate electrode allows for device electrical properties, such as breakdown voltage, to be tuned (Chang: ¶¶9, 40; Chen: ¶16). See also In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.).
Furthermore, the angle between the first sidewall and the second sidewall when forming the gate electrode according to Chang, given the angles depicted in Chang’s Fig. 3B, shows an angle within the claimed range (note the inclination of 172s of Chang). See In re Scherl, 156 F.2d 72, 74-75, 70 USPQ 204, 205-206 (CCPA 1946) (prior art showed an angle in a groove of up to 90° and an applicant claimed an angle of no less than 120°) and In re Aslanian, 590 F.2d 911, 200 USPQ 500 (CCPA 1979).
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(Re Claim 12) Modified Lee teaches the semiconductor device of claim 11, wherein a width the first channel neighboring part decreases toward the first semiconductor pattern (due to the incline introduced through Chang’s teachings).
(Re Claim 13) Modified Lee teaches the semiconductor device of claim 11, wherein the gate spacer (130; Fig. 13B) is disposed on the second sidewall and the third sidewall, and the first channel neighboring part is spaced apart from the source/drain pattern (Fig. 2C markup), and wherein the gate spacer is disposed between the first channel neighboring part and the source/drain pattern (Fig. 2C markup).
(Re Claim 14) Modified Lee teaches the semiconductor device of claim 13, further comprising: a gate insulating layer (128; Fig. 15A) disposed between the first semiconductor pattern and the gate electrode (deposition location is between 132 and the black outline of the gate electrode as seen in the Fig. 13B markup), wherein the gate insulating layer covers the first sidewall of the first semiconductor pattern (Fig. 13B markup), and wherein the gate spacer covers at least a portion of the first sidewall of the first semiconductor pattern (Fig. 13B markup).
(Re Claim 15) Modified Lee teaches the semiconductor device of claim 13, wherein a thickness of the gate spacer disposed on the second sidewall of the first channel neighboring part is greater than a thickness of the gate spacer on the third sidewall of the first body part (due to the incline of the second sidewall; Fig. 13B markup).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2021/0082914) as applied to claim 1 above, and further in view of Chen et al. (US 2021/0359109), Cheon et al. (US 2019/0312049), and Cheng (US 2021/0375698), all of record.
(Re Claim 21) Modified Lee teaches the semiconductor device of claim 1, but has not been shown to teach the semiconductor device wherein in a plan view of the semiconductor device at a level of the first semiconductor pattern, the channel neighboring part includes a third sidewall that includes a curved concave surface that protrudes toward an inner region of the channel neighboring part along the second direction.
Chen teaches an embodiment of a gate spacer configuration (94+80+86; “The sidewall 95 shown in Fig. 17D includes a convex region”; Fig. 17D, ¶68) where, in a plan view of the semiconductor device (compare Fig. 16B, 16C, and 17A-17D) after conformal deposition of a gate insulating layer and gate electrode, a second width of a channel neighboring part of a deposited gate electrode (98; Fig. 18C) decreases and then increases as a first semiconductor pattern (58; Fig. 18C) is approached.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the gate spacers of Lee in the manner taught by Chen, as these spacer geometries can be applied to nanostructure transistors (Chen: ¶19), and the spacer geometry of Fig. 17D allows for parasitic capacitance between the gate electrode 120M and the source/drain patterns 140 to be reduced, improving device performance (Chen: ¶¶61, 68).
Conformal deposition of the gate electrode results in the pattern of modified Lee’s gate spacers transferring to the gate electrode, such that the third sidewall of the channel neighboring part includes a concave surface that protrudes towards an inner region of the channel neighboring part along the second direction (Compare Chen’s Fig. 17D with Lee’s Fig. 13B mark).
Modified Lee has yet to explicitly teach a device wherein the concave surface of the channel neighboring part’s third sidewall is curved.
Cheon teaches smoothing the surface of a dielectric (204; Fig. 4 and 5) causing the top surface to be curved.
Chen additionally shows an embodiment where a smooth gate spacer sidewall is attained in Fig. 17B.
A PHOSITA would find it obvious to smooth the dielectric gate spacers of modified Lee, in the manner of smoothing performed through wet etching in Cheon, thereby smoothing the sharp points of the gate spacer configuration of the embodiment shown in Chen’s Fig. 17D, in order to reduce the concentration of an electric field originating from the gate electrode, (Chen: “The shape of the corner spacers 94 may be controlled by controlling the shape of the corner regions 91, the thickness of the dielectric layer 92, and/or the parameters of the etching process that etches the dielectric layer 92.“; ¶62; Cheon: ¶¶83, 127), and to increase the volume available to deposit the metal fill forming the gate electrode, thereby reducing gate resistance (Cheng: ¶17).
Conformal deposition of the gate electrode then results in the pattern of modified Lee’s gate spacers transferring to the gate electrode, in view of Chen and smoothing from Cheon, such that the second sidewall of the channel neighboring part includes a curved concave surface that protrudes toward an inner region of the channel neighboring part.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2021/0082914), and Chang et al. (US 2017/0179117), both of record, as applied to claim 11 above, and further in view of Chen et al. (US 2021/0359109), Cheon et al. (US 2019/0312049), and Cheng (US 2021/0375698), all of record.
(Re Claim 22) Modified Lee teaches the semiconductor device of claim 11, but has not been shown to teach wherein in a plan view of the semiconductor device at a level of the second semiconductor pattern, the second channel neighboring part includes a fifth sidewall that includes a curved concave surface that protrudes toward an inner region of the second channel neighboring part along a third direction perpendicular to the first direction and the second direction.
Chen teaches an embodiment of a gate spacer configuration (94+80+86; “The sidewall 95 shown in Fig. 17D includes a convex region”; Fig. 17D, ¶68) where, in a plan view of the semiconductor device (compare Fig. 16B, 16C, and 17A-17D) after conformal deposition of a gate insulating layer and gate electrode, a second width of a channel neighboring part of a deposited gate electrode (98; Fig. 18C) decreases and then increases as a first semiconductor pattern (58; Fig. 18C) is approached.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the gate spacers of Lee in the manner taught by Chen, as these spacer geometries can be applied to nanostructure transistors (Chen: ¶19), and the spacer geometry of Fig. 17D allows for parasitic capacitance between the gate electrode 120M and the source/drain patterns 140 to be reduced, improving device performance (Chen: ¶¶61, 68).
Conformal deposition of the gate electrode results in the pattern of modified Lee’s gate spacers transferring to the gate electrode, such that the fifth sidewall of the second channel neighboring part includes a concave surface that protrudes towards an inner region of the second channel neighboring part along a third direction perpendicular to the first direction and the second direction (left to right in Lee’s Fig. 13B; also, Compare Chen’s Fig. 17D with Lee’s Fig. 13B mark).
Modified Lee has yet to explicitly teach a device wherein the concave surface of the second channel neighboring part’s fifth sidewall is curved.
Cheon teaches smoothing the surface of a dielectric (204; Fig. 4 and 5) causing the top surface to be curved.
Chen additionally shows an embodiment where a smooth gate spacer sidewall is attained in Fig. 17B.
A PHOSITA would find it obvious to smooth the dielectric gate spacers of modified Lee, in the manner of smoothing performed through wet etching in Cheon, thereby smoothing the sharp points of the gate spacer configuration of the embodiment shown in Chen’s Fig. 17D, in order to reduce the concentration of an electric field originating from the gate electrode, (Chen: “The shape of the corner spacers 94 may be controlled by controlling the shape of the corner regions 91, the thickness of the dielectric layer 92, and/or the parameters of the etching process that etches the dielectric layer 92.“; ¶62; Cheon: ¶¶83, 127), and to increase the volume available to deposit the metal fill forming the gate electrode, thereby reducing gate resistance (Cheng: ¶17).
Conformal deposition of the gate electrode then results in the pattern of modified Lee’s gate spacers transferring to the gate electrode, in view of Chen and smoothing from Cheon, such that the fifth sidewall of the second channel neighboring part includes a curved concave surface that protrudes toward an inner region of the second channel neighboring part.
Response to Arguments
Applicant's arguments filed 11/19/2025 have been fully considered but they are not persuasive.
Applicant appears to argue a narrower interpretation of “protrudes outwardly” than justified by the specification and claim language. Under a broadest reasonable interpretation (BRI), words of the claim must be given their plain meaning, unless such meaning is inconsistent with the specification. The plain meaning of a term means the ordinary and customary meaning given to the term by those of ordinary skill in the art at the relevant time. “Protrudes” means to stick out from something, and “outwardly” just means toward the outside. As the portion of the first semiconductor layer identified in the claim rejections respectively protrudes, that is sticks out from, the first and fourth sidewall, and does so externally, the gate spacer is in contact with a portion of the first semiconductor layer as claimed.
The remainder of Applicant’s arguments are moot.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898