DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/25/2025 has been entered.
Status of the claims
Claims 1-11, 13, 15-17 and 19 are pending in this application. Claims 12, 18 and 20 were previously withdrawn. Claim 14 is cancelled by the applicant, as filed on 11/25/2025.
Information Disclosure Statement
Acknowledgement is made of Applicant's Information Disclosure Statement (IDS) from PTO-1449 filed on 12/15/2025. The IDS has been considered.
Drawings
Prior drawing objection related to Claim 1 is withdrawn in view of newly amended Figs. 8 and 9, filed on 11/25/2025.
Prior drawing objection related to Claim 2 is withdrawn in view of applicant’s remarks in the reply filed on 11/25/2025.
Prior drawing objection related to Claim 14 is withdrawn in view of cancellation of the claim.
Claim Rejections - 35 USC § 112
Prior rejection of Claim 14 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, is withdrawn in view of applicant’s cancellation of the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 7-11, 13, 15, 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2012/0146177 A1), and further in view of Baek et al. (US 2008/0128882 A1) and Chen et al. (US 2019/0067244 A1).
Re Claim 1, Choi recites a semiconductor device assembly, comprising:
a monolithic silicon structure (364, Fig. 13, where 172 is Silicon substrate, see paras [0051] and para [0117]) having a second dielectric layer (208, Fig. 3, para [0071]) defining a lower surface (212, Fig. 13, paras [0074]), the monolithic silicon structure (364) including a cavity (marked “cavity-1” in annotated Fig. 13 below) extending from the lower surface into a body of the monolithic silicon structure (see Fig. 13);
a second semiconductor device (lower-146, Fig. 13, para [0047]) disposed in the cavity (cavity-1), the second semiconductor device including:
a second plurality of interconnects (lower-160, Fig. 13, para [0049]) on an upper surface of the second semiconductor device (upper-156, Fig. 13, para [0048]), each operatively coupled to a corresponding TSV of a plurality of TSVs (199, Fig. 13, para [0060]) extending from the cavity (cavity-1) to a top surface of the monolithic silicon structure (see Fig. 13); and
a third semiconductor device (upper-146, Fig. 13, para [0047]) disposed over the monolithic silicon structure (364) and including a third plurality of interconnects (upper-160, Fig. 13, para [0049]), each operatively coupled to a corresponding one of the plurality of TSVs (199, see Fig. 13).
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Choi does not explicitly show the first semiconductor device. However, Choi teaches that the bumps 362 connects the semiconductor structure to another semiconductor device (para [0114]). Thus, one of ordinary skill would look into related art to learn the connections to an external semiconductor device. Related art, Baek teaches a similar semiconductor structure (110+130, Fig. 1, paras [0023] - [0024]) connected to another semiconductor device like a package substrate (150, Fig. 1, para [0023]). Additionally, Chen discloses that a top layer of a package substrate (101, Fig. 2, para [0017]) can be a redistribution structure consisting of a dielectric layer (101b, Fig. 2, para [0019]) defining a top surface (top surface of 101, Fig. 2) with embedded conductive elements (101c, Fig. 2, para [0020]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the package substrate to the semiconductor structure of Choi, according to the disclosures of Choi, Baek and Chen. A package substrate helps in providing the physical and electrical infrastructure of the semiconductor structure and allows stacking of devices on top of it, and furthermore helps in connecting and routing signals.
Thus, Choi modified by Baek and Chen teaches the following:
a first semiconductor device (150, Fig. 1, para [0023], Baek) including a first dielectric layer (101b, Fig. 2, para [0019], Chen) and a plurality of electrical contacts (152, Fig. 1, para [0029], Baek) on an upper surface (upper surface of 150, Fig. 1, Baek) thereof;
a monolithic silicon structure (364, Fig. 13, Choi) having a lower surface (212, Fig. 13, Choi) in contact (electrical contact) with the upper surface of the first semiconductor device (upper surface of 150, Fig. 1, Baek).
Additionally, Choi modified by Baek and Chen does not teach a first plurality of interconnects on the second semiconductor device (lower-146, Fig. 13, Choi). However, Chen teaches a semiconductor device 103 (Fig. 2, paras [0032] - [0034]), where the device is connected to the lower substrate (101, Fig. 2, para [0015]) through a first plurality of interconnects (108, Fig. 2, para [0052]), and also connected to the upper interconnect structure (105, Fig. 2, para [0015]) through a second plurality interconnects (103g, Fig. 2, paras [0041] - [0043]). Thus, the semiconductor device will be electrically connected both to the substrate below and the device structure above, which not only helps in multifunctionality as it can aide in functions associated with both the top and the bottom devices but also improves process and signal flow as the electrical signals can have a direct channel between top and bottom devices through the semiconductor device.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the first plurality of interconnects as disclosed by Chen to the second semiconductor device of Choi, because the second semiconductor device can then be controlled both by the first semiconductor device below and the device structure above, which not only helps in multifunctionality but also improves process and signal flow.
Thus, Choi modified by Baek and Chen teaches the following:
a second semiconductor device (lower-146, Fig. 13, Choi) disposed in the cavity (cavity-1, Choi), the second semiconductor device including:
a first plurality of interconnects (108, Fig. 2, para [0052], Chen), each operatively coupled to a corresponding one of the plurality of electrical contacts (101c-1/Fig. 2/para [0021]/Chen which is similar to 152/Baek),
a second plurality of interconnects (lower-160, Fig. 13, Choi) on an upper surface of the second semiconductor device (upper-156, Fig. 13, para [0048], Choi) opposite the first plurality of interconnects (108, Chen).
Furthermore, Choi does not explicitly teach that the cavity of the monolithic structure has a rectangular cross-sectional shape. However, Choi discloses that the sidewalls of the cavities can be angled or curved (para [0054]). Related art, Baek teaches that the recess 112 (Fig. 2, para [0024]) of the monolithic substrate 110 (Fig. 2, para [0024]) can have rectangular cross-sectional shape as envisioned by Choi. It would have been prima facie obvious to one of ordinary skill in the art to realize that the cross-sectional shape of the cavity is a design choice as disclosed by Choi, and can have a rectangular cross-section shape as disclosed by Baek. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Re Claim 3, Choi modified by Baek and Chen recites the semiconductor device assembly of claim 1, wherein the upper surface of the first semiconductor device (upper surface of 150, Fig. 1, Baek) includes a plurality of thermal contacts (160, Fig. 1, para [0026], Baek) in direct contact with the lower surface of the monolithic silicon structure (364, Choi).
Re Claim 4, Choi modified by Baek and Chen recites the semiconductor device assembly of claim 3, wherein the lower surface of the monolithic silicon structure includes (364, Choi) a corresponding plurality of thermal pads (362, Fig. 13, para [0114], Choi), each in direct contact with a corresponding one or more of the plurality of thermal contacts (160, Baek).
Re Claim 5, Choi modified by Baek and Chen recites the semiconductor device assembly of claim 4, wherein each of the plurality of thermal pads is coupled to the corresponding one or more of the plurality of thermal contacts by a metal-metal bond (see para [114] of Choi and para [0026] of Baek).
Re Claim 7, Choi modified by Baek and Chen recites the semiconductor device assembly of claim 1, wherein the cavity is a first cavity (cavity-1, Choi), the monolithic structure (364, Choi) includes a second cavity extending from the lower surface into the body of the monolithic silicon structure (marked “cavity-2” in annotated Fig. 13 above), and further comprising a fourth semiconductor device disposed in the second cavity (lower-144, Fig. 13, para [0047]) and including a fourth plurality of interconnects (2nd set of 108, Fig. 2, para [0052], Chen, see discussion in claim 1), each operatively coupled to a corresponding one of the plurality of electrical contacts (2nd set of 101c-1/Fig. 2/para [0021]/Chen which is similar to 2nd set of 152/Baek, see discussion in claim 1).
Re Claim 8, Choi modified by Baek and Chen recites the semiconductor device assembly of claim 1, wherein the second semiconductor device includes a vertical stack of electrically coupled memory devices (Choi teaches that the semiconductor device 146 can be a plurality of dies which can be memory dies, see paras [0047] - [0048]).
Re Claim 9, Choi modified by Baek and Chen recites the semiconductor device assembly of claim 1, wherein one or more of the upper surface of the first semiconductor device and the lower surface of the monolithic silicon structure include a redistribution layer (RDL 201, Fig. 13, para [0061], Choi).
Re Claim 10, Choi recites a semiconductor device assembly, comprising:
a monolithic silicon structure (364, Fig. 13, where 172 is Silicon substrate, see paras [0051] and para [0117]) having a lower surface (212, Fig. 13, paras [0074]) defined by a second dielectric layer (208, Fig. 3, para [0071]), the monolithic silicon structure (364) including a cavity (marked “cavity-1” in annotated Fig. 13 above) extending from the lower surface into a body of the monolithic silicon structure (see Fig. 13);
a second semiconductor device (lower-146, Fig. 13, para [0047]) disposed in the cavity (cavity-1) such that a back surface and a plurality of sidewalls of the second semiconductor device are completely enclosed within the cavity (see Fig. 13); and
a third semiconductor device (upper-146, Fig. 13, para [0047]) disposed on a top surface of the monolithic silicon structure (364),
wherein the monolithic silicon structure includes a plurality of TSVs (199+164, Fig. 13, paras [0060] and [0049]) extending between the cavity (cavity-1) and the top surface of the monolithic silicon structure (364, see Fig. 13) and electrically coupling (see Fig. 13) the second semiconductor device (lower-146) and the third semiconductor device (upper-146).
Choi does not explicitly show the first semiconductor device. However, Choi teaches that the bumps 362 connects the semiconductor structure to another semiconductor device (para [0114]). Thus, one of ordinary skill would look into related art to learn the connections to an external semiconductor device. Related art, Baek teaches a similar semiconductor structure (110+130, Fig. 1, paras [0023] - [0024]) connected to another semiconductor device like a package substrate (150, Fig. 1, para [0023]). Additionally, Chen discloses that a top layer of a package substrate (101, Fig. 2, para [0017]) can be a redistribution structure consisting of a dielectric layer (101b, Fig. 2, para [0019]) defining a top surface (top surface of 101, Fig. 2) with embedded conductive elements (101c, Fig. 2, para [0020]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the package substrate to the semiconductor structure of Choi, according to the disclosures of Choi, Baek and Chen. A package substrate helps in providing the physical and electrical infrastructure of the semiconductor structure and allows stacking of devices on top of it, and furthermore helps in connecting and routing signals.
Thus, Choi modified by Baek and Chen teaches the following:
a first semiconductor device (150, Fig. 1, para [0023], Baek) including an upper surface (upper surface of 150, Fig. 1, Baek) defined by a first dielectric layer (101b, Fig. 2, para [0019], Chen);
a monolithic silicon structure (364, Fig. 13, Choi) having a lower surface (212, Fig. 13, Choi) in contact (electrical contact) with the upper surface of the first semiconductor device (upper surface of 150, Fig. 1, Baek)
Additionally, Choi modified by Baek and Chen does not teach that the second semiconductor device is directly coupled to the first semiconductor device. However, Chen teaches a semiconductor device 103 (Fig. 2, paras [0032] - [0034]), where the device is connected to the lower substrate (101, Fig. 2, para [0015]) through a first plurality of interconnects (108, Fig. 2, para [0052]), and also connected to the upper interconnect structure (105, Fig. 2, para [0015]) through a second plurality interconnects (103g, Fig. 2, paras [0041] - [0043]). Thus, the semiconductor device will be electrically connected both to the substrate below and the device structure above, which not only helps in multifunctionality as it can aide in functions associated with both the top and the bottom devices but also improves process and signal flow as the electrical signals can have a direct channel between top and bottom devices through the semiconductor device.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Choi modified by Baek and Chen such that the second semiconductor device is directly coupled to the first semiconductor device, as taught by Chen, because then the semiconductor device can be controlled both by the first semiconductor device below and the device structure above, which not only helps in multifunctionality but also improves process and signal flow.
Furthermore, Choi does not explicitly teach that the cavity of the monolithic structure has a rectangular cross-sectional shape. However, Choi discloses that the sidewalls of the cavities can be angled or curved (para [0054]). Related art, Baek teaches that the recess 112 (Fig. 2, para [0024]) of the monolithic substrate 110 (Fig. 2, para [0024]) can have rectangular cross-sectional shape as envisioned by Choi. It would have been prima facie obvious to one of ordinary skill in the art to realize that the cross-sectional shape of the cavity is a design choice as disclosed by Choi, and can have a rectangular cross-section shape as disclosed by Baek. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Re Claim 11, Choi modified by Baek and Chen recites the semiconductor device assembly of claim 10, wherein the third semiconductor device (upper-146, Fig. 13, Choi) is encapsulated by a mold material (211, Fig. 13, para [0074], Choi).
Re Claim 13, Choi modified by Baek and Chen recites the semiconductor device assembly of claim 10, wherein a back surface of the second semiconductor device (lower-146, Fig. 13, Choi) is adhered to an interior surface of the cavity (see Fig. 13, Choi) by an adhesive material (211, Fig. 13, para [0074], Choi).
Re Claim 15, Choi modified by Baek and Chen recites the semiconductor device assembly of claim 10, wherein the second semiconductor device (lower-146, Fig. 13, Choi) has a bonding surface (bottom surface of lower-146, Choi) coplanar (see Fig. 13, Choi) with the lower surface of the monolithic silicon structure (212, Fig. 13, Choi).
Re Claim 17, Choi recites a semiconductor device assembly, comprising:
a second semiconductor device (lower-146, Fig. 13, para [0047]);
a monolithic silicon structure (364, Fig. 13, where 172 is Silicon substrate, see paras [0051] and para [0117]) having a second dielectric layer (208, Fig. 3, para [0071]) defining a lower surface (212, Fig. 13, paras [0074]), the monolithic silicon structure (364) including a cavity (marked “cavity-1” in annotated Fig. 13 above) extending from the lower surface into a body of the monolithic silicon structure (see Fig. 13) and surrounding the second semiconductor device (lower-146, see Fig. 13); and
a third semiconductor device (upper-146, Fig. 13, para [0047]) disposed on a top surface of the monolithic silicon structure (364),
wherein the monolithic silicon structure includes a plurality of TSVs (199, Fig. 13, paras [0060]) extending between the cavity (cavity-1) and the top surface of the monolithic silicon structure (364, see Fig. 13) and electrically coupling (see Fig. 13) the second semiconductor device (lower-146) and the third semiconductor device (upper-146).
Choi does not explicitly show the first semiconductor device. However, Choi teaches that the bumps 362 connects the semiconductor structure to another semiconductor device (para [0114]). Thus, one of ordinary skill would look into related art to learn the connections to an external semiconductor device. Related art, Baek teaches a similar semiconductor structure (110+130, Fig. 1, paras [0023] - [0024]) connected to another semiconductor device like a package substrate (150, Fig. 1, para [0023]). Additionally, Chen discloses that a top layer of a package substrate (101, Fig. 2, para [0017]) can be a redistribution structure consisting of a dielectric layer (101b, Fig. 2, para [0019]) defining a top surface (top surface of 101, Fig. 2) with embedded conductive elements (101c, Fig. 2, para [0020]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the package substrate to the semiconductor structure of Choi, according to the disclosures of Choi, Baek and Chen. A package substrate helps in providing the physical and electrical infrastructure of the semiconductor structure and allows stacking of devices on top of it, and furthermore helps in connecting and routing signals.
Thus, Choi modified by Baek and Chen teaches the following:
a first semiconductor device (150, Fig. 1, para [0023], Baek) including a first dielectric layer (101b, Fig. 2, para [0019], Chen) defining an upper surface (upper surface of 150, Fig. 1, Baek);
a second semiconductor device (lower-146, Fig. 13, para [0047]) directly carried by the upper surface of the first semiconductor device (150, Fig. 1, para [0023], Baek);
a monolithic silicon structure (364, Fig. 13, Choi) having a lower surface (212, Fig. 13, Choi) in contact (electrical contact) with the upper surface of the first semiconductor device (upper surface of 150, Fig. 1, Baek).
Furthermore, Choi does not explicitly teach that the cavity of the monolithic structure has a rectangular cross-sectional shape. However, Choi discloses that the sidewalls of the cavities can be angled or curved (para [0054]). Related art, Baek teaches that the recess 112 (Fig. 2, para [0024]) of the monolithic substrate 110 (Fig. 2, para [0024]) can have rectangular cross-sectional shape as envisioned by Choi. It would have been prima facie obvious to one of ordinary skill in the art to realize that the cross-sectional shape of the cavity is a design choice as disclosed by Choi, and can have a rectangular cross-section shape as disclosed by Baek. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Re Claim 19, Choi modified by Baek and Chen recites the semiconductor device assembly of the semiconductor device assembly of wherein the third semiconductor device (upper-146, Fig. 13, Choi) is encapsulated by a mold material (211, Fig. 13, para [0074], Choi).
Claims 2 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2012/0146177 A1), Baek et al. (US 2008/0128882 A1) and Chen et al. (US 2019/0067244 A1), and further in view of Chen2 et al. (US 2011/0215470 A1).
Re Claim 2, Choi modified by Baek and Chen recites the semiconductor device assembly of claim 1, but does not disclose that the monolithic silicon structure has a plan area corresponding in size and shape to a plan area of the first semiconductor device.
However, in a related semiconductor art, Chen2 discloses that the monolithic silicon structure (24’, Figs. 6a-6B, paras [0017] and [0020]) can have a plan area corresponding in size and shape to a plan area of the first semiconductor device (10, Fig. 6A-6B, para [0015]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the device of Choi modified by Baek and Chen, such that the monolithic silicon structure has a plan area corresponding in size and shape to a plan area of the first semiconductor device, as taught by Chen2, as this will reduce overall footprint of the electronic device and the more compact design will facilitate an efficient heat dissipation between the different semiconductor devices.
Re Claim 16, Choi modified by Baek and Chen recites the semiconductor device assembly of the semiconductor device assembly of wherein the monolithic silicon structure includes a plurality of outer surfaces (outer surfaces of 364, Choi).
However, Choi modified by Baek and Chen does not disclose that the outer surfaces of the monolithic structure are coplanar with the outer surfaces of the first semiconductor device (150, Fig. 1, para [0023], Baek).
In a related semiconductor art, Chen2 discloses that the monolithic silicon structure (24’, Figs. 6a-6B, paras [0017] and [0020]) can have a plan area corresponding in size and shape to a plan area of the first semiconductor device (10, Fig. 6A-6B, para [0015]) and the outer surfaces of the monolithic silicon structure (24’, Figs. 6a-6B) are coplanar with the outer surfaces of the first semiconductor device (10, Fig. 6A-6B).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the device of Choi modified by Baek and Chen, such that the monolithic silicon structure has a plan area corresponding in size and shape to a plan area of the first semiconductor device, as taught by Chen2, and thus the outer surfaces of the monolithic silicon structure will be coplanar with the outer surfaces of the first semiconductor device. This will reduce the overall footprint of the electronic device and the more compact design will facilitate an efficient heat dissipation between the different semiconductor devices.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2012/0146177 A1), Baek et al. (US 2008/0128882 A1) and Chen et al. (US 2019/0067244 A1), and further in view of Jiang et al. (US 2005/0218518 A1).
Re Claim 6, Choi modified by Baek and Chen recites the semiconductor device assembly of claim 1, but does not teach that the lower surface of the monolithic silicon structure (364, Choi) is bonded to the upper surface of the first semiconductor device (upper surface of 150, Baek) by a dielectric bond.
However, related art Jiang teaches that an underfill dielectric material can be placed between the semiconductor devices and the interposer substrate to secure the semiconductor devices to the substrate and to provide additional electrical insulation between the semiconductor devices and the interposer (para [0021]). The underfill will also serve as a dielectric bond between the devices and the substrate.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have an underfill dielectric material between the lower surface of the monolithic silicon structure and the upper surface of the first semiconductor device as taught by Jiang, as it will secure the monolithic silicon structure to the first semiconductor device and will also provide additional electrical insulation between them (para [0021], Jiang). The underfill dielectric will also serve as a dielectric bond between the lower surface of the monolithic silicon structure (364, Choi) and the upper surface of the first semiconductor device (upper surface of 150, Baek).
Response to Arguments
Applicant’s arguments with respect to claims 1, 10 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Shen et al. (US 2016/0133600 A1) also show a similar semiconductor device assembly including a monolithic silicon structure (Fig. 5G) as compared to the applicant.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PINAKI DAS whose telephone number is (703)756-5641. The examiner can normally be reached M-F 8-5 EST.
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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