DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/2/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the limitation "dummy pattern" in line 2. There is insufficient antecedent basis for this limitation in the claim. It is not clear if the applicant is referring to the dummy pattern in claim 10, or redefining a new one. Hence, the claim is indefinite and rejected. Claim 12 depends from claim 11 and are rejected for at least the reasons above
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim 17 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Su et al. (US 2017/0133351 A1, of record).
Re Claim 17, Su teaches a semiconductor package comprising:
a package substrate (68+70, Fig. 15, para [0030]);
a first semiconductor chip (marked “chip1” in annotated Fig. 15 below) on the package substrate (68+70); and
a plurality of outer terminals (74, Fig. 15, para [0031]) on a bottom surface of the package substrate (68+70),
wherein the first semiconductor chip (“chip1”) comprises:
a substrate (36, Fig.15, para [0018]);
an insulating layer (50, marked in Fig.15 below, para [0023], also see Fig. 11B where the layer is marked) on a bottom surface of the substrate (36);
a through via (42, Fig. 15, para [0019]) penetrating the substrate (36);
an interconnection structure (52, marked in Fig.15 below, para [0023], also see Fig. 11B where the structure is marked) in the insulating layer (50), the interconnection structure (52) comprising a conductive via penetrating a portion of the insulating layer (see Fig. 15), and a conductive pattern electrically connected to the conductive via (see Fig. 15);
a stepwise portion (marked “step-portion” in annotated Fig. 15 below), which is provided by a portion of the insulating layer (50) protruding outward from a side surface of the substrate (36); and
a dummy pattern (32+84, Fig. 15) disposed directly on the stepwise portion (“step-portion”), the dummy pattern (32+84) having an upward convex shape (84 has an upward convex shape, Fig. 15).
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Allowable Subject Matter
Claims 1-10 and 13-16 are allowed.
Claim 11 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Claim 12 depends from claim 11 and would be allowable for at least the reasons above.
Claims 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowable subject matter:
Claim 1 is allowable for at least the following reasons. Most of the limitations of claim 1 are taught by Yu et al. (US 2017/0263518 A1, of record), as stated in the office action dated 11/13/2025. However, the newly amended claim includes an additional limitation, “wherein the dummy pattern comprises a burr”. In the Examiner’s opinion, this limitation is neither anticipated nor made obvious by the prior art of record, when viewed in the context of the whole claim. Claims 2-9 depend from claim 1 and are allowable for at least the reasons above.
Claim 10 is allowable for at least the following reasons. Most of the limitations of claim 10 are taught by Yu et al. (US 2017/0263518 A1, of record) in view of Chen et al. (US 2019/0027454 A1, of record), as stated in the office action dated 11/13/2025. However, the newly amended claim includes an additional limitation, where the device further comprises, “a dummy pattern comprising a burr” and “wherein the dummy pattern is disposed on the portion of the top surface of the insulating layer”. In the Examiner’s opinion, this limitation is neither anticipated nor made obvious by the prior art of record, when viewed in the context of the whole claim. Claims 13-16 depend from claim 10 and are allowable for at least the reasons above.
Claim 11 depends from allowable independent claim 10 and would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Claim 12 depends from claim 11 and would be allowable for at least the reasons above.
Claim 18 is allowable for at least the reasons of, “a second semiconductor chip disposed between the package substrate and the first semiconductor chip; and a plurality of third semiconductor chips stacked on the first semiconductor chip, wherein the first semiconductor chip comprises an upper connection pad adjacent to a top surface thereof, wherein a lowermost one of the plurality of third semiconductor chips comprises a lower connection pad adjacent to a bottom surface thereof, and wherein the upper connection pad and the lower connection pad are in contact with each other”. The prior art of record taken either single or in combination fails to teach or reasonably suggest the above limitation when taken in context of the independent claim 17, as a whole.
Claims 19 depends from claim 18 and is allowable for at least the reasons above.
Claim 20 is allowable for at least the reasons of, “a second semiconductor chip disposed between the package substrate and the first semiconductor chip; and a third semiconductor chip horizontally spaced apart from the second semiconductor chip, wherein the third semiconductor chip is of a different kind from the first semiconductor chip”. The prior art of record taken either single or in combination fails to teach or reasonably suggest the above limitation when taken in context of the independent claim 17, as a whole.
Response to Arguments
Applicant’s arguments with respect to claim 17 has been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898