DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Applicant’s amendments filed 02/18/2026 have been entered. Claims 1-12, 14-18, 26-27, and 30 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-8, 14-15 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20200104462 A1) hereinafter “Chen” in view of Zhang et al. (US 10825736 B1) hereinafter “Zhang,” Ng et al. (US 20220359506 A1) hereinafter “Ng” and Xie et al. (US 20210391222 A1) hereinafter “Xie.”
Regarding Claim 1, Figures 1-4B of Chen teach: An integrated circuit (101) comprising: a first cell (Fig. 2B: 211-2; Fig. 2H: 232-1) including a first transistor (Fig. 2B: 208N and 208P of cell 211-2; Fig. 2H: N-fins and P-fins) in which a plurality of nanosheets (Paragraph 0025) included in a first nanosheet stack (Fig. 2B: 208N-4; Fig. 2H: top vertical P-fin of row 231-3) and a second nanosheet stack (Fig. 2B: 208P-2; Fig. 2H: N-fin of row 231-2) extend in a first direction (left/right horizontally in Fig. 2B) to pass through a first gate electrode (Fig. 2B: 215-2) that extends in a second direction (up/down vertically in Fig. 2B) intersecting with the first direction; and a second cell (Fig. 2B: 210-2; Fig. 2H: 234-2) including a second transistor (Fig. 2B: 208N of cell 210-2; Fig. 2H: P-fin) in which at least one nanosheet (Paragraph 0025) included in a third nanosheet stack (Fig. 2B: 208N-1; Fig. 2H: P-fin in row 231-3) extends in the first direction to pass through a second gate electrode (Fig. 2B: 214-2) that extends in the second direction, an insulating layer extending in the first direction (452) wherein a length of the first cell in the second direction is greater than a length of the second cell in the second direction (Figure 2H, where Chen depicts a height, vertically, of first cell, 232-1, is greater than the height, vertically, of a second cell, 234-2.) [Examiner notes there are multiple N-fin and P-fin stacks that satisfy the claim language.]
Chen does not explicitly teach: the first nanosheet stack and the second nanosheet stack extend in a first direction over a first fin pattern and a second fin pattern; wherein the first nanosheet stack includes first nanosheets stacked over the first fin pattern in a vertical direction, and wherein the second nanosheet stack includes second nanosheets stacked over the second fin pattern in the vertical direction.
Figure 1 of Zhang teaches: a semiconductor structure (5) comprising a substrate (10) with shallow trench isolation regions (12) formed within the substrate forming fin patterns, and a nanosheet stack (20) stacked over the fin pattern in the vertical direction (up/down).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first nanosheet stack and the second nanosheet stack extend in a first direction over a first fin pattern and a second fin pattern; wherein the first nanosheet stack includes first nanosheets stacked over the first fin pattern in a vertical direction, and wherein the second nanosheet stack includes second nanosheets stacked over the second fin pattern in the vertical direction because Zhang teaches nanosheet stacks can be stacked vertically over fins to form field effect devices (Zhang Column 4; Lines 13-21).
Chen does not explicitly teach: the insulating layer in contact with at least one of a side surface of the first nanosheet stack and a side surface of the second nanosheet stack
Figures 17A-17B of Xie teach: a first nanosheet (Paragraph 0032) stack (200a) and a second nanosheet stack (200b) with an insulating layer (402) in contact with at least one of a side surface of the first nanosheet stack and a side surface of the second nanosheet stack (Figure 17B)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the insulating layer in contact with at least one of a side surface of the first nanosheet stack and a side surface of the second nanosheet stack because the insulating layer acts as a spacer between NFET and PFET devices (Xie Paragraph 0043) creating a “fork nanosheet device” which permits area scaling (Xie Paragraph 0002).
Chen does not explicitly teach: the first insulating layer is formed in the first gate electrode, and a bottom surface of the first insulating layer being coplanar with a bottom surface of the first gate electrode
Figures 2K-1 – 2K-4 of Ng teach: a semiconductor structure comprising FETs (T1 and T2) with a first insulating layer (174) formed in (Figure 2K-4) the first gate electrode (166), and the bottom surface of the first insulating layer is coplanar with the bottom surface of the first gate electrode.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first insulating layer is formed in the first gate electrode, and a bottom surface of the first insulating layer being coplanar with a bottom surface of the first gate electrode because Ng teaches gate-cut features are formed in meal gates to separate and electrically isolate neighboring segments of the final gate stacks (Ng Paragraph 0087).
Regarding Claim 6, Figure 2H of Chen: the second cell (234-2) is in a first row (231-3) extending in the first direction (left/right horizontally), wherein the first nanosheet stack (top vertical P-fin of row 231-3 in cell 232-1) and the third nanosheet stack (top vertically P-fin in row 231-3 in cell 231-3) are aligned with each other in the first direction in the first row, and wherein the second nanosheet stack (N-fin of row 231-2 in cell 232-1) is included in a second row (231-2) adjacent (adjacent vertically) to the first row.
Regarding Claim 7, the combination of Chen, Zhang, Ng, and Xie teaches all of the limitations of the claimed invention as stated above.
Chen does not explicitly teach: the length of the first cell in the second direction is twice the length of the second cell in the second direction.
However, Figure 2H teaches a cell (232-1) with double row-height (DRH)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the length of the first cell in the second direction be twice the length of the second cell in the second direction because Chen teaches an embodiment of a cell of double row-height in which the double-row height is utilized to avoid wasted space (Paragraph 0064).
Regarding Claim 8, Figure 2H of Chen teaches: the integrated circuit includes a first row (204-10) and a second row (204-9) adjacent (vertically) to the first row, wherein the first cell (232-1) is used in the first row and in the second row, wherein the second cell is used in the first row; wherein the first nanosheet stack (2H: top vertical N-fin of half-row 231-2) and the second nanosheet stack (Fig. 2H: bottom vertical N-fin of half-row 231-2) are in the second row, and wherein the first cell further includes a third transistor (Fig. 2H: P-fins of half-row 231-3) in which at least one nanosheet (Paragraph 0025) included in a fourth nanosheet stack (Fig. 2H: top vertical P-fin of half-row 231-3) in the first row extends in the first direction (left/right horizontally) to pass through the first gate electrode (gate of 232-1). [Examiner notes that the claim language does not require the second cell only be used in the first row.]
Regarding Claim 14, the language “the first cell and the second cell provide a same function and different performances” is functional language.
It would be obvious to one of ordinary skill in the art, that the first cell and second cell could have the same function with a different performance, as the performance of a cell can be changed with different voltages applied to the transistors within and the function of the cells can be decided by the corresponding circuit. This functional language does not distinguish the claimed device over the prior art, since it appears that this limitation can be performed by the prior art structure of Chen. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429,1431-32 (Fed. Cir. 1997) See MPEP 2114.
The Examiner suggests including limitations in Claim 1, which will render a performance difference between the first cell and the second cell.
Regarding Claim 15, Figures 2A-2H and 4A-4B of Chen teach: An integrated circuit (Paragraph 0018) comprising: a first device region (See annotated Figure 2B and 4A of Chen below; R1) and a second device region (See annotated Figure 2B and 4A of Chen below; R2) that extend in parallel with each other in a first direction (Fig 2B; left/right horizontally); a first device isolation layer (See annotated Figure 4A below; IL) extending in the first direction between the first device region and the second device region; a first gate electrode (Fig 2B: 215-2) extending in a second direction (Fig 2B: up/down vertically) intersecting with the first direction; a first active pattern (See annotated Figure 2B below; A1) extending in the first direction in the first device region; a second active pattern (See annotated Figure 2B below; A2) extending in the first direction between the first device isolation layer and the first active pattern; a first nanosheet stack (Paragraph 0025; 208N-3) including first nanosheets (Paragraph 0025) extending in the first direction over the first active pattern to pass through the first gate electrode; and a second nanosheet stack (Paragraph 0025; 208N-4) including second nanosheets (Paragraph 0025) extending in the first direction over the second active pattern to pass through the first gate electrode, an insulating layer extending in the first direction (452)
Chen does not explicitly teach: the first active pattern having a fin shape; the second active pattern having a fin shape; wherein the first nanosheets are stacked over the first active pattern in a vertical direction, and wherein the second nanosheets are stacked over the second active pattern in the vertical direction.
Figure 1 of Zhang teaches: a semiconductor structure (5) comprising a substrate (10) with shallow trench isolation regions (12) formed within the substrate forming fin patterns, and a nanosheet stack (20) stacked over the fin pattern in the vertical direction (up/down).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first active pattern having a fin shape; the second active pattern having a fin shape; wherein the first nanosheets are stacked over the first active pattern in a vertical direction, and wherein the second nanosheets are stacked over the second active pattern in the vertical direction because Zhang teaches nanosheet stacks can be stacked vertically over fins to form field effect devices (Zhang Column 4; Lines 13-21).
Chen does not explicitly teach: the insulating layer in contact with at least one of a side surface of the first nanosheet stack and a side surface of the second nanosheet stack
Figures 17A-17B of Xie teach: a first nanosheet (Paragraph 0032) stack (200a) and a second nanosheet stack (200b) with an insulating layer (402) in contact with at least one of a side surface of the first nanosheet stack and a side surface of the second nanosheet stack (Figure 17B)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the insulating layer in contact with at least one of a side surface of the first nanosheet stack and a side surface of the second nanosheet stack because the insulating layer acts as a spacer between NFET and PFET devices (Xie Paragraph 0043) creating a “fork nanosheet device” which permits area scaling (Xie Paragraph 0002).
Chen does not explicitly teach: the first insulating layer is formed in the first gate electrode, and a bottom surface of the first insulating layer being coplanar with a bottom surface of the first gate electrode
Figures 2K-1 – 2K-4 of Ng teach: a semiconductor structure comprising FETs (T1 and T2) with a first insulating layer (174) formed in (Figure 2K-4) the first gate electrode (166), and the bottom surface of the first insulating layer is coplanar with the bottom surface of the first gate electrode.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first insulating layer is formed in the first gate electrode, and a bottom surface of the first insulating layer being coplanar with a bottom surface of the first gate electrode because Ng teaches gate-cut features are formed in meal gates to separate and electrically isolate neighboring segments of the final gate stacks (Ng Paragraph 0087).
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Annotated Figure 2B of Chen Annotated Figure 2B of Chen
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Annotated Figure 4A of Chen
Regarding Claim 26, Figures 2A-2H and 4A-4B of Chen teach: a third device region (See annotated Figure 2B of Chen; R3) and a fourth device region (See annotated Figure 2B of Chen; R4) respectively extending in parallel with the first device region and the second device region in the first direction (left/right horizontally); and a second device isolation layer (See annotated Figure 2B of Chen; IL2) extending in parallel with the third device region and the fourth device region in the first direction between the third device region and the fourth device region, wherein a total length of the first device region, the first device isolation layer, and the second device region in the second direction is greater than a total length of the third device region, the second device isolation layer, and the fourth device region in the second direction (Figure 2H, where Chen depicts a height, vertically, of first cell, 232-1, which includes the first device region, the first device isolation layer, and the second device region, is greater than the
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height, vertically, of a second cell, 234-2.)
Annotated Figure 2B of Chen
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20200104462 A1) hereinafter “Chen” in view of Zhang et al. (US 10825736 B1) hereinafter “Zhang,” Ng et al. (US 20220359506 A1) hereinafter “Ng,” Xie et al. (US 20210391222 A1) hereinafter “Xie,” and Bao et al. (US 20190378830 A1) hereinafter “Bao”.
Regarding Claim 3, the combination of Chen, Zhang, Ng, and Xie teaches all of the limitations of the claimed invention as stated above.
Figure 3A of Chen further teaches: the first cell (Fig. 2B: 211-2; Fig. 2H: 232-1; Fig. 3A: 311-5) includes first patterns (M0 of 311-5; Figure 3A) formed in a wiring layer (Paragraph 0073) among a plurality of wiring layers (Paragraph 0074) wherein the second cell (Fig. 2B: 210-2; Fig. 2H: 234-2; Fig 3A: 310-5) includes second patterns (M0 of 310-5; Figure 3A) formed in the wiring layer
Chen does not teach: a pitch between the first patterns is greater than a pitch between the second patterns.
Figure 1 of Bao teaches: a semiconductor die (100) with a first device (130) with gates (150 of device region 130) having a first gate pitch (CPP2) and a second device (120) with gates (150 of device region 120) having a second gate pitch (CPP1) wherein the first pitch is greater than the second pitch (Paragraph 0020).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a pitch between the first gate electrodes in the first cell is greater than a pitch between the second gate electrodes in the second cell because cells with a small CPP are used to save area on the die, while cells with a large CPP can be utilized for higher performance on the same die (Bao Paragraph 0002).
When the different contacted poly pitches as described by Bao are combined with the structure of Chen, a structure will be yielded such that a pitch between the first patterns is greater than a pitch between the second patterns.
Regarding Claim 4, the combination of Chen, Zhang, Ng, Xie and Bao teaches all of the limitations of the claimed invention.
Figures Chen further teaches: the first cell (Fig. 2B: 211-2; Fig. 2H: 232-1; Fig. 3A: 311-5) includes a first via (Fig. 3A: 342-2; Fig 4B: 442-4) connected (Paragraph 0073) to one of the first patterns (M0 of 311-5; Figure 3A), wherein the second cell (Fig. 2B: 210-2; Fig. 2H: 234-2; Fig 3A: 310-5) includes a second via (Fig. 3A: 342-1) connected to one of the second patterns (M0 of 310-5; Figure 3A),
Chen does not teach: the first via has a greater cross-sectional area than the second via.
Figure 1 of Bao teaches: a semiconductor die (100) with a first device (130) with a via (combination of 180 and 170) and a second device (120) with a via (160) wherein the first via has a greater cross-sectional area (Figure 1) than the second via
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first via has a greater cross-sectional area than the second via because the larger contact poly pitch cell requires a larger contact opening (Bao Paragraph 0027).
Claims 2 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20200104462 A1) hereinafter “Chen” in view of Zhang et al. (US 10825736 B1) hereinafter “Zhang,” Ng et al. (US 20220359506 A1) hereinafter “Ng,” Xie et al. (US 20210391222 A1) hereinafter “Xie,” Kishishita (US 20190172841 A1) hereinafter “Kishishita” and Bao et al. (US 20190378830 A1) hereinafter “Bao”.
Regarding Claim 2, the combination of Chen, Zhang, Ng, and Xie teaches all of the limitations of the claimed invention as stated above.
Chen does not teach: the first cell includes a plurality of the first gate electrodes and the second cell includes a plurality of the second gate electrodes
Figure 1 of Kishishita teaches: a cell (1) with a plurality of gate electrodes (31p, 31n, 32p, and 32n) intersecting a p-type transistor region (PA) and an n-type transistor region (NA) with a pitch (Pg) between gate electrodes.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first cell include a plurality of the first gate electrodes and the second cell includes a plurality of the second gate electrodes, a pitch between the first gate electrodes in the first cell and a pitch between the second gate electrodes in the second cell because Kishishita teaches a plurality of gates is used in a standard cell utilizing multiple field-effect transistors to create a different number of inputs (Kishishita Paragraph 0038).
Chen does not teach: a pitch between the first gate electrodes in the first cell is greater than a pitch between the second gate electrodes in the second cell
Figure 1 of Bao teaches: a semiconductor die (100) with a first device (130) with gates (150 of device region 130) having a first gate pitch (CPP2) and a second device (120) with gates (150 of device region 120) having a second gate pitch (CPP1) wherein the first pitch is greater than the second pitch (Paragraph 0020).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a pitch between the first gate electrodes in the first cell is greater than a pitch between the second gate electrodes in the second cell because cells with a small CPP are used to save area on the die, while cells with a large CPP can be utilized for higher performance on the same die (Bao Paragraph 0002).
Regarding Claim 5, the combination of Chen, Zhang, Ng, Xie and Bao teaches all of the limitations of the claimed invention as stated above.
Figures 2A-4B of Chen teach: the second patterns (M0 of 310-5; Figure 3A) extend only in the first direction (left/right horizontally).
Chen does not teach: the first patterns include a pattern including a first portion extending in the first direction and a second portion extending in the second direction
Figure 1 of Kishishita teaches: a cell (1) with a pattern (M1) that includes a first portion (See annotated Figure 1 of Kishishita below; P1) extending in the first direction (left/right horizontally) and a second portion (See annotated Figure 1 of Kishishita below; P2) extending in the second direction (P2)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first patterns include a pattern including a first portion extending in the first direction and a second portion extending in the second direction because Kishishita teaches metal patterns are used to form interconnects in cells to perform various functions such as power supply potential, ground potential, and connections to pads (Kishishita Paragraph 0044).
Claims 9 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20200104462 A1) hereinafter “Chen” in view of Zhang et al. (US 10825736 B1) hereinafter “Zhang,” Ng et al. (US 20220359506 A1) hereinafter “Ng,” Xie et al. (US 20210391222 A1) hereinafter “Xie,” and Lin et al. (US 20210066291 A1) hereinafter “Lin.”
Regarding Claim 9, the combination of Chen, Zhang, Ng, and Xie teaches all of the limitations of the claimed invention as stated above.
Figures 1-4B of Chen further teaches: the first nanosheet stack (Fig. 2B: 208N-4; Fig. 2H: top vertical P-fin of row 231-3) includes a nanosheet having a first width, wherein the second nanosheet stack (Fig. 2B: 208P-2; Fig. 2H: N-fin of row 231-2) includes a nanosheet having a second width [The Examiner notes that each nanosheet in the stacks of Chen would inherently have a width.]
Chen does not teach: the first width is different from the second width.
Figure 3A of Lin teaches: a logic cell (300) with first nanosheets (302a and 304a) with a first width and second nanosheets (302b and 304b) having a second width, wherein the first width is different from the second width (Paragraph 0034).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first width be different from the second width because Lin teaches nanosheets with a smaller width causes processing of current signals in gates to be slower than in the nanosheets with a larger width, and have a greater power efficiency (Lin Paragraph 0034.)
Regarding Claim 16, the combination of Chen, Zhang, Ng, and Xie teaches all of the limitations of the claimed invention as stated above.
Figures 1-4B of Chen further teaches: the each of the first nanosheets (Fig. 2B: 208N-4; Fig. 2H: top vertical P-fin of row 231-3) having a first width, wherein the each of the second nanosheets (Fig. 2B: 208P-2; Fig. 2H: N-fin of row 231-2) has a second width [The Examiner notes that each nanosheet in the stacks of Chen would inherently have a width.]
Chen does not teach: the first width is different from the second width.
Figure 3A of Lin teaches: a logic cell (300) with first nanosheets (302a and 304a) with a first width and second nanosheets (302b and 304b) having a second width, wherein the first width is different from the second width (Paragraph 0034).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first width be different from the second width because Lin teaches nanosheets with a smaller width causes processing of current signals in gates to be slower than in the nanosheets with a larger width, and have a greater power efficiency (Lin Paragraph 0034.)
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20200104462 A1) hereinafter “Chen” in view of Zhang et al. (US 10825736 B1) hereinafter “Zhang,” Ng et al. (US 20220359506 A1) hereinafter “Ng,” Xie et al. (US 20210391222 A1) hereinafter “Xie,” and Kishishita (US 20190172841 A1) hereinafter “Kishishita.”
Regarding Claim 10, the combination of Chen, Zhang, Ng, and Xie teaches all of the limitations of the claimed invention as stated above.
Chen does not teach: a number of nanosheets included in the first nanosheet stack is different from a number of nanosheets included in the second nanosheet stack.
Figure 9 of Kishishita teaches: a standard cell (3A) with a first nanowire stack FET (N31) and a second nanowire stack FET (N32a), where a number of nanowires included in the first nanowire stack is different from a number of nanowires included in the second nanowire stack (Paragraph 0092).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a number of nanosheets included in the first nanosheet stack is different from a number of nanosheets included in the second nanosheet stack because Kishishita teaches having a plurality of nanowire FETs which are connected in series and to which the same input is given include different numbers of nanowires, the driving capability can be finely adjusted (Kishishita Paragraph 0093).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20200104462 A1) hereinafter “Chen” in view of Zhang et al. (US 10825736 B1) hereinafter “Zhang,” Ng et al. (US 20220359506 A1) hereinafter “Ng,” Xie et al. (US 20210391222 A1) hereinafter “Xie,” and Zhu (US 20210226004 A1) hereinafter “Zhu.”
Regarding Claim 11, the combination of Chen, Zhang, Ng, and Xie teaches all of the limitations of the claimed invention as stated above.
Figures 1-4B of Chen further teaches: the first nanosheets (Fig. 2B: 208N-4; Fig. 2H: top vertical P-fin of row 231-3) are spaced apart from each other by a first distance and adjacent to each other, wherein the second nanosheets (Fig. 2B: 208P-2; Fig. 2H: N-fin of row 231-2) are spaced apart by a second distance and adjacent to each other (Paragraph 0025; as a Gate-All-Around structure)
Chen does not explicitly teach: the first nanosheets are vertically space apart from each other and the second nanosheets are vertically spaced apart
Figure 1 of Zhang teaches: a semiconductor structure (5) comprising a nanosheet stack (20) stacked over the fin pattern in the vertical direction (up/down), comprising nanosheets (24) vertically spaced apart from each other.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first nanosheets are vertically space apart from each other and the second nanosheets are vertically spaced apart because Zhang teaches alternating stacks of nanosheets and semiconducting material are utilized to form multiple field effect transistor devices (Zhang Column 4; Lines 13-21).
Chen does not teach: the first distance is different from the second distance.
Figures 9 and 10a of Zhu teach: channel layers (1021n and 1021p) with different thicknesses (Paragraph 0073).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention as stated above to have the first distance be different from the second distance because Zhu teaches adjusting the thickness of nanosheets in a semiconductor device adjusts the device performance (Zhu Paragraph 0024).
Regarding Claim 12, the combination of Chen, Zhang, Ng, and Xie teaches all of the limitations of the claimed invention as stated above.
Figures 1-4B of Chen further teaches: each of the first nanosheets (Fig. 2B: 208N-4; Fig. 2H: top vertical P-fin of row 231-3) has a first thickness in the vertical direction, wherein each of the second nanosheets (Fig. 2B: 208P-2; Fig. 2H: N-fin of row 231-2) has a second thickness in the vertical direction. [The Examiner notes that the nanosheets in the first and second stack will inherently have some thickness in the vertical direction.]
Chen does not teach: the first thickness is different from the second thickness.
Figures 9 and 10a of Zhu teach: channel layers (1021n and 1021p) with different thicknesses (Paragraph 0073).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention as stated above to have the first distance be different from the second distance because Zhu teaches adjusting the thickness of nanosheets in a semiconductor device adjusts the device performance (Zhu Paragraph 0024).
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20200104462 A1) hereinafter “Chen” in view of Zhang et al. (US 10825736 B1) hereinafter “Zhang,” Ng et al. (US 20220359506 A1) hereinafter “Ng,” Xie et al. (US 20210391222 A1) hereinafter “Xie,” Lin et al. (US 20210066291 A1) hereinafter “Lin” and Kishishita (US 20190172841 A1) hereinafter “Kishishita”.
Regarding Claim 17, the combination of Chen, Zhang, Ng, Xie, and Lin teach all of the limitations of the claimed invention as stated above.
Chen does not teach: a second gate electrode extending in the second direction
Figure 1 of Kishishita teaches: a cell (1) with a plurality of gate electrodes (31p, 31n, 32p, and 32n) intersecting a p-type transistor region (PA) and an n-type transistor region (NA) with a pitch (Pg) between gate electrodes.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a second gate electrode extending in the second direction because Kishishita teaches a plurality of gates is used in a standard cell utilizing multiple field-effect transistors to create a different number of inputs (Kishishita Paragraph 0038).
Chen does not teach: a third active pattern extending in the first direction in the first device region; a fourth active pattern extending in the first direction between the first device isolation layer and the third active pattern; a third nanosheet stack including at least one nanosheet extending in the first direction over the third active pattern to pass through the second gate electrode; and a fourth nanosheet stack including at least one nanosheet extending in the first direction over the fourth active pattern to pass through the second gate electrode
The combination of the structure including multiple gate electrodes of Kishishita with the structure of Chen would yield a structure such that a third active pattern extending in the first direction in the first device region; a fourth active pattern extending in the first direction between the first device isolation layer and the third active pattern; a third nanosheet stack including at least one nanosheet extending in the first direction over the third active pattern to pass through the second gate electrode; and a fourth nanosheet stack including at least one nanosheet extending in the first direction over the fourth active pattern to pass through the second gate electrode; the third nanosheet stack includes a nanosheet having a third width, wherein the fourth nanosheet stack includes a nanosheet having a fourth width
Chen does not teach: a sum of the first width and the second width is different from a sum of the third width and the fourth width.
Figure 3A of Lin teaches: a logic cell (300) with first nanosheets (302a and 304a) with a first width and second nanosheets (302b and 304b) having a second width, wherein the first width is different from the second width (Paragraph 0034).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a sum of the first width and the second width is different from a sum of the third width and the fourth width because Lin teaches nanosheets with a smaller width causes processing of current signals in gates to be slower than in the nanosheets with a larger width, and have a greater power efficiency (Lin Paragraph 0034).
Regarding Claim 18, the combination of Chen, Zhang, Ng, Xie, Lin, and Kishishita teaches all of the limitations of the claimed invention as stated above.
Figures 2A-2H and 4A-4B Chen further teaches: the first nanosheet stack (Paragraph 0025; 408N-3) is spaced apart from a first boundary (See annotated Figure 4A of Chen below; B) of the first device region (See annotated Fig 4A of Chen below; R1) by a first distance (See annotated Figure 4A of Chen below; D1).
Chen does not teach: the third nanosheet stack is spaced apart from a first boundary of the first device region by a first distance
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The combination of the plurality of gate electrodes of Kishishita and the structure of Chen will yield a structure such that the third nanosheet stack is spaced apart from a first boundary of the first device region by a first distance.
Annotated Figure 4A of Chen
Claims 27 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20200104462 A1) hereinafter “Chen” in view of Zhang et al. (US 10825736 B1) hereinafter “Zhang,” Ng et al. (US 20220359506 A1) hereinafter “Ng,” Xie et al. (US 20210391222 A1) hereinafter “Xie,” and Guha et al. (US 20200091145 A1) hereinafter “Guha.”
Regarding Claim 27, Figures 2A-2H and 4A-4B of Chen teach: An integrated circuit (Paragraph 0018) comprising: a first device region (See annotated Figure 2B and 4A of Chen below; R1)and a second device region (See annotated Figure 2B and 4A of Chen below; R2) that extend in parallel with each other in a first direction (Fig 2B; left/right horizontally); a first device isolation layer (See annotated Figure 4A below; IL) extending in the first direction between the first device region and the second device region; a first gate electrode (Fig 2B: 215-2) extending in a second direction (Fig 2B: up/down vertically) intersecting with the first direction; a plurality of first active patterns (See annotated Figure 2B below; A1) that extend in parallel with each other in the first direction in the first device region; a plurality of first nanosheet stacks (Paragraph 0025; 208N-3 and 208N-4) that each include at least one nanosheet extending in the first direction over each of the plurality of first active patterns to pass through the first gate electrode; a plurality of second active patterns (See annotated Figure 2B below; A2) that extend in parallel with each other in the first direction in the second device region; and a plurality of second nanosheet stacks (Paragraph 0025; 208P-3 and 208P-2) that each include at least one nanosheet extending in the first direction over each of the plurality of second active patterns to pass through the first gate electrode.
Chen does not explicitly teach: the plurality of first active patterns each having a fin shape; the plurality of second active patterns each having a fin shape;
Figure 1 of Zhang teaches: a semiconductor structure (5) comprising a substrate (10) with shallow trench isolation regions (12) formed within the substrate forming fin patterns, and a nanosheet stack (20) stacked over the fin pattern in the vertical direction (up/down).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of first active patterns each having a fin shape and the plurality of second active patterns each having a fin shape because Zhang teaches nanosheet stacks can be stacked vertically over fins to form field effect devices (Zhang Column 4; Lines 13-21).
Chen does not teach: wherein a first insulating layer is formed between the plurality of first nanosheet stacks and the plurality of second nanosheet stacks to replace a lower portion of the first gate electrode between the plurality of first nanosheet stacks and the plurality of second nanosheet stacks.
Figure 9A of Guha teaches: a semiconductor structure (900) with a first plurality of semiconductor fin/nanowire pairs (904/907; in region 970B), a second plurality of semiconductor fin/nanowire pairs (904/907; in region 970C), a first insulating layer (920) formed between the first plurality of semiconductor fin/nanowire pairs and the second plurality of semiconductor fin/nanowire pairs to replace a lower portion of a gate electrode (combination of 950 and 954) between the first plurality of semiconductor fin/nanowire pairs and the second plurality of semiconductor fin/nanowire pairs.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a first insulating layer is formed between the plurality of first nanosheet stacks and the plurality of second nanosheet stacks to replace a lower portion of the first gate electrode between the plurality of first nanosheet stacks and the plurality of second nanosheet stacks because Guha teaches the use of self-aligned gate wall architecture has the advantage of enabling of higher layout density and, in particular, scaling of diffusion to diffusion spacing (Guha Paragraph 0042).
Chen does not teach: the first insulating layer is in contact with at least one of a side surface of the at least one nanosheet of the plurality of first nanosheet stacks or a side surface of the at least one nanosheet of the plurality of second nanosheet stacks
Figures 17A-17B of Xie teach: a first nanosheet (Paragraph 0032) stack (200a) and a second nanosheet stack (200b) with an insulating layer (402) in contact with at least one of a side surface of the first nanosheet stack and a side surface of the second nanosheet stack (Figure 17B)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to the first insulating layer is in contact with at least one of a side surface of the at least one nanosheet of the plurality of first nanosheet stacks or a side surface of the at least one nanosheet of the plurality of second nanosheet stacks because the insulating layer acts as a spacer between NFET and PFET devices (Xie Paragraph 0043) creating a “fork nanosheet device” which permits area scaling (Xie Paragraph 0002).
Chen does not explicitly teach: the first insulating layer is formed in the first gate electrode, and a bottom surface of the first insulating layer being coplanar with a bottom surface of the first gate electrode
Figures 2K-1 – 2K-4 of Ng teach: a semiconductor structure comprising FETs (T1 and T2) with a first insulating layer (174) formed in (Figure 2K-4) the first gate electrode (166), and the bottom surface of the first insulating layer is coplanar with the bottom surface of the first gate electrode.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first insulating layer is formed in the first gate electrode, and a bottom surface of the first insulating layer being coplanar with a bottom surface of the first gate electrode because Ng teaches gate-cut features are formed in meal gates to separate and electrically isolate neighboring segments of the final gate stacks (Ng Paragraph 0087).
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Annotated Figure 2B of Chen Annotated Figure 4A of Chen
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Annotated Figure 2B of Chen
Regarding Claim 30, the combination of Chen, Zhang, Ng, and Xie teaches all of the limitations of the claimed invention as stated above.
Chen does not teach: a first insulating layer is formed between the first nanosheet stack and the second nanosheet stack to replace a lower portion of the first gate electrode between the first nanosheet stack and the second nanosheet stack.
Figure 9A of Guha teaches: a semiconductor structure (900) with a first plurality of semiconductor fin/nanowire pairs (904/907; in region 970B), a second plurality of semiconductor fin/nanowire pairs (904/907; in region 970C), a first insulating layer (920) formed between the first plurality of semiconductor fin/nanowire pairs and the second plurality of semiconductor fin/nanowire pairs to replace a lower portion of a gate electrode (combination of 950 and 954) between the first plurality of semiconductor fin/nanowire pairs and the second plurality of semiconductor fin/nanowire pairs.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a first insulating layer is formed between the first nanosheet stack and the second nanosheet stack to replace a lower portion of the first gate electrode between the first nanosheet stack and the second nanosheet stack because Guha teaches the use of self-aligned gate wall architecture has the advantage of enabling of higher layout density and, in particular, scaling of diffusion to diffusion spacing (Guha Paragraph 0042).
Response to Arguments
Applicant’s arguments, see Applicant’s Remarks, filed 02/18/2026, with respect to the rejections of Claims 1, 15, and 27 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Chen, Zhang, Ng, Xie, and Guha.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HALEE CRAMER/Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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