DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: the specification fails to provide proper antecedent basis for newly recited claim limitation of “a consistent mean grain size being present throughout an entirety of the polycrystalline oxide channel structure,” as set forth in claim 1 and of “the oxide material having a single mean grain size throughout the pillar,” as set forth in claim 7.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-6 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
With regard to claim 1, the newly recited limitation of “a consistent mean grain size being present throughout an entirety of the polycrystalline oxide channel structure,” is not supported by the originally filed disclosure. Paragraphs [0029] and [0063], cited by the applicant in the remarks of 9/8/2025 at page 7, discuss various grain size ranges and methods of forming grains, but fall short of providing support for the newly claimed limitations. Figures 1, 2, 4, 6, and 11-14, cited by the applicant in the remarks of 9/8/2025 at page 7, each show channel structures with various grain sizes, at least at the edges of the channel structure if not throughout, thus failing to provide support for the newly claimed limitations.
Claims 2-6 depend from claim 1 and inherit its deficiencies.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With regard to claim 1, the term “consistent” in claim 1 is a relative term which renders the claim indefinite. The term “consistent” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. It is unclear to what degree the mean grain sizes must concord with each other, or some other standard, in order to meet this claim term. Furthermore, it is unclear how the mean grain size can be evaluated as any given region, up to and including the entire channel structure, may be evaluated to provide a mean grain size. It is thus unclear if multiple mean grain sizes must be calculated in order to evaluate these mean grain sizes and determine if they are “consistent” or if a single mean grain size taken over the entire channel structure can be viewed as “consistent” with itself. For the purposes of examination with regard to the prior art, this interpretation will be used.
Claims 2-6 depend from claim 1 and inherit its deficiencies.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5, and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son et al. (US 2011/0017990) in view of Ikeda et al. (US 2019/0295626), Lue (US 2016/0005762), and Pillarisetty et al. (US 2020/0058798).
With regard to claim 1, Son teaches, in Fig 4, an integrated assembly, comprising: a gate material (120); a gate insulator material (130) adjacent to the gate material; a polycrystalline oxide channel structure (140) proximate the gate material and spaced from the gate material by the gate insulator material, a consistent mean grain size being present throughout an entirety of the polycrystalline oxide channel structure (here taking the mean grain size over the entire channel structure will give a value that is consistent with itself throughout the channel structure),
the polycrystalline oxide channel structure having an upper surface (surface on the right in the figure) and a lower surface (surface on the left in the figure) opposing the upper surface; a conductive contact structure (162, 164) against the upper surface and comprising a conductive material that differs from the polycrystalline channel structure ([0048]); wherein a carrier flow is induced along a first direction in response to an electric field along the gate material (arrow in figure); individual grains of the polycrystalline oxide channel region being peripherally bounded by grain boundaries (grain boundaries shown in figure); at least one of the grain boundaries having a portion which extends along a second direction, with the second direction crossing the first direction of the carrier flow (several shown in the figure).
Son does not explicitly teach that an entirety of a horizontal width of the lower surface being in contact with a digit line, the horizontal width of the lower surface extending between the first pair of opposing vertical surfaces; the conductive contact is coupled to a charge storage device.
Ikeda teaches, in Fig 2, that an entirety of a horizontal width of the lower surface (of 24) being in contact with a digit line (/BL), the horizontal width of the lower surface extending between the first pair of opposing vertical surfaces (vertical surfaces of /24, see figure); the conductive contact (top surface of 24, features taught by Son) is coupled to a charge storage device (26/27/28) to provide, “A dynamic random access memory (DRAM) is used in various applications such as a main memory, a buffer memory, and the like of a computer system,” ([0003]).
Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the device of Son with the configuration of Ikeda to provide a DRAM useful for multiple applications.
Son/Ikeda do not explicitly teach the gate material and gate insulator material being present on a first pair of opposing vertical surfaces of the polycrystalline oxide channel structure and being absent from a second pair of opposing vertical surfaces of the polycrystalline oxide channel structure.
Lue teaches, in Figs 1 and 3, the gate material (163) and gate insulator material (relevant portion of 151) being present on a first pair of opposing vertical surfaces of the polycrystalline oxide channel structure and being absent from a second pair of opposing vertical surfaces of the polycrystalline oxide channel structure (see figure, [0010]), “to provide a structure for three-dimensional integrated circuit memory with a low manufacturing cost, including reliable, very small memory elements, and high data densities,” ([0009]).
Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the device of Son/Ikeda with the gate configuration of Lue to provide a structure for three-dimensional integrated circuit memory with a low manufacturing cost, including reliable, very small memory elements, and high data densities.
Son/Ikeda/Lue do not explicitly teach the conductive contact structure having vertically extending sidewalls and having a width between the sidewalls equivalent to a width between the first pair of sidewalls across the upper surface of the polycrystalline oxide channel structure.
Pillarisetty teaches, in Figs 2A-2K and 9A, the conductive contact structure (104) having vertically extending sidewalls and having a width between the sidewalls equivalent to a width between the first pair of sidewalls (sidewalls of 103) across the upper surface of the polycrystalline oxide channel structure (103) so that, “the formation of the pillar 203 may be performed in a single set of etch operations,” ([0034]).
Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the device of Son/Ikeda/Lue with the pillar configuration of Pillarisetty so that the formation of the pillar structure can be performed with a single set of etch operations.
With regard to claim 5, Ikeda teaches, in Fig 2, that the gate material (WL), the insulative material (25) and the polycrystalline oxide (24) are supported by a semiconductor base (20) having a horizontally-extending upper surface, and wherein the carrier flow extends substantially orthogonally relative to the horizontally-extending upper surface (from BL to SL).
With regard to claim 6, Son teaches, in Fig 4, that the polycrystalline oxide channel comprises one or more of indium, zinc, tin and gallium ([0009]).
Claim(s) 2 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son et al. (US 2011/0017990) in view of Ikeda et al. (US 2019/0295626), Lue (US 2016/0005762), Pillarisetty et al. (US 2020/0058798), and Yuan et al. (US 2017/0170208).
With regard to claim 2, Son/Ikeda/Lue/Pillarisetty teaches most of the limitations of this claim, as set forth above with regard to claim 1.
Son/Ikeda/Lue/Pillarisetty does not explicitly teach that the individual grains are cubic crystallinity dominated.
Yuan teaches that the individual grains are cubic crystallinity dominated ([0063]) to, “increase the stability of the material, which can simplify the process of fabricating,” ([0063]).
Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the device of Son/Ikeda/Lue/Pillarisetty with the crystallinity of Yuan to increase stability and simplify fabrication.
With regard to claim 3, Son/Ikeda/Lue/Pillarisetty teaches most of the limitations of this claim, as set forth above with regard to claim 1.
Son/Ikeda/Lue/Pillarisetty does not explicitly teach that the polycrystalline oxide channel structure comprises semiconductor oxide having predominately cubic crystallinity.
Yuan teaches that the polycrystalline oxide channel structure comprises semiconductor oxide having predominately cubic crystallinity ([0063]) to, “increase the stability of the material, which can simplify the process of fabricating,” ([0063]).
Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the device of Son/Ikeda/Lue/Pillarisetty with the crystallinity of Yuan to increase stability and simplify fabrication.
Claim(s) 7 and 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son et al. (US 2011/0017990) in view of Ikeda et al. (US 2019/0295626) and Pillarisetty et al. (US 2020/0058798).
With regard to claim 7, Son teaches, in Fig 4, an integrated assembly, comprising: a gate material (120); an insulative material (130) adjacent to the gate material; and an oxide material (140) adjacent to the insulative material; the oxide material comprising one or more of indium, zinc, tin and gallium ([0009]), wherein a carrier flow is induced along a first direction in response to an electric field along the gate material (arrow in figure); the oxide material having a single mean grain size throughout the pillar (taking the mean grain size over the entirety of the pillar would inherently result in a single mean grain size) and having at least one grain boundary which extends along the first direction (several seen in layer 142) and which is offset from the insulative material by an intervening portion (141) of the oxide material; the carrier flow being within the intervening region and substantially parallel to said at least one grain boundary (see figure), a conductive contact (152, 162) in direct physical contact with a surface of the oxide material.
Son does not explicitly teach a digit line extending horizontally over a substrate; that the gate material is elevationally above the digit line; that the oxide material is in the form of a vertically extending pillar and in direct physical contact with the digit line; that the first direction is vertically; and that the direct physical contact of the conductive contact is with an upper surface of the pillar of oxide material, the conductive contact being coupled with a charge storage device.
Ikeda teaches, in Fig 2, a digit line (/BL) extending horizontally over a substrate (20); that the gate material (/WL) is elevationally above the digit line; that the oxide material (/24) is in the form of a vertically extending pillar and in direct physical contact with the digit line; that the first direction is vertically (see figure); and that the direct physical contact of the conductive contact (upper surface of /24, conductive contact of Son) is with an upper surface of the pillar of oxide material, the conductive contact being coupled with a charge storage device (/26, /27, /28) to provide, “A dynamic random access memory (DRAM) is used in various applications such as a main memory, a buffer memory, and the like of a computer system,” ([0003]).
Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the device of Son with the configuration of Ikeda to provide a DRAM useful for multiple applications.
Son/Ikeda do not explicitly teach the conductive contact structure having opposing vertical sidewalls extending above the upper surface of the pillar of oxide material, a width between the opposing vertical sidewalls being equivalent to a width of the upper surface of the pillar of oxide material; and the conductive contact consisting of one or more materials selected from the group consisting of metal silicide, metal nitride, metal carbide, conductively-doped silicon, conductively-doped germanium, and both tungsten and ruthenium.
Pillarisetty teaches, in Figs 2A-2K and 9A, the conductive contact structure (104) having opposing vertical sidewalls extending above the upper surface of the pillar of oxide material (103), a width between the opposing vertical sidewalls being equivalent to a width of the upper surface of the pillar of oxide material (see figures); and the conductive contact consisting of one or more materials selected from the group consisting of metal silicide, metal nitride, metal carbide, conductively-doped silicon, conductively-doped germanium, and both tungsten and ruthenium ([0026]) so that, “the formation of the pillar 203 may be performed in a single set of etch operations,” ([0034]).
Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the device of Son/Ikeda with the pillar configuration of Pillarisetty so that the formation of the pillar structure can be performed with a single set of etch operations.
With regard to claim 12, Son teaches, in Fig 4, that the oxide material includes indium, zinc and gallium ([0009]).
With regard to claims 13 and 14, Son/Ikeda/Pillarisetty teaches most of the limitations of these claims, as set forth above with regard to claim 12. However, Son/Ikeda/Pillarisetty does not explicitly teach the claimed concentrations of indium, zinc and gallium. Nonetheless, the skilled artisan would know too that concentrations of indium, zinc and gallium would impact the electrochemical properties of the layer.
The specific claimed concentration, absent any criticality, is only considered to be the “optimum” concentration disclosed by Son that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the electrochemical properties, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as the claimed concentrations of indium, zinc and gallium is used, as already suggested by Son/Ikeda/Pillarisetty.
Since the applicant has not established the criticality (see next paragraph) of the concentration stated and since these concentrations are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Son/Ikeda/Pillarisetty.
Please note that the specification contains no disclosure of either the critical nature of the claimed concentration or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son et al. (US 2011/0017990) in view of Ikeda et al. (US 2019/0295626), Pillarisetty et al. (US 2020/0058798), and Yuan et al. (US 2017/0170208).
With regard to claim 8, Son/Ikeda/Pillarisetty teaches most of the limitations of this claim, as set forth above with regard to claim 7.
Son/Ikeda does not explicitly teach that individual grains of the oxide material are cubic crystallinity dominated.
Yuan teaches that individual grains of the oxide material are cubic crystallinity dominated ([0063]) to, “increase the stability of the material, which can simplify the process of fabricating,” ([0063]).
Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the device of Son/Ikeda/Pillarisetty with the crystallinity of Yuan to increase stability and simplify fabrication.
With regard to claim 9, Son/Ikeda/Pillarisetty teaches most of the limitations of this claim, as set forth above with regard to claim 7.
Son/Ikeda/Pillarisetty does not explicitly teach that the oxide material is predominately of cubic crystallinity.
Yuan teaches that the oxide material is predominately of cubic crystallinity ([0063]) to, “increase the stability of the material, which can simplify the process of fabricating,” ([0063]).
Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the device of Son/Ikeda/Pillarisetty with the crystallinity of Yuan to increase stability and simplify fabrication.
Response to Arguments
Applicant's arguments filed 9/8/2025 have been fully considered but they are not persuasive.
All arguments have been fully addressed in prior Office Actions or in the rejections set forth above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/RAJ R GUPTA/Primary Examiner, Art Unit 2893
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