DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/25/25 has been entered.
Examiner’s Note
The prior art rejection below cites particular paragraphs, columns, and/or line numbers in the references for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art.
Claims 1 – 29 are pending for examination. Claims 1 – 8, 11 – 12, 14 – 20 and 22 – 28 are amended.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1 - 29 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
As to claim 1, the claim recites
One or more processors, comprising:
circuitry to, in response to perform an application programming interface (API) call:
cause a user mode driver to calculate one or more memory usage metrics corresponding to indicate one or more usage metrics about one or more storage locations corresponding to a pool of memory indicated by one or more input parameters of the API call; and
indicate the one or more memory usage metrics.
Prong I: the limitations “perform an application programming interface (API) call:
cause a user mode driver to calculate one or more memory usage metrics corresponding to indicate one or more usage metrics about one or more storage locations corresponding to a pool of memory indicated by one or more input parameters of the API call; and
indicate the one or more memory usage metrics.” are functions that can be reasonably carried out in the human mind with the aid of pen and paper, through observation, evaluation, judgment, opinion, thus it is reasonable to identify these limitation as reciting a mental process.
Prong II: the additional limitation “One or more processors, comprising:
Circuitry” merely recite instructions to implement an abstract idea on a generic computer, or merely uses a generic computer or computer components as a tool to perform the abstract idea.
As to claim 2, The one or more processors of claim 1, wherein the pool of memory pools comprises one or more blocks of memory to be allocated using one or more stream ordered memory allocators. merely recite insignificant extra solution activity such as gathering, displaying, updating, transmitting and storing data which does not integrate the judicial exception into a practical application. See MPEP 2106.05(d).
As to claim 3, The one or more processors of claim 1, wherein the one or more memory usage metrics comprises one or more data values to indicate one or more current usage metrics about the one or more storage locations. merely recite insignificant extra solution activity such as gathering, displaying, updating, transmitting and storing data which does not integrate the judicial exception into a practical application. See MPEP 2106.05(d).
As to claim 4, the one or more processors of claim 1, wherein the one or more memory usage metrics comprises one or more data values to indicate one or more historic usage metrics about the one or more storage locations. merely recite insignificant extra solution activity such as gathering, displaying, updating, transmitting and storing data which does not integrate the judicial exception into a practical application. See MPEP 2106.05(d).
As to claim 5, The one or more processors of claim 1, wherein the one or more storage locations are to be indicated to the API by one or more data values of the one or more input parameters, the one or more data values of the one or more input parameters indicating at least a block of memory comprising the one or more storage locations. merely recite insignificant extra solution activity such as gathering, displaying, updating, transmitting and storing data which does not integrate the judicial exception into a practical application. See MPEP 2106.05(d).
As to claim 6, The one or more processors of claim 1, wherein the one or more memory usage metrics is to indicate one of a plurality of attributes of the one or more storage locations, the one of the plurality of attributes selected by the API based, at least in part, on the one or more input parameters indicated to the API. merely recite insignificant extra solution activity such as gathering, displaying, updating, transmitting and storing data which does not integrate the judicial exception into a practical application. See MPEP 2106.05(d).
As to claim 7, this is a system claim of claim 1. See rejection for claim 1 above. Further, the additional limitations one or more processors and memory storing executable instructions merely recite instructions to implement an abstract idea on a generic computer, or merely uses a generic computer or computer components as a tool to perform the abstract idea.
As to claim 8, The system of claim 7, wherein the API is to receive one or more data values as a result of one or more API calls are functions that can be reasonably carried out in the human mind with the aid of pen and paper, through observation, evaluation, judgment, opinion, thus it is reasonable to identify these limitation as reciting a mental process,
the one or more data values indicating a type of the one or more memory usage metrics about the one or more storage locations merely recite insignificant extra solution activity such as gathering, displaying, updating, transmitting and storing data which does not integrate the judicial exception into a practical application. See MPEP 2106.05(d).
As to claim 9, The system of claim 7, wherein the API is to receive one or more data values as a result of one or more API calls are functions that can be reasonably carried out in the human mind with the aid of pen and paper, through observation, evaluation, judgment, opinion, thus it is reasonable to identify these limitation as reciting a mental process, the one or more data values indicating the one or more storage locations merely recite insignificant extra solution activity such as gathering, displaying, updating, transmitting and storing data which does not integrate the judicial exception into a practical application. See MPEP 2106.05(d).
As to claim 10, the system of claim 7, wherein the one or more storage locations comprise one or more pools of pool of memory merely recite insignificant extra solution activity such as gathering, displaying, updating, transmitting and storing data which does not integrate the judicial exception into a practical application. See MPEP 2106.05(d) is usable by one or more graphics processing units (GPUs) merely recite instructions to implement an abstract idea on a generic computer, or merely uses a generic computer or computer components as a tool to perform the abstract idea.
As to claims 11 - 12, these claims recite similar scope of claims 3 - 4. See rejection for claims 3 - 4 above.
As to claim 13, this claim recites similar scope of claim 2. See rejection for claim 2 above.
As to claim 14, this is a machine-readable medium claim of claim 1. See rejection for claim 1 above. Further, Rao teaches a machine-readable medium (“…By indicating a non-transitory storage medium it is not intend to limit characteristics of the medium, and can include a variety of storage mediums (e.g., programmable, erasable, nonprogrammable, read/write, read only, etc.) and "non-transitory" computer-readable media comprises all computer-readable media, with the sole exception being a transitory, propagating signal.” para. 0167) one or more processors (“…central processor unit 901…” para. 0054).
As to claim 15, this claim recites similar scope of claim 9. See rejection for claim 9 above.
As to claims 16 - 18, these claims recite similar scope of claims 8 - 10. See rejection for claims 8 - 10 above.
As to claims 19 - 20, these claims recite similar scope of claims 3 - 4. See rejection for claims 3 - 4 above.
As to claim 21, this claim recites similar scope of claim 2. See rejection for claim 2 above.
As to claim 22, this is a method claim of claim 1. See rejection for claim 1 above.
As to claim 23, this claim recites similar scope of claim 16. See rejection for claim 16 above.
As to claim 24, this claim recites similar scope of claim 9. See rejection for claim 9 above.
As to claim 25, this claim recites similar scope of claim 3. See rejection for claim 3 above.
As to claim 26, this claim recites similar scope of claim 12. See rejection for claim 12 above.
As to claim 28, this claim recites similar scope of claim 10. See rejection for claim 10 above.
As to claims 27 and 29, this claim recites similar scope of claim 2. See rejection for claim 2 above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1- 29 are rejected under 35 U.S.C. 103 as being unpatentable over Rao et al., (US PUB 2015/0206277 hereinafter Rao) in view of Poxon et al., (US PUB 2018/0165209 hereinafter Poxon).
As to claim 1, Rao teaches One or more processors comprising:
circuitry in response to an[application programming interface (API) call (“In block 110, a memory allocation trigger indication is received. In one embodiment, the allocation trigger is associated with a unified memory virtual address allocation. The present approach is compatible with a variety of triggers. The trigger indications can result from whenever a user requests a GPU allocation, an OS API initiates allocation of GPU accessible memory, or through an application program interface (API) (e.g., like cudaMalloc, etc.)” para. 0032) and (“...when a user tries to access a unified memory region a debugger (e.g., frontend, etc.) makes a call to an API (e.g., ptrace on Linux/Mac, etc.)...” para. 0065) and (“...There are a variety or ways to create managed memory (e.g., the managed memory can be created using an API call...” para. 0089):
cased a user mode driver (“..The device driver sitting there running inside the OS and can ask the device driver to read and write the address...” para. 0074 – 0080. Note: Driver running in application level is user mode driver) and (“...In one embodiment there is an API call (e.g., CudaMalloManaged, etc.) and a driver (e.g., GPU driver, etc.) manages the memory...” para. 0088) and (“In one embodiment, a new API call Cuda mallocmanaged is utilized. In one exemplary implementation, managed refers to the memory space that is managed by a driver (e.g., graphics device driver, etc.). A decision is made where to place the memory associated with a pointer and accesses to that memory are managed. The managing can include: when the GPU is accessing it make sure it is moved to the GPU and when the CPU is accessing make sure it is moved to the CPU. In one exemplary implementation, once a managed pointer is created the pointer is accessible from any location (e.g., a kernel, a processor, CPU, GPU, etc,).” Para. 0096) to calculate one or more memory usage metrics corresponding to one or more storage locations (“With unified memory, the GPU driver allows the application to use a single pointer to data from both, the CPU and the GPU. Unified memory also enables "local" access to memory. In one exemplary implementation, it moves data between CPU memory and GPU memory when the CPU or GPU accesses that data. Having data be present locally typically increases the performance of those accesses. “ para. 0083) corresponding to a pool of memory (“...The GPU driver reserves one or more regions from the CPU's virtual address space. The same or similar set of regions are also reserved in the GPUs virtual address space. The driver provides an opt-in allocator to the application to allocate out of these regions. The physical pages backing these allocations are created in GPU memory...” para. 0084) indicated by one or more input parameters of the API call (“..Program 2 is also a basic program. Program 2 begins by allocating memory on the GPU. The way this program does this is by making the call: "CudaMalloc(&d_ptr, sizeof(int))." This allows a portion of memory at pointer "d" to be allocated a desired number of bits (indicated by sizeof(int))...” para. 0127); and
Rao does not but Poxon teaches
indicate the one or more memory usage metrics (“..In this way, the allocation of data structures between HBM and LBM for an execution of the program is based on actual performance statistics collected during a prior execution of the program....” para. 0012) and (In some embodiments, the memory allocation system may employ various types of the performance counters as statistics that represent memory requests and memory bandwidth utilization. These statistics may include expiration of a timer, number of instructions executed, number of execution cycles, number of stalled cycles, LLC misses or hits, and so on. The number of stalled cycles may be approximated based on accesses (hits or misses) to a line fill buffer or an outstanding request buffer” para. 0014).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Rao by applying the teachings of Poxon because Poxon also teaches the same field of the invention of determining memory usage metrics/statistics for optimizing memory allocation (abstract and para. 0011).
As to claim 2, Rao modified by Poxon teaches The one or more processors of claim 1, Rao teaches wherein pool of memory comprises one or more blocks of memory to be allocated using one or more stream ordered memory allocators (“...A first type of stream is a "global" stream that represents all streams in the process that can access unified memory. When data is attached to the "global" stream, any work launched in any stream can access that data from the GPU. In order to access that data from the CPU, the application must ensure that there's no work from any stream pending on the GPU, by synchronizing those streams. A second type of stream is a "host" stream, that applications can attached data to if they intend to access that data from the CPU...” para. 0119).
As to claim 3, Rao modified by Poxon teaches The one or more processors of claim 1, Rao does not but Poxon teaches wherein the one or more memory usage metrics comprises one or more data values to indicate one or more current usage metrics about the one or more storage locations (“...These statistics may include expiration of a timer, number of instructions executed, number of execution cycles, number of stalled cycles, LLC misses or hits, and so on. The number of stalled cycles may be approximated based on accesses (hits or misses) to a line fill buffer or an outstanding request buffer” para. 0014).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Rao by applying the teachings of Poxon because Poxon also teaches the same field of the invention of determining memory usage metrics/statistics for optimizing memory allocation (abstract and para. 0011).
As to claim 4, Rao modified by Poxon teaches The one or more processors of claim 1, Rao teaches wherein the one or more memory usage metrics comprises one or more data values to indicate one or more historic usage metrics about the one or more storage locations (“..The memory bandwidth utilization may be estimated based on the time since the last occurrence, the number of instructions executed since the last occurrence and the time since the last occurrence, the number of processor cycles since the last occurrence, the number of processor stalled cycles since the last occurrence, the number of instructions executed since the last occurrence, and so on.” Para. 0015).
As to claim 5, Rao modified by Poxon teaches The one or more processors of claim 1, Rao teaches wherein the one or more storage locations are to be indicated to the API by one or more data values of the one or more input parameters, the one or more data values of the one or more input parameters indicating at least a block of memory comprising the one or more storage locations (“...Program 2 begins by allocating memory on the GPU. The way this program does this is by making the call: "CudaMalloc(&d_ptr, sizeof(int))." This allows a portion of memory at pointer "d" to be allocated a desired number of bits (indicated by sizeof(int))...” para. 0127).
As to claim 6, Rao modified by Poxon teaches The one or more processors of claim 1, Rao teaches wherein the one or more memory usage metrics is to indicate one of a plurality of attributes of the one or more storage locations, the one of the plurality of attributes selected by the API based, at least in part, on the one or more input parameters indicated to the API (“...Program 2 begins by allocating memory on the GPU. The way this program does this is by making the call: "CudaMalloc(&d_ptr, sizeof(int))." This allows a portion of memory at pointer "d" to be allocated a desired number of bits (indicated by sizeof(int))...” para. 0127).
As to claim 7, this is a system claim of claim 1. See rejection for claim 1 above. Further, teaches one or more processors (“…processors…” para. 0021).
As to claim 8, Rao modified by Poxon teaches The system of claim 7, Rao does not but Poxon teaches wherein the API is to receive one or more data values as a result of one or more API calls, the one or more data values indicating a type of the one or more memory usage metrics about the one or more storage locations (“...These statistics may include expiration of a timer, number of instructions executed, number of execution cycles, number of stalled cycles, LLC misses or hits, and so on. The number of stalled cycles may be approximated based on accesses (hits or misses) to a line fill buffer or an outstanding request buffer” para. 0014).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Rao by applying the teachings of Poxon because Poxon also teaches the same field of the invention of determining memory usage metrics/statistics for optimizing memory allocation (abstract and para. 0011).
As to claim 9, Rao modified by Poxon teaches the system of claim 7, Rao teaches wherein the API is to receive one or more data values as a result of one or more API calls, the one or more data values indicating the one or more storage locations (“...ensure that a GPU VA pointer does not collide with a CPU pointer provided by OS CPU allocation (e.g., like one returned by "malloc" C runtime API, etc.)” abstract).
As to claim 10, Rao modified by Poxon teaches The system of claim 7, Rao teaches wherein the pool of memory is usable by one or more graphics processing units (GPUs (“...graphics processing unit (GPU)...” abstract).
As to claims 11 - 12, these claims recite similar scope of claims 3 - 4. See rejection for claims 3 - 4 above.
As to claim 13, this claim recites similar scope of claim 2. See rejection for claim 2 above.
As to claim 14, this is a machine-readable medium claim of claim 1. See rejection for claim 1 above. Further, Rao teaches a machine-readable medium (“…By indicating a non-transitory storage medium it is not intend to limit characteristics of the medium, and can include a variety of storage mediums (e.g., programmable, erasable, nonprogrammable, read/write, read only, etc.) and "non-transitory" computer-readable media comprises all computer-readable media, with the sole exception being a transitory, propagating signal.” para. 0167) one or more processors (“…central processor unit 901…” para. 0054).
As to claim 15, this claim recites similar scope of claim 9. See rejection for claim 9 above.
As to claims 16 - 18, these claims recite similar scope of claims 8 - 10. See rejection for claims 8 - 10 above.
As to claims 19 - 20, these claims recite similar scope of claims 3 - 4. See rejection for claims 3 - 4 above.
As to claim 21, this claim recites similar scope of claim 2. See rejection for claim 2 above.
As to claim 22, this is a method claim of claim 1. See rejection for claim 1 above.
As to claim 23, this claim recites similar scope of claim 16. See rejection for claim 16 above.
As to claim 24, this claim recites similar scope of claim 9. See rejection for claim 9 above.
As to claim 25, this claim recites similar scope of claim 3. See rejection for claim 3 above.
As to claim 26, this claim recites similar scope of claim 12. See rejection for claim 12 above.
As to claim 28, this claim recites similar scope of claim 10. See rejection for claim 10 above.
As to claims 27 and 29, this claim recites similar scope of claim 2. See rejection for claim 2 above.
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record but not relied upon request is considered to be pertinent to applicant’s disclosure.
Pan et al., (US PUB 2020/0213246), discloses a method of accessing memory region using API call (title, abstract and figures 1 – 5).
Cheng, (US PUB 2021/0173917), discloses a method of processing request to access memory location based on the memory usage information (title, abstract and figures 1 – 32).
Robin, (US PUB 20100312984), discloses a method of memory allocation request by making function call with input parameter as a pointer to the memory region (title, abstract and figures 1 – 6).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHUONG N HOANG whose telephone number is (571)272-3763. The examiner can normally be reached 9:5-30.
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/PHUONG N HOANG/Examiner, Art Unit 2194 /KEVIN L YOUNG/Supervisory Patent Examiner, Art Unit 2194