DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/15/2026 has been entered.
Response to Amendment
Applicant’s amendment filed 6/15/2026 is acknowledged. Claims 1, 8 have been amended. Claims 13-21 remain withdrawn from consideration
Response to Arguments
Applicant’s arguments with respect to claims 1-12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US 2020/0203215 A1) in view of Yu et al. (US 9455198 B1) and Steimle (US 2005/0287729 A1).
Regarding claim 1, Jang teaches a semiconductor device (device in Figs. 1 to 12A-12C), comprising:
two or more fins (ACT1), the fins separated by one or more inter-fin trenches (trenches TR1) having an inter-fin trench depth (depth of trenches TR1);
a gate dielectric (GI of the gate line structure LST1 in Fig. 2B) over each of the two or more fins;
a gate (wordline WL in Fig. 2B) covering the gate dielectric of the two or more fins;
an isolation structure (ST3 in Fig. 2B) adjacent to the two or more fins, the isolation structure having a flat bottom and a depth greater than the inter-fin trench depth (as shown in Fig. 2B of Jang), the isolation structure filled with a dielectric (BI-GP1 in Fig. 2B & 8A includes a portion of PBI in the inter-fin trenches TR1, as shown in Fig. 6B) that also extends into the one or more inter-fin trenches to a common level in both the isolation structure and the inter-fin trenches (see Fig. 6A-8A);
wherein the two or more fins are included in a memory array (array of memory cells DS in MCR in Fig. 1 of Jang), and wherein the isolation structure separates the memory array from peripheral circuits (the peripheral circuit CPR).
But Jang does not teach that the dielectric is a single dielectric, and the peripheral circuits operate at a higher voltage than the memory array.
Yu teaches a semiconductor device (device in Fig. 2I of Yu), comprising: two or more fins (118), the fins separated by one or more inter-fin trenches (116) having an inter-fin trench depth (depth 116D of trench 116); a gate dielectric (gate insulation layer of the gate structure 130 described in column 8 lines 7-10 of Yu) over each of the two or more fins; a gate (gate electrode of gate structure 130) covering the gate dielectric of the two or more fins; an isolation structure (120X in Fig. 2I) adjacent to the two or more fins, the isolation structure having a flat bottom (flat surface of 114A, as shown in Fig. 2F of Yu) and a depth (depth 114D of trench 114A) greater than the inter-fin trench depth, the isolation structure filled with a single dielectric (insulating material 120 as shown in Fig. 2G of Yu) that also extends into the one or more inter-fin trenches to a common level (level of surface 120S in Fig. 2I) in both the isolation structure and the inter-fin trenches.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the isolation structure together with the inter-fin isolation structure using the same single dielectric material (120 of Yu), as disclosed by Yu, in order to simplify the manufacturing process.
But Jang in view of Yu does not teach that the peripheral circuits operate at a higher voltage than the memory array.
Steimle teaches a semiconductor device (Fig. 14 of Steimle) that comprises: a memory region (28) and a high-voltage region (26) at the peripheral region of the memory region (see [0009] of Steimle).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the peripheral circuits operate at a higher voltage while the memory array circuits operate at lower voltage in order to obtain lower power consumption.
Regarding claim 4, Jang-Yu-Steimle teaches all limitations of the semiconductor device of claim 1, and also teaches wherein the two or more fins include a fin lithographic dimension (distance between two adjacent fins), and a fin pitch is one lithographic dimension (as defined above).
Regarding claim 5, Jang-Yu-Steimle teaches all limitations of the semiconductor device of claim 1, and also teaches wherein the two or more fins include a fin lithographic dimension (this is defined to be half fin pitch), and a fin pitch is two lithographic dimensions (as defined above).
Regarding claim 6, Jang-Yu-Steimle teaches all limitations of the semiconductor device of claim 5, and also teaches wherein the isolation structure is a first isolation structure on a first side (right side) of the two or more fins (fins ACT1 adjacent to ST3) and further including a second isolation structure ( as implies in Fig. 1 of Jang, the isolation structure ST3 surrounds the memory cell array MCR. So there is another ST3 on the other side of the MCR) on a second side (left side) of the two or more fins.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Yu and Steimle, as applied to claim 1 above, and further in view of Chen (US 2023/0215915 A1) (hereinafter referred to as Chen2023).
Regarding claim 2, Jang-Yu-Steimle teaches all limitations of the semiconductor device of claim 1, but does not teach wherein the semiconductor device includes a DRAM memory array.
Chen2023 teaches a memory device (100 in Fig. 1A of Chen2023) comprising: a memory cell array (102) and a peripheral circuit (104); the memory cell array includes DRAM memory array (see [0034] of Chen2023).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used DRAM memory in the memory cell array of Jang due to its simple design and low cost compared to other types of memory.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Yu and Steimle, as applied to claim 1 above, and further in view of Phoa et al. (US 2017/0025533 A1).
Regarding claim 3, Jang-Yu-Steimle teaches all limitations of the semiconductor device of claim 1, but does not teach wherein an operating voltage of at least some components of the semiconductor device is 3.5 volts or greater.
Phoa teaches a memory device with high voltage transistor are utilized for I/O or other circuitry within the IC (see Abstract); the high-voltage transistor has threshold voltage greater than 3V (see [0020] of Phoa).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used high voltage transistor with threshold voltage greater than 3V in memory device of Jang-Yu-Steimle since these are known operating range of high-voltage device.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Yu and Steimle, as applied to claim 6 above, and further in view of Yoo et al. (US 2016/0155741 A1).
Regarding claim 7, Jang-Yu-Steimle teaches all limitations of the semiconductor device of claim 6, but does not teach wherein the first and second isolation structures are two lithographic dimensions wide.
Yoo teaches a fin-removing region (FRR) has width of one fin pitch.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the isolation structure with width of a fin pitch in order to optimize the device density.
As incorporated, the isolation structure (measured from one sidewall of a fin of one fin region to another sidewall of a fin of another fin region) would have width of a fin pitch. This is two lithographic dimension (as defined in claim 5 above).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Steimle in view of Yu.
Regarding claim 8, Steimle teaches a semiconductor device (memory device in Fig. 14 of Steimle), comprising:
a planar device (56) formed on a semiconductor substrate (12);
a device (58-60) formed on the semiconductor substrate adjacent the planar device, the device including:
one or more channels (channels of transistors 58-60);
a gate dielectric (38) over each of the one or more channels;
a gate (50-52, as labeled in Fig. 13) covering the gate dielectric of the one or more channels; and
wherein the device is included in a memory array (as described in [0009] of Steimle), and wherein the planar device is included in peripheral circuitry that operate at a higher voltage than the memory array (as described in [0008] of Steimle).
But Steimle does not teach that the device is a FinFET device, and that the one or more channels are fin channels, the fin channels separated by one or more inter-fin trenches having an inter-fin trench depth; and the semiconductor device comprising: an isolation structure separating the planar device from the FinFET device, the isolation structure having a flat bottom and a depth greater than the inter-fin trench depth, the isolation structure filled with a single dielectric that also extends into the one or more inter-fin trenches to a common level in both the isolation structure and the inter-fin trenches.
Yu teaches a semiconductor device (device in Fig. 2I of Yu), comprising: two or more fins (118), the fins separated by one or more inter-fin trenches (116) having an inter-fin trench depth (depth 116D of trench 116); a gate dielectric (gate insulation layer of the gate structure 130 described in column 8 lines 7-10 of Yu) over each of the two or more fins; a gate (gate electrode of gate structure 130) covering the gate dielectric of the two or more fins; an isolation structure (120X in Fig. 2I) adjacent to the two or more fins, the isolation structure having a flat bottom (flat surface of 114A, as shown in Fig. 2F of Yu) and a depth (depth 114D of trench 114A) greater than the inter-fin trench depth, the isolation structure filled with a single dielectric (insulating material 120 as shown in Fig. 2G of Yu) that also extends into the one or more inter-fin trenches to a common level (level of surface 120S in Fig. 2I) in both the isolation structure and the inter-fin trenches.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the isolation structure together with the inter-fin isolation structure using the same single dielectric material (120 of Yu), as disclosed by Yu, in order to simplify the manufacturing process.
Regarding claim 9, Steimle in view of Yu teaches all limitations of the semiconductor device of claim 8, and also teaches wherein the planar device includes a planar transistor (as shown in Fig. 14 of Steimle).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Steimle in view of Yu, as applied to claim 8 above, and further in view of Phoa.
Regarding claim 10, Steimle in view of Yu teaches all limitations of the semiconductor device of claim 8, but does not teach wherein an operating voltage of the semiconductor device is 3.5 volts or greater.
Phoa teaches a memory device with high voltage transistor are utilized for I/O or other circuitry within the IC (see Abstract); the high-voltage transistor has threshold voltage greater than 3V (see [0020] of Phoa).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used high voltage transistor with threshold voltage greater than 3V in memory device of Steimle-Yu since these are known operating range of high-voltage device.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Steimle in view of Yu, as applied to claim 8 above, and further in view of Chen2023.
Regarding claim 11, Steimle in view of Yu teaches all limitations of the semiconductor device of claim 8, but does not teach wherein the semiconductor device includes a DRAM memory array.
Chen2023 teaches a memory device (100 in Fig. 1A of Chen2023) comprising: a memory cell array (102) and a peripheral circuit (104); the memory cell array includes DRAM memory array (see [0034] of Chen2023).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used DRAM memory in the memory cell array of Steimle due to its simple design and low cost compared to other types of memory.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Steimle in view of Yu and Chen2023, as applied to claim 11 above, and further in view of Jang.
Regarding claim 12, Steimle-Yu-Chen2023 teaches all limitations of the semiconductor device of claim 11, but does not teach wherein the planar device is included in a wordline driver of the DRAM memory array.
Jang teaches that the word line driver transistors are placed in the peripheral circuit (see [0017] of Jang).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the planar device the wordline driver of the DRAM array, as disclosed by Jang, in order to simplify the layout of the memory cell region and to minimize electrical coupling with the memory cell region which could deteriorate the charge storage capability of the cells.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
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