Office Action Predictor
Application No. 17/720,231

APPLICATION PROGRAMMING INTERFACE TO MONITOR RESOURCE USAGE

Final Rejection §101§103
Filed
Apr 13, 2022
Examiner
TRUONG, LECHI
Art Unit
2194
Tech Center
2100 — Computer Architecture & Software
Assignee
Nvidia Corporation
OA Round
4 (Final)
87%
Grant Probability
Favorable
5-6
OA Rounds
3y 1m
To Grant
99%
With Interview

Examiner Intelligence

87%
Career Allow Rate
764 granted / 877 resolved
Without
With
+37.1%
Interview Lift
avg trend
3y 1m
Avg Prosecution
33 pending
910
Total Applications
career history

Statute-Specific Performance

§101
16.9%
-23.1% vs TC avg
§103
55.8%
+15.8% vs TC avg
§102
3.1%
-36.9% vs TC avg
§112
7.6%
-32.4% vs TC avg
Black line = Tech Center average estimate • Based on career data

Office Action

§101 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claims 1-24 are presented for the examination. § 101 2. 35 U.S.C. 101 reads as follows Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. 2. As to Claims 1, 2, 4, 7, 13, 15, 19, 20, 21 have been rejected under 35 USC 101 for abstract idea without significantly more. 3. As to claims 1, 2, 4, 7, 13, 15, 19, 20, 21, Under Step 2A, Prong 1, the "track a number of references to one or more computer resources remaining to be used by one or more computer programs, indicating reference, location, that the one or more computer programs lack a reference to the one more computer resources and deleting the one or more computer resources" recite a mental process since " track", "indicating" are functions that can be reasonably performed in the human mind with the aid of pen and paper through observation, evaluation, judgment, opinion. Under Prong 2, the additional element perform an application programming interface (API) to generate one or more data structures, computer resources remaining to be used by one or more computer programs are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using a generic computer component, the one or more data structures are to be modified in the event that a reference is created or deleted when the one or more computer programs start or stop referencing the one or more computer resources associated with the one or more graph handles merely a generic computer or generic computer components to perform the judicial exception, Accordingly, the additional elements do not integrate the recited judicial exception into a practical application, and the claim is therefore directed to the judicial exception. See MPEP 2106.05(f). Under Step 2B, the additional elements " perform an application programming interface (API) to generate one or more data structures"- this generally should have been a mental process although API could be a generic computer component if the spec describes it as actual computer hardware , "computer resources remaining to be used by one or more computer programs", - this this is just information that is being processed in the identified mental process and “such that the one or more data structures are to be modified in the event that a reference is created or deleted when the one or more computer programs start or stop referencing the one or more computer resources associated with the one or more graph handles” - this generally have been a mental process although the data structures could be a generic computer component if the spec describes it as software component in an actual computer hardware that amounts to merely generally linking the use of the judicial exception to a particular technological environment or field or use, and is merely applying the judicial exception, therefore, docs not amount to significantly more, hence, cannot provide an inventive concept. 4. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application. See MPEP 2106.05(d). Thus, the claim is not patent eligible. 5. As to claims 2, 4, 8, 14, 15, 20, 10, Under Step 2A, Prong 1, the " indicate at least a number of references associated with a computer program", " indicating at least the API" recite a mental process since , " indicated by the one or more data structures", "indicating one or more functions", "indicating a location corresponding to the one or more data structures", " indicate one or more destructor functions", "indicating" are functions that can be reasonably performed in the human mind with the aid of pen and paper through observation, evaluation, judgment, opinion. Under Prong 2, the additional element " perform an application programming interface (API) to generate one or more data structures , computer resources remaining to be used by one or more computer programs' are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using a generic computer component, or merely a generic computer or generic computer components to perform the judicial exception, Accordingly, the additional elements do not integrate the recited judicial exception into a practical application, and the claim is therefore directed to the judicial exception. See MPEP 2106.05(f). Under Step 2B, the additional elements " perform an application programming interface (API) to generate one or more data structures" , this generally should have been a mental process although API could be a generic computer component if the spec describes it as actual computer hardware, computer resources remaining to be used by one or more computer programs" this this is just information that is being processed in the identified mental process and should have been included in the mental process that amounts to merely generally linking the use of the judicial exception to a particular technological environment or field or use, and is merely applying the judicial exception, therefore, does not amount to significantly more, hence, cannot provide an inventive concept. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application. See MPEP 2106.05(d). Thus, the claim is not patent eligible. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 6. Claims 1, 7, 13, 19 are rejected under 35 U.S.C. 103 as being unpatentable over TOGAN( US 20160085545 A1) in view of Gould( US 8271996 B1) in view Yazdani(US 20180260255 A1) and further in view of Mullins( 20170155658 A1). As to claim 1, Togan teaches A processor, comprising: one or more circuits for application programming interface (API) to generate one or more data structures data structures to be used to track ( illustrated embodiments of the present invention may for the most part, be implemented using electronic components and circuits known to those skilled in the art, para[0017], In 7-12/ The computer system may for instance include at least one processing unit, associated memory and a number of input/output (I/O) devices. When executing the computer program, the computer system processes information according to the computer program and produces resultant output information via I/O devices, para[0083]/ computer program code 830 may comprise executable program code for implementing inter-component function calls[API] within a computer program, such program code may be operable for generating at least a first lower tier indirection data structure[data structures] associated with at least a first software component, the at least first lower tier indirection data structure comprising at least one entry indicating a location in memory of at least one function within the at least first software component, para[0076], In 1-12/ a lower tier indirection data structure associated with the new software component is generated comprising entries that indicate the locations in memory of the executable code for the respective functions within the new software component version, para[0068], In 1-10). Gould teaches perform an application programming interface (API) to generate one or more data structures( The open API may be invoked to create a reference structure (indicated by the fourth parameter) to an event queue (named by the first parameter) for event notifications, col 16, In 42-47/ An application programming interface may be invoked by code of a container other than said producer and said one or more consumers to create said event queue, col 2, In 36- 41); data structure including one or more graph handler at one or more locations to be used to track a number of references to one or more computer resources remaining to be used such that the one or more data structures are to be modified in the event that a reference is created or deleted when the one or more computer programs start or stop referencing the one or more computer resources associated with the one or more graph handles( Referring to FIG. 9, shown is an example of a list of event queue structures that may be created and maintained in kernel space for use in connection with the techniques described herein. The example 550 includes a list of event queue structures having a first entry denoted by HEAD pointer and a last entry denoted by the TAIL pointer. Each entry on the list may correspond to a single event queue created as a result of executing the create event queue API described in FIG. 3. Each entry on the list of event queue structures may be referred to as a handle structure created and specified as the handle_rv parameter of the create API call. Element 552 illustrates in more detail different fields that may be included in the handle structure for each event queue created. Element 552 may include a private data size 554, registration database (db) 556, ref count 558, col 19, In 60-67 to col 20, In 1-7/ At step 1212, ref count field of the handle (of the event queue associated with this reference structure) is decremented. At step 1214, a determination is made as to whether the ref count is 0. If so there are no current users of the event queue as indicated with the event queue handle structure's ref count=0, the handle may be removed from the global list of event queues. Storage associated with the remove handle structure may be made available for other uses, col 29, In 56-66/ Ref count 558 may be an integer value indicating a number of current users of the event queue. Ref count 558 may be used in an embodiment in connection with event queue maintenance, for example, to detect when event queue handle structures and resources may be made available for other uses, col 20, ln 25-30/For example, when the reference count (ref count 558 of FIG. 9) of the handle structure associated with an event queue reaches 0 indicating there are no users of the event queue, resources associated with the event queue may be made available for other uses (e.g., the handle structure may be deallocated), col 38, In 5-10/ At step 1212, ref count field of the handle (of the event queue associated with this reference structure) is decremented. At step 1214, a determination is made as to whether the ref count is 0. If so there are no current users of the event queue as indicated with the event queue handle structure's ref count=0, the handle may be removed from the global list of event queues. Storage associated with the remove handle structure may be made available for other use, col 29, In 55-66/ when the reference count (ref count 558 of FIG. 9) of the handle structure associated with an event queue reaches 0 indicating there are no users of the event queue, resources associated with the event queue may be made available for other uses (e.g., the handle structure may be deallocated). As described herein, processing may be performed to manage the reference count by incrementing the reference count with each open and create API call and accordingly decrementing the reference count on each close and destroy API call for the event queue handle structure, col 38, ln 5-15). It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Togan with Gould to incorporate the above feature because this keeps track of memory objects after they are created and delete those objects when they are no longer needed so that the memory being used becomes available again. Yazdani teaches generate the one or more data structures including one or more graph handles to be used to track a number of references to one or more computer resources remaining to be used by one or more computer programs such that the one or more data structures are to be modified in the event that a reference is created or deleted when the one or more computer programs start or stop referencing the one or more computer resources associated with the one or more graph handles( counter RC.sub.pt 302A tracks references from parent thread 302 to the object ABC(.1.) using a hierarchical counter data structure (discussed with reference to FIG. 3B) that keeps track of (1) the number of references in the thread (in this example, 4 variables make reference) made to the object ABC(.1.) from parent thread 302, para[0059], ln 4-10/ a local structure (ST) is also created as part of the parent thread counter RC.sub.pt 302A. Each structure (herein referred to as a hierarchical counter data structure 300A) includes member elements that are initialized, as described below, para[0068]/ The hierarchical counter data structure 300A includes, for example, member elements of a count value, a state of the object, a list of child counters and a pointer. Applying the member elements illustrated in FIG. 3B, the count value (inUse) is responsible for counting the number of references being made to an object by a particular counter. For example, if the count value is zero, no references are being made by the corresponding thread, para[0070]/ forms a hierarchical structure, which may be expressed as a directed tree graph, where the parent thread counter RC.sub.pt 302A is a root node and the child thread counter RC.sub.cd 306A is a leaf node of the root node. As additional references and pointers are formed, the directed tree graph scales to furth, para[0093], ln 12-21/ During the initialization period, the member elements in the hierarchical counter data structure 300A (also represented in FIG. 3D by items 11, 13, 15 . . . 29 and 31) are set to initial values. For example, inUse=0, isDead=FALSE, Child_List={ } and Parent=NULL. Each time a variable (e.g. ‘var a’) of the parent thread 302 references the object ABC(.1.), the hierarchical counter data structure 300A of the parent thread counter RC.sub.pt 302A is sent a command (e.g., an increment or ‘inc’) to be updated (e.g., modify one or more member elements in the hierarchical counter data structure 300A). In one embodiment, the increment occurs upon a first reference to the object, para[0078], ln 6-21/ updating the hierarchical counter data structure comprises increasing the parent count value of the parent thread counter when the parent thread adds a reference to the object and decreasing the parent count value of the parent thread counter when the parent thread removes the reference to the object; and increasing the child count value of the child reference counter when the child thread adds a reference to the object and decreasing the child count value of the child reference counter when the child thread removes the reference to the object, para[0005]) It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Togan and Gould with Yazdani to incorporate the above feature because this keeps track of memory objects after they are created and delete those objects when they are no longer needed so that the memory being used becomes available again. Mullins teaches a call of perform an application programming interface (API) comprising one or more locations in one or more data structures( such a request can be received via a network service API, such as a web service API. The request includes data identifying a location in the graph of the resource, para[0014], ln 6-10/ such a request 308 can be received via a network service API, such as a web service API (shown in FIG. 3A as the graph retrieval API 302). The facet request 308 includes data identifying a location in the graph of the resource (shown in FIG. 3A as the graph resource location 310), para[0060], ln 4-10/transmits a facet request 308 to the federated graph provider service 102. As discussed above, the facet request 308 includes a graph resource location 310 for the graph resource for which a facet is being requested, para[0071]). It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Togan, Gould and Yazdani with Mullins to incorporate the above feature because this exposes related data that is mastered by a multitude of other federated data providers, such as other network services operated by the same entity to extend a federated graph with third-party data and facilitates simultaneous communications with multiple networks. As to claims 7, 13, they are rejected for the same reason as to claim 1 above. In additional, Gould teaches Processor(The processor included in the host computer systems 14a-14n, col 9, In 36-40/ on-transitory machine-readable medium( A non-transitory computer readable medium, claim 15, In 1-3). 7. Claims 1, 7, 13, 19 are rejected under 35 U.S.C. 103 as being unpatentable over TOGAN( US 20160085545 A1) in view of Gould( US 8271996 B1) in view Yazdani(US 20180260255 A1) in view of Mullins( 20170155658 A1) and further in view of Kevner ( US 5956509 A). As to claim 2, Kevner teaches the one or more data structures indicate at least a number of references associated with the computer program( Referring now to FIG. 4A, the next level of the client data structure 208a contains an interface object 410 which is instantiated when the client application 200a has successfully established a connection with the service application 200b,co 11, In 63-67/The next level of the client data structure 208a contains a method object 416. Each method object 416 corresponds to a particular remote request. In the preferred embodiment, each interface object 410 can point to many method objects 416 as memory will permit, col 12, In 60-67/col 30, In 65-67) . It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Togan, Gould, Yazdani and Mullins with Kevner to incorporate the feature of data structures data structures to be used to count a number of identifiers of one or more storage locations because this allows the client to concurrently execute multiple remote requests within the same thread of execution. As to claim 12, Kevner teaches the information includes at least input data to the computer program( col 4, In 10-15) for the same reason as to claim 2. As to claim 15, Kevner teaches the use of the information is indicated by one or more references used by the computer program( col 18, In 26-35) for the same reason as to claim 2. As to claim 16, Kevner teaches the set of instructions further include instructions, which if performed by the one or more processors, cause the one or more processors to modify the one or more data structures based on the use of the information by the computer program( col 4, In 10-15) for the same reason as to claim 2 above. 8. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over TOGAN( US 20160085545 A1) in view of Gould( US 8271996 B1) in view Yazdani(US 20180260255 A1) in view of Mullins( 20170155658 A1) and further in view of Bohling(US 20140006874 A1). As to claim 3, Bohling teaches the storage location includes at least a region of memory( FIG. 1. A trace 18 data structure includes a trace identifier (ID) 50; a monitor parameter 52 used to determine the region of the application memory space 16 to monitor, para[0023], In 1-6). It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Togan, Gould, Yazdani and Mullins with Bohling to incorporate the feature of the information includes at least a region of memory because this provides a need in the art for improved techniques to monitor memory to debug errors. 9. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over TOGAN( US 20160085545 A1) in view of Gould( US 8271996 B1) in view Yazdani(US 20180260255 A1) in view of Mullins( 20170155658 A1) and further in view of Sankaran( 20090190591 A1). As to claim 4, Sankaran teaches the one or more circuits are to perform the API based at least in part on a parameter value indicating a location corresponding to the one or more data structures( The CLI command specifies address information that identifies the packet flow. In response to the command, API logic 310 creates and initializes a data structure in storage area 112 for storing forwarding information 114, and invokes or otherwise passes the address information to forwarding examination logic 316, para[0089], In 5- 15). It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Togan, Gould, Yazdani and Mullins with Sankaran to incorporate the feature of the one or more circuits are to perform the API based at least in part on a parameter value indicating a location corresponding to the one or more data structures because this determines whether a router correctly forwards packets provide for sending one or more network packets. 10. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over TOGAN( US 20160085545 A1) in view of Gould( US 8271996 B1) in view Yazdani(US 20180260255 A1) in view of Mullins( 20170155658 A1) and further in view of Abernethy( US 20070198281 A1). As to claim 5, Abernethy teaches the one or more circuits are further to execute one or more functions based on at least in part on the use of the information by the computer program( Upon distributing the synchronization group data structure to each of the communication devices, the communication monitors on the various communication devices proceed to perform a synchronization operation with the other communication devices, para[0045], In 1-6). It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Togan, Gould, Yazdani and Mullins with Abernethy to incorporate the feature of the one or more circuits are further to execute one or more functions based on at least in part on the use of the information by the computer program because this monitors are provided on one or more communication devices and/or systems of the same or different types. 11. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over TOGAN( US 20160085545 A1) in view of Gould( US 8271996 B1) in view Yazdani(US 20180260255 A1) in view of Mullins( 20170155658 A1) and further in view of Jiao(US 20080246773 A1). As to claim 6, Jiao teaches the computer program is executable by one or more graphics processing units (GPUs)( a "graphics processing object" may comprise a data structure that specifies a type of graphics processing information that GPU 6 may use to perform a graphics operation, para[0020], In 3-9). It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Togan, Gould, Yazdani and Mullins with Jiao to incorporate the feature of the computer program is executable by one or more graphics processing units (GPUs) because this allows GPU may implement a number of socalled "primitive" graphics operations. 12. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over TOGAN( US 20160085545 A1) in view of Gould( US 8271996 B1) in view Yazdani(US 20180260255 A1) in view of Mullins( 20170155658 A1) and further in view of Bhaya(US 20180190271 A1). As to claim 8, Bhaya teaches the one or more processors are further to: obtain code indicating at least the API; and perform the API by at least executing the code( The data processing system 102 can include a direct action API 116 designed and constructed to generate, based on the trigger keyword, an action data structure responsive to the request. Processors of the data processing system 102 can invoke the direct action API 116 to execute scripts that generate a data structure , para[0043], In 1-10). It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Togan, Gould and Kawamoto with Bhaya to incorporate the feature of obtain code indicating at least the API; and perform the API by at least executing the code because this determines necessary parameters and can package the information into an action data structure, which can then be sent to another component for the service provider computing device to be fulfilled. 13. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over TOGAN( US 20160085545 A1) in view of Gould( US 8271996 B1) in view Yazdani(US 20180260255 A1) in view of Mullins( 20170155658 A1) and further in view of Gula( US 20140007241 A1). As to claim 9, Gula teaches the one or more data structures encode a count of one or more references associated with the information( an operation 620 may then instantiate various counters and lists to track the trust relationships associated with each IP address listed in the ConnectedServers data structure. For example, in one implementation, the counters instantiated in operation 620 may track (for each IP address listed in the ConnectedServers data structure) a number of connections to the IP address from remotely exploitable servers, para[0070], In 1 -10/ As such, operations 630 through 670 may be iteratively performed until all IP addresses in the ConnectedServers data structure have been processed to update the corresponding trust relationship counters and lists, para[0072], In 16-21). It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Togan, Gould and Kawamoto with Gula to incorporate the feature of the one or more data structures encode a count of one or more references associated with the information because this exists for a network security system that can leverage active and passive vulnerability discovery to identify services, client software, trust relationships. 14. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over TOGAN( US 20160085545 A1) in view of Gould( US 8271996 B1) in view Yazdani(US 20180260255 A1) in view of Mullins( 20170155658 A1) and further in view of KRIVOBORODO(DE 102012006310 A1). As to claim 10, Krivoborodo teaches the one or more data structures indicate one or more destructor functions(the data structure is determined to determine the destructors 235-1 the object file 230-1 searched for destructors, Sec: In one step 310 becomes an object file 230-1, In 12-15/ The destructor is the inverse function of the constructor, Sec: In the following, some aspects of a conventional compilation process will be described in more detail, In 7-10). It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Togan, Gould, Yazdani and Mullins with Krivoborod to incorporate the feature of the one or more data structures indicate one or more destructor functions because this executes a method for reduction of storage requirement of an application (3) a computer. 15. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over TOGAN( US 20160085545 A1) in view of Gould( US 8271996 B1) in view Yazdani(US 20180260255 A1) in view of Mullins( 20170155658 A1) further in view of Venkataramani(US 20180157471 A1). As to claim 11, Venkataramani teaches computer program is executable by at least one or more parallel processing units (PPUs)( the function mapping table 1600 may include mappings for more functions. In some embodiments, the function mapping table 1600 (or one or more other data structures) may map functions for source programs written in other programming environments to PPU library functions. The mapping of source program functions to PPU library functions may be determined manually by selecting PPU library functions that perform equivalent functions to the source program functions, para[0197]). It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Togan, Gould, Yazdani and Mullins with Venkataramani to incorporate the feature of computer program is executable by at least one or more parallel processing units (PPUs) because this facilitate the creation of computer programs to be run on PPUs. 16. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over TOGAN( US 20160085545 A1) in view of Gould( US 8271996 B1) in view Yazdani(US 20180260255 A1) in view of Mullins( 20170155658 A1) and further in view of Osminer(US 9563420 B2). As to claim 14, Osminer teaches further include instructions, which if performed by the one or more processors, cause the one or more processors to perform the API based at least in part on a parameter value indicating a number of references( generating using at least the second software a data structure comprising a listing of all APIs that can be called by the first software; recursively examining, using at least the second software, all classes on the file path to identify library calls made by the first software; and generating, using at least the second software, a call report including at least the identified library calls, col 6, In 50-60/ second software component is implemented to: (i) receive a computer program to be evaluated from the first software component; (ii) generate a data structure comprising a listing of all APIs that can be called by the computer program, including a listing of all public methods on all public classes; and (iii) recursively evaluate all classes on a file path to identify calls made by the computer program (including in one implementation identifying constituent methods associated with each class on the file path, and disassembling each of the constituent methods that reference calls within the listing into a plurality of instructions to identify one or more API calls therein); (iv) provide a report including at least the identified library calls and an indication of use of one or more deprecated APIs; and (v) provide one or more placeholders configured to replace the one or more deprecated APIs, col 8, In 35-51). It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Togan, Gould, Yazdani and Mullins with Osminer to incorporate the feature of perform the API based at least in part on a parameter value indicating a number of references because this provides the functionality described by the API is said to be an implementation of the API. 17. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over TOGAN( US 20160085545 A1) in view of Gould( US 8271996 B1) in view Yazdani(US 20180260255 A1) in view of Mullins( 20170155658 A1) and further in view of Huang(US 8296741 B1). As to claim 17, Huang teaches teach the set of instructions further include instructions, which if performed by the one or more processors, cause the one or more processors to associate the one or more data structures with one or more graph data structures( the simulation module 212 uses a graph data structure referred to herein as a "tracker graph" to track the classes and functions, col 4, In 43-47/ tracker graph is merely a visual depiction of a corresponding data structure, and that there are many different ways to represent the graph and structure the data, col 6, In 1-15). It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Togan, Gould, Yazdani and Mullins with Huang to incorporate the feature of the set of instructions further include instructions, which if performed by the one or more processors, cause the one or more processors to associate the one or more data structures with one or more graph data structures because this identifies functions/methods in that class that can be invoked from the entry points. 18. Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over TOGAN( US 20160085545 A1) in view of Gould( US 8271996 B1) in view Yazdani(US 20180260255 A1) in view of Mullins( 20170155658 A1) and further in view of BENTHIN( US 20190318445 A1). As to claim 18, Benthin teaches the computer program is executable by one or more general purpose graphics processing units (GPGPUs)( The EU arrays 502A-502F, 504A-504F each include multiple execution units, which are general-purpose graphics processing units capable of performing floating-point and integer/fixed-point logic operations in service of a graphics, media, or compute operation, including graphics, media, or compute shader programs, para[0076], In 10- 15/ A graphics processing apparatus comprising: one or more cores to execute graphics instructions including instructions to perform ray tracing operations with a hierarchical acceleration data structure comprising a plurality of hierarchically arranged nodes including lowest level nodes, para[0274], In 1-16). It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Togan, Gould, Yazdani and Mullins with Benthin to incorporate the feature of the computer program is executable by one or more general purpose graphics processing units (GPGPUs) because this instructions to perform ray tracing operations. 19. Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over TOGAN( US 20160085545 A1) in view of Gould( US 8271996 B1) in view Yazdani(US 20180260255 A1) in view of Mullins( 20170155658 A1) and further in view of East( US 5187790 A). As to claim 19, it is rejected for the same reason as to claim 1 above. In additional, Kawamoto teaches indicating that the one or more computer programs lack a reference to the one more computer resources and deallocate the one or more computer resources( Step S403: The frame creator 10 calls the generation heap creating processing shown in FIG. 4B so that the generation heap creator 20 creates a generation heap, para[0126], In 1-5/ deallocation of unnecessary objects is performed based on the reference counting system in addition to the markand-sweep system. To be more specific, an object is deallocated in the steps S24 and S25 by the reference counting upon the reference count falls to 0, and objects that are part of a cyclic data structure arc deallocated in the step S1701 that is performed when the available memory area in a generation heap falls short, Note that the step S1701 is performed only when there is not sufficient memory area, which occurs rarely as the steps S24 and S25 are performed on each applicable occasion to deallocate objects based on the reference counting system para[0327], In 1-10/ When the reference counter of an object falls to O, the reference count modifier 94 instructs the object deallocator 95 to deallocate the object, para[0280], In 3-7/ The reference counting system operates by keeping, in management information of each object, a count showing how many references there are to that object. The reference count is incremented or decremented each time a reference is modified. An object is collected when a reference count falls to zero, para[0012]). East teaches indicating that the one or more computer programs lack a reference to the one more computer resources and deleting the one or more computer resources( The pointer count 364 represents the number of pointers that have been taken out on the object, plus one for a non-zero object ID count When an object ID, object container pointer, or reference object ID is deleted, the object ID count 366 of the object is decremented. If the resultant object ID count is zero, the pointer count 364 is decremented, and then the process of deleting the object is begun by calling an object type-specific remove routine to initiate any required object type-specific removal actions, such as canceling I/O, col 11, In 65-67 to col 12, In 1-17). It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Togan, Gould, Yazdani and Mullins with East to incorporate the above feature because this be able to automatically deallocate resources, such as input/output devices, no longer needed by a process. 20. Claims 20, 21 are rejected under 35 U.S.C. 103 as being unpatentable over TOGAN( US 20160085545 A1) in view of Gould( US 8271996 B1) in view Yazdani(US 20180260255 A1) in view of Mullins( 20170155658 A1) in view of East( US 5187790 A) and further in view of Hua(US 20150149689 A1). As to claim 20, Hua teaches executing one or more functions based at least in part on a number of references indicated by the one or more data structures( storing the original function lookup data structure includes storing an identifier for each function that the application program calls and respective memory addresses for each of those identified functions at which the processor may locate the function and execute it, para[0030], In 3-10). It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Togan, Gould, Yazdani and Mullins and East with Hua to incorporate the feature of because this provide that higher processing speed to find and execute the functions. As to claim 21, Hua teaches performing the API based at least in part on one or more parameter values indicating one or more functions( para[0026], In 9-17) for the same reason as to claim 20 above. 21. Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over TOGAN( US 20160085545 A1) in view of Gould( US 8271996 B1) in view Yazdani(US 20180260255 A1) in view of Mullins( 20170155658 A1) in view of East( US 5187790 A) and further in view of Koneru( US 20190235917 A1). As to claim 22, Koneru teaches the API is a runtime API(The command queue list maintained by the parent context is a list of software command queues created by different runtimes (APIs), para[0336], In 1-3). It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Togan, Gould, Yazdani and Mullins and East with Koneru to incorporate the feature of the API is a runtime API because this allows fast and efficient management of code blocks in computation rich applications. 22. Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over TOGAN( US 20160085545 A1) in view of Gould( US 8271996 B1) in view Yazdani(US 20180260255 A1) in view of Mullins( 20170155658 A1) in view of East( US 5187790 A) further in view of Flynn(US 20120151118 A1). As to claim 23, Flynn teaches the computer program is executable by one or more central processing units (CPUs)( tracks write operations in process during normal operation of the storage device 102 using a data structure such as an in-flight tree, para[0234], In 1-5/ power reduction management described above may be leveraged to implement an auto-commit memory capable of implementing memory semantic write operations (e.g., persistent writes) at CPU memory write granularity and speed Memory semantic operations may operate at a CPU-level of granularity (e.g., single bytes, words, cache lines, or the like), para[0248], In 1-15). It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Togan, Gould, Yazdani and Mullins and East with Flynn to incorporate the feature of the computer program is executable by one or more central processing units (CPUs) because this operates at CPU memory granularity and speed, without the need for corresponding "commit" commands. 23. Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over TOGAN( US 20160085545 A1) in view of Gould( US 8271996 B1) in view Yazdani(US 20180260255 A1) in view of Mullins( 20170155658 A1) in view of East( US 5187790 A) and further in view of Gould( US 8271996 B1). As to claim 24, Gould teaches obtaining one or more status indications as a result of performing the API( f a list of event queue structures that may be created and maintained in kernel space for use in connection with the techniques described herein. The example 550 includes a list of event queue structures having a first entry denoted by HEAD pointer and a last entry denoted by the TAIL pointer. Each entry on the list may correspond to a single event queue created as a result of executing the create event queue API described in FIG. 3, col 19, In 60-67). It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Togan, Gould, Yazdani and Mullins and East with Gould to incorporate the feature of obtaining one or more status indications as a result of performing the API because this utilizes a flexible and efficient communication model and facility allowing communications to be exchanged between executing code modules. Response to the argument: Applicant amendment filed on 11/17/2025 has been considered but they are not persuasive: Applicant argued in substance that : (1) “ Applicant respectfully submits that these features result in claims that even more clearly fall within the scope of patent-eligible subject matter”. (1) " claim 1 has been amended, for example, in the interest of compact prosecution. Support for all amended claims can be found in the specification, e.g., at paragraphs [0054], [0067], [0078], and [0079], and no new matter has been added by these amendments. Applicant respectfully submits that Togan, Gould, and Kawamoto, either alone or in combination, fail to teach or suggest claim 1 ". . Examiner respectfully disagreed with Applicant's remarks: As to the point(1), As to claims 1, 2, 4, 7, 13, 15, 19, 20, 21, Under Step 2A, Prong 1, the "track a number of references to one or more computer resources remaining to be used by one or more computer programs, indicating reference, location, that the one or more computer programs lack a reference to the one more computer resources and deleting the one or more computer resources" recite a mental process since " track", "indicating" are functions that can be reasonably performed in the human mind with the aid of pen and paper through observation, evaluation, judgment, opinion. Under Prong 2, the additional element perform an application programming interface (API) to generate one or more data structures, computer resources remaining to be used by one or more computer programs are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using a generic computer component, the one or more data structures are to be modified in the event that a reference is created or deleted when the one or more computer programs start or stop referencing the one or more computer resources associated with the one or more graph handles merely a generic computer or generic computer components to perform the judicial exception, Accordingly, the additional elements do not integrate the recited judicial exception into a practical application, and the claim is therefore directed to the judicial exception. See MPEP 2106.05(f). Under Step 2B, the additional elements " perform an application programming interface (API) to generate one or more data structures"- this generally should have been a mental process although API could be a generic computer component if the spec describes it as actual computer hardware , "computer resources remaining to be used by one or more computer programs", - this this is just information that is being processed in the identified mental process and “such that the one or more data structures are to be modified in the event that a reference is created or deleted when the one or more computer programs start or stop referencing the one or more computer resources associated with the one or more graph handles” - this generally have been a mental process although the data structures could be a generic computer component if the spec describes it as software component in an actual computer hardware that amounts to merely generally linking the use of the judicial exception to a particular technological environment or field or use, and is merely applying the judicial exception, therefore, docs not amount to significantly more, hence, cannot provide an inventive concept. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application. See MPEP 2106.05(d). Thus, the claim is not patent eligible. As to claims 2, 4, 8, 14, 15, 20, 10, Under Step 2A, Prong 1, the " indicate at least a number of references associated with a computer program", " indicating at least the API" recite a mental process since , " indicated by the one or more data structures", "indicating one or more functions", "indicating a location corresponding to the one or more data structures", " indicate one or more destructor functions", "indicating" are functions that can be reasonably performed in the human mind with the aid of pen and paper through observation, evaluation, judgment, opinion. Under Prong 2, the additional element " perform an application programming interface (API) to generate one or more data structures , computer resources remaining to be used by one or more computer programs' are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using a generic computer component, or merely a generic computer or generic computer components to perform the judicial exception, Accordingly, the additional elements do not integrate the recited judicial exception into a practical application, and the claim is therefore directed to the judicial exception. See MPEP 2106.05(f). Under Step 2B, the additional elements " perform an application programming interface (API) to generate one or more data structures", this generally should have been a mental process although API could be a generic computer component if the spec describes it as actual computer hardware, computer resources remaining to be used by one or more computer programs" this this is just information that is being processed in the identified mental process and should have been included in the mental process that amounts to merely generally linking the use of the judicial exception to a particular technological environment or field or use, and is merely applying the judicial exception, therefore, does not amount to significantly more, hence, cannot provide an inventive concept. The claim does not include additional elements that are sufficient to amount to 8. significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application. See MPEP 2106.05(d). Thus, the claim is not patent eligible. As to the point (2), Gould teaches The open API may be invoked to create a reference structure (indicated by the fourth parameter) to an event queue (named by the first parameter) for event notifications, col 16, In 42-47/ An application programming interface may be invoked by code of a container other than said producer and said one or more consumers to create said event queue, col 2, In 36- 41/Referring to FIG. 9, shown is an example of a list of event queue structures that may be created and maintained in kernel space for use in connection with the techniques described herein. The example 550 includes a list of event queue structures having a first entry denoted by HEAD pointer and a last entry denoted by the TAIL pointer. Each entry on the list may correspond to a single event queue created as a result of executing the create event queue API described in FIG. 3. Each entry on the list of event queue structures may be referred to as a handle structure created and specified as the handle_rv parameter of the create API call. Element 552 illustrates in more detail different fields that may be included in the handle structure for each event queue created. Element 552 may include a private data size 554, registration database (db) 556, ref count 558, col 19, In 60-67 to col 20, In 1-7/ At step 1212, ref count field of the handle (of the event queue associated with this reference structure) is decremented. At step 1214, a determination is made as to whether the ref count is 0. If so there are no current users of the event queue as indicated with the event queue handle structure's ref count=0, the handle may be removed from the global list of event queues. Storage associated with the remove handle structure may be made available for other uses, col 29, In 56-66/ Ref count 558 may be an integer value indicating a number of current users of the event queue. Ref count 558 may be used in an embodiment in connection with event queue maintenance, for example, to detect when event queue handle structures and resources may be made available for other uses, col 20, ln 25-30/For example, when the reference count (ref count 558 of FIG. 9) of the handle structure associated with an event queue reaches 0 indicating there are no users of the event queue, resources associated with the event queue may be made available for other uses (e.g., the handle structure may be deallocated), col 38, In 5-10/ At step 1212, ref count field of the handle (of the event queue associated with this reference structure) is decremented. At step 1214, a determination is made as to whether the ref count is 0. If so there are no current users of the event queue as indicated with the event queue handle structure's ref count=0, the handle may be removed from the global list of event queues. Storage associated with the remove handle structure may be made available for other use, col 29, In 55-66/ when the reference count (ref count 558 of FIG. 9) of the handle structure associated with an event queue reaches 0 indicating there are no users of the event queue, resources associated with the event queue may be made available for other uses (e.g., the handle structure may be deallocated). As described herein, processing may be performed to manage the reference count by incrementing the reference count with each open and create API call and accordingly decrementing the reference count on each close and destroy API call for the event queue handle structure, col 38, ln 5-15). Yazdani teaches ( counter RC.sub.pt 302A tracks references from parent thread 302 to the object ABC(.1.) using a hierarchical counter data structure (discussed with reference to FIG. 3B) that keeps track of (1) the number of references in the thread (in this example, 4 variables make reference) made to the object ABC(.1.) from parent thread 302, para[0059], ln 4-10/ a local structure (ST) is also created as part of the parent thread counter RC.sub.pt 302A. Each structure (herein referred to as a hierarchical counter data structure 300A) includes member elements that are initialized, as described below, para[0068]/ The hierarchical counter data structure 300A includes, for example, member elements of a count value, a state of the object, a list of child counters and a pointer. Applying the member elements illustrated in FIG. 3B, the count value (inUse) is responsible for counting the number of references being made to an object by a particular counter. For example, if the count value is zero, no references are being made by the corresponding thread, para[0070]/ forms a hierarchical structure, which may be expressed as a directed tree graph, where the parent thread counter RC.sub.pt 302A is a root node and the child thread counter RC.sub.cd 306A is a leaf node of the root node. As additional references and pointers are formed, the directed tree graph scales to furth, para[0093], ln 12-21/ During the initialization period, the member elements in the hierarchical counter data structure 300A (also represented in FIG. 3D by items 11, 13, 15 . . . 29 and 31) are set to initial values. For example, inUse=0, isDead=FALSE, Child_List={ } and Parent=NULL. Each time a variable (e.g. ‘var a’) of the parent thread 302 references the object ABC(.1.), the hierarchical counter data structure 300A of the parent thread counter RC.sub.pt 302A is sent a command (e.g., an increment or ‘inc’) to be updated (e.g., modify one or more member elements in the hierarchical counter data structure 300A). In one embodiment, the increment occurs upon a first reference to the object, para[0078], ln 6-21/ updating the hierarchical counter data structure comprises increasing the parent count value of the parent thread counter when the parent thread adds a reference to the object and decreasing the parent count value of the parent thread counter when the parent thread removes the reference to the object; and increasing the child count value of the child reference counter when the child thread adds a reference to the object and decreasing the child count value of the child reference counter when the child thread removes the reference to the object, para[0005]) Mullins teaches such a request can be received via a network service API, such as a web service API. The request includes data identifying a location in the graph of the resource, para[0014], ln 6-10/ such a request 308 can be received via a network service API, such as a web service API (shown in FIG. 3A as the graph retrieval API 302). The facet request 308 includes data identifying a location in the graph of the resource (shown in FIG. 3A as the graph resource location 310), para[0060], ln 4-10/transmits a facet request 308 to the federated graph provider service 102. As discussed above, the facet request 308 includes a graph resource location 310 for the graph resource for which a facet is being requested, para[0071]). Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Conclusion US 20180260255 A1 teaches The parent thread counter RC.sub.pt 302A tracks references from parent thread 302 to the object ABC(.1.) using a hierarchical counter data structure (discussed with reference to FIG. 3B) that keeps track of (1) the number of references in the thread (in this example, 4 variables make reference) made to the object ABC(.1.) US 20150261670 A1 teaches IG. 1 is a data structure diagram illustrating an example of reference-counted objects. In this reference graph, an edge such as 101 represents a reference (e.g., a pointer, a handle, an identifier, an address, and/or another appropriate mechanism that facilitates the access of an object). For each object, the corresponding reference count value indicates the number of references to the object. For instance, object 104 has 3 references to it, namely by objects 102, 103, and 105. US 20030191783 A1 teaches At 500, a reference count is maintained for each of the objects, the reference count indicating the number of incoming pointers to each object. At 502, the reference counts are updated each time the graph structure is altered. At 504, a timestamp is recorded for an object each time the reference count for the object changes. The timestamp may be a counter that is incremented on every pointer store. It may be stored in a record generated each time a change is made to the graph structure. At 506, an object is indicated as dead when its reference count goes. US 20080052693 A1 teaches A data structure referred to as "object descriptor list" is generated in the SIMD system. The data structure is used to keep track of pointers, which may be eligible as candidate or target pointers in a program. Each entry in the object descriptor list holds at least the following attributes corresponding to a US 20040181782 A1 teaches The increment data 312 may be stored in a raw data structure 314 as indicated by the object column and reference count column, which reflect the number of times a particular object has been referenced. A filter function 316 applies a probabilistic heuristic profile in the form of a predetermined count criterion to the data in the raw data structure 314 to filer out the objects deemed to be lingering. In the context of the present patent application, the term "heuristics" refers to techniques involving parametric data that measure or relate to a physical property, e.g., size, count, et cetera, associated with the objects of a reference graph. In one US 20110138368 A1 teaches count element 210 and 215 can specify location information for the call graph. More particularly, each count element can specify information that indicates the position of the function as displayed within the call graph, with respect to parent, sibling, and descendent functions that also may be displayed within the call graph. For example, each count element can indicate which function called function A and the function to which function A passed control upon exit for the invocations of function A represented by each respective count element. US 70083701 teaches creates an ACS list 2006, stores the pointer to the list in rule 1's "ACS list" field and decrements the counter in the dynamic portion of rule 1's "ACS list" field from 4 to 3. to 1, set an "s" value in the flags field to indicate US 20130019254 teaches set the reference ed string, and may return a value that represents the location of the that this is a reference memory as the handle value. US 20090327372 teaches update the free space counts on the fly, whenever a multiobject is allocated from the region, freed in the region, or moved out from the region Any inquiry concerning this communication or earlier communications from the examiner should be directed to LECHI TRUONG whose telephone number is (571)272-3767. The examiner can normally be reached 10-8 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpracticc. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor Young Kevin can be reached on (571)270-3180. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LECHI TRUONG/Primary Examiner, Art Unit 2194
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Prosecution Timeline

Apr 13, 2022
Application Filed
Aug 26, 2023
Non-Final Rejection — §101, §103
Mar 08, 2024
Response Filed
Jun 11, 2024
Final Rejection — §101, §103
Sep 10, 2024
Interview Requested
Oct 23, 2024
Examiner Interview Summary
Oct 23, 2024
Applicant Interview (Telephonic)
Dec 17, 2024
Notice of Allowance
Apr 08, 2025
Request for Continued Examination
Apr 15, 2025
Response after Non-Final Action
Jul 11, 2025
Non-Final Rejection — §101, §103
Aug 22, 2025
Interview Requested
Sep 30, 2025
Applicant Interview (Telephonic)
Oct 02, 2025
Examiner Interview Summary
Nov 17, 2025
Response Filed
Feb 15, 2026
Final Rejection — §101, §103
Mar 12, 2026
Interview Requested
Apr 03, 2026
Request for Continued Examination
Apr 08, 2026
Response after Non-Final Action

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99%
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3y 1m
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