DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 08/21/2025 have been fully considered but they are not persuasive. Regarding the argument that Lo ‘736 as modified by Chen ‘233 does not meet the amended claim 1 and 10 limitation of “wherein the support member comprises an organic material”. Note that Examiner has interpreted the structure of 118 and 120 as the support member and as described below 120 is disclosed as an epoxy material.
Regarding the further amendments of claim 1 and 10, as presented in the argument below, Chen ‘233 is relied on to provide the teaching of a semiconductor chip having a configuration of the insulating layer, (210) of Chen ‘233, in direct contact with the protection film, (Top Layer DI2) of Chen ‘233, and this teaching is incorporated in the device of Lo ‘736 (the insulating layer (64) would be in direct contact with the protection film (110B)). As described below Lo ‘736 as modified by Chen ‘233, as presented in claims 1 and 10, meets the amended claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 7-9, 21-22 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Lo et al. (US 2022/0068736 A1, hereinafter Lo ‘736) in view of Chen et al. (US 2020/0343223 A1, hereinafter Chen ‘233), in view of the following arguments.
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With respect to Claim 1 Lo ‘736 discloses a semiconductor package (package component 200 in Fig 1-11 and Fig 23-29 of Lo ‘736) comprising:
a wiring structure (60, Fig 1 of Lo ‘736, Para [0023 and 0024]) including at least one wiring layer (wiring structure 60 shows multiple wiring layers, Fig 1 of Lo ‘736, Para [0022], hereinafter WL);
a semiconductor chip (50, Fig 3 of Lo ‘736, Para [0036]) disposed on the wiring structure (60) and connected to the wiring structure (60) (Para [0022] of Lo ‘736 discloses connection of 50 to 60);
a first connecting terminal (left most terminal 66, Fig 1 of Lo ‘736, Para [0025], hereinafter FCT) and a second connecting terminal (right most terminal 66, Fig 1 of Lo ‘736, Para [0025], hereinafter SCT) formed on a first surface (pad 62, Fig 1 of Lo ‘736, Para [0025]) of the wiring structure (60);
a support member (support member comprised of 118 and 120, Fig 5 of Lo ‘736, Para [0044], hereinafter SM) spaced apart from the wiring structure (60) (Fig 5 of Lo ‘736 shows 118/120 is spaced apart from 60) wherein the support member (118/120) comprises an organic material (Para [0045] discloses 120 as epoxy, therefore support member 118/120 comprises organic material);
a dummy connecting terminal (connectors 112 under 118/120, Fig 6 of Lo ‘736, Para [0044-0045], hereinafter DCT) (“dummy connecting terminal” is an intended use statement. Regardless, the prior art Lo ‘736 meets the “dummy connecting terminal” intended use.) formed on a first surface (lower surface of 118/120, Fig 6, Para [0045]) of the support member (118/120);
a mold layer (mold layer comprised of 116, 134, 220 and 218, Fig 29 of Lo ‘736, Para [0037, 0042, 0079, 0080], hereinafter ML) covering a side surface (left or right of 114, Fig 7 of Lo ‘736, Para [0048]) of the wiring structure (60), a first surface (top of 50, Fig 27 of Lo ‘736, Para [0048]) of the semiconductor chip (50), and a second surface (top of 118, Fig 29 of Lo ‘736, Para [0079]) and a side surface (left or right of 118/120, Fig 29, Para [0080]) of the support member (118/120);
a protective film (110B, Fig 2 of Lo ‘736, Para [0032]) disposed between the dummy connecting terminal (DCT) and at least one of the first (FCT) and second connecting (SCT) terminals (Fig 6 of Lo ‘736 discloses 110B disposed between DCT and FCT and SCT); and
an insulating layer (64, Fig 1 of Lo ‘736, Para [0024]) and disposed between the first (FCT) and second connecting terminals (SCT)(Fig 1 of Lo ‘736 discloses 64 disposed between FCT and SCT), wherein the insulating layer (64) is not in contact with the dummy connecting terminal (DCT) (Fig 6 of Lo ‘736 discloses 64 is not in contact with DCT)
But Lo ‘736 fails to explicitly disclose an insulating layer in contact with the protective film.
Nevertheless, in a related endeavor (Fig 1A-2E of Chen ‘223), Chen ‘223 teaches an insulating layer (212, Fig 1C of Chen ‘223, Para [0039]) in contact with the protective film (Top Layer of DI2 as shown in Fig 2E of Chen ‘233)
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chen ‘233’s teaching of having the insulating layer in direct contact with the protective film into Lo ‘736’s device. The ordinary artisan would have been motivated to modify Lo ‘736 in the manner set forth above, at least, because the arrangement of the chip insulating layer in direct contact with the protective film results in a lower profile package which saves valuable vertical direction real estate.
As incorporated, the configuration of the insulating layer (210) of Chen ‘233 in direct contact with the protection film (Top Layer DI2) of Chen ‘233 in the device of Lo ‘736 (the insulating layer (64) would be in direct contact with the protection film (110B)).
Lo ‘736 as modified by Chen ‘233 further discloses wherein the protective film (110B) includes a first opening (one of openings for connections to 118/120 as shown in annotated Fig 5 of Lo ‘736),
the insulating layer (64 of Lo ‘736 as modified above by 210 of Chen ‘233 so that 64 is in direct contact with protection film 110B) includes a second opening (one of the openings in 64 of Lo ‘736 as modified above by 210 of Chen ‘233 so that 64 is in direct contact with protection film 110B of Lo ‘736) extending to the first opening (one of openings for connections to 118/120 as shown in annotated Fig 5 of Lo ‘736) (64 of Lo ‘736 as modified above by 210 of Chen ‘233 so that 64 is in direct contact with protection film 110B of Lo ‘736, so the second openings in that film, where the electrical contacts of the semiconductor chip pass from the chip through the protection layer 64 as modified by Chen ‘233 so it is in direct contact to 110B of Lo ‘736 (as described above), therefore as the modified protective layer 64 is in direct contact with 110B the second openings extend to the first openings),
the first connecting terminal (FCT) is arranged within the second opening (one of the openings in 64 of Lo ‘736 as modified above by 210 of Chen ‘233 so that 64 is in direct contact with protection film 110B of Lo ‘736)(Fig 5 of Lo ‘736 discloses connecting terminals arranged with second openings in 64), and
the dummy connecting terminal (DCT) is arranged within the first opening (one of openings for connections to 118/120 as shown in annotated Fig 5 of Lo ‘736)(Fig 5 of Lo ‘736 discloses dummy terminals arranged with first opening).
With respect to Claim 2 Lo ‘736 as modified by Chen ‘233 discloses all limitations of the semiconductor package of claim 1, and Lo ‘736 further discloses wherein each of a side surface (left and right side as shown in Fig 5) of the semiconductor chip (50) and the side surface (left and right side as shown in Fig 5) of the wiring structure (60) is spaced apart from the support member (118/120) and is at least partially surrounded (Fig 4A-4C shows support member 118/120 surrounding 50 and therefore 60) by the support member (118/120).
With respect to Claim 4 Lo ‘736 discloses all limitations of the semiconductor package of claim 1, but in the instant embodiment of Lo ‘736 (Fig 1-11 and 23-29 of Lo ‘736), Lo ‘736 does not disclose wherein a thickness of the mold layer formed on the second surface of the support member is thicker than a thickness of the mold layer formed on the first surface of the semiconductor chip.
Nonetheless in a related endeavor (additional embodiment taught by Lo ‘736 as shown in Fig 32 of Lo ‘736 and Par [0116]), Lo ‘736 teaches a semiconductor package (Fig 13 and Fig 32 of Lo ‘736, Para [0058] and [0116])
wherein a thickness of the mold layer (mold layer comprised of 116, 134, 220 and 218, Fig 29 of Lo ‘736, Para [0037, 0042, 0079, 0080], hereinafter ML) formed on the second surface (top of 118’/120, Fig 13 of Lo ‘736, Para [0058]) of the support member (118’/120) is thicker than a thickness (thickness of mold layer (ML) above 50, Fig 32 of Lo ‘736) of the mold layer (ML) formed on the first surface (top) of the semiconductor chip (50). (Fig 13 of Lo ‘736 and Para [0058] disclose 118’/120 has a height less than a height of die 50, therefore the thickness of ML above 118’/120 is greater than thickness of ML above 50).
Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date, absent unexpected results, to use the greater thicknesses of the mold layer over the support structure than the die taught by the further embodiment of Lo ‘736 with the semiconductor package of the prior referenced embodiment of Lo ‘736. Using the embodiment where the molding thickness is higher on the support structure than over the die is motivating because it offers additional potential structures for this semiconductor package which would enable it to be sold into additional applications.
With respect to Claim 7 Lo ‘736 as modified by Chen ‘233 discloses all limitations of the semiconductor package of claim 1, and Lo ‘736 further discloses wherein the support member (118/120) includes a cavity (122, Fig 4B of Lo ‘736, Para 0040]), wherein the wiring structure (60) is disposed in the cavity (122, Fig 4A-4C shows support member 118/120 surrounding 50 and therefore 60), and
wherein the mold layer (ML) fills the cavity (122, Fig 7 of Lo ‘736 shows 134 fills cavity, Para [0042]) .
With respect to Claim 8 Lo ‘736 as modified by Chen ‘233 discloses all limitations of the semiconductor package of claim 1, and Lo ‘736 further discloses further comprising:
a connecting pad (Pad on bottom of chip 50, as shown in annotated Fig 5 of Lo ‘736 below, Para [0025], hereinafter CP) formed on a second surface (bottom of 50, Fig 3 of Lo ‘736) of the semiconductor chip (50) which faces a second surface (top side of 110, Fig 26 of Lo ‘736, Para [0080]) of the wiring structure (WS),
wherein the connecting pad (CP) and the first connecting terminal (FCT) are electrically connected to each other (Para [0025] of Lo ‘736 discloses 66 is electrically connected to die 50 and 66 is connected to 112 through solder 68) through the wiring structure (WS).
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With respect to Claim 9 Lo ‘736 as modified by Chen ‘233 discloses all limitations of the semiconductor package of claim 1, and Lo ‘736 further discloses comprising:
a connecting pad (112 pads in layer 120 under support member, Fig 5 of Lo ‘736, Para [0033]) formed inside the support member (Para [0033] of Lo ‘736 discloses 120 extends “along sidewalls and top surfaces of the electrical connectors 112”) and connecting the support member (118/120) and the dummy connecting terminal (DCT) to each other (Para [0044] discloses the attachment of 118 to layer 120 which is connected to connecting pads 112).
With respect to Claim 21 Lo ‘736 as modified by Chen ‘233 discloses all limitations of the semiconductor package of claim 1, and Lo ‘736 further discloses wherein the organic material comprises a polymer. (Para [0045] discloses 120 as epoxy, therefore support member 118/120 comprises organic polymer material).
With respect to Claim 22 Lo ‘736 as modified by Chen ‘233 discloses all limitations of the semiconductor package of claim 9, but Lo ‘736 as modified by Chen ‘233 fails to explicitly disclose wherein the connecting pad comprises a copper foil layer.
Nevertheless, in a related endeavor (Fig 3A-3D of Maeda ‘666), Maeda ‘666 teaches wherein the connecting pad (31, Fig 3B of Maeda ‘666, Para [0099]) comprises a copper foil layer (Para [0099] of Maeda ‘666 discloses the use of a copper foil to form conductive patterns).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Maeda ‘666’s teaching where a connecting pad comprises a copper foil layer into Lo ‘736 as modified by Chen ‘233’s device. Using a copper foil laminated to polymer layer, as taught by Maeda ‘666 is a well-known method to create a conductive contact or seed layer. Therefore the ordinary artisan would have been motivated to modify Lo ‘736 as modified by Chen ‘233 in the manner set forth above, at least, using the well-known copper clad foil to create conductive pads would have a high level of success and the use of a copper clad laminate can save both costs and process steps in the formation of conductive pads.
As incorporated, the copper foil layer (31) of Maeda ‘666 would be used on the protective film (110B) of Lo ;’736 to form the connection pads (112) in the device of Lo ‘736 as modified by Chen ‘233.
With respect to Claim 25 Lo ‘736 as modified by Chen ‘233 discloses all limitations of the semiconductor package of claim 1, and Lo ‘736 further discloses wherein the first connecting terminal (left most terminal 66) comprises at least one selected from the group consisting of tin, indium, lead, zinc, nickel, gold, silver, copper, antimony and bismuth (Para 0025] of Lo ‘736 discloses 66 as copper).
Claims 3, 10-12, 14-16 and 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Lo ‘736 in view of Chen ‘233 in further view of Shih (US 9,607,967 B1, hereinafter Shih ‘967), in view of the following arguments.
With respect to Claim 3 Lo ‘736 as modified by Chen ‘233 discloses all limitations of the semiconductor package of claim 1, but Lo ‘736 as modified by Chen ‘233 fails to disclose wherein the dummy connecting terminal and the semiconductor chip are not electrically connected to each other.
Nevertheless, in a related endeavor Shih ‘967 teaches wherein the dummy connecting terminal (414c and 416c, Fig 5 of Shih ‘967, Col 5, lines 41-43) and the semiconductor chip (420, Fig 5 of Shih ‘967, Col 5, Lines 44-45) are not electrically connected to each other (Col 5, lines 41-43 discloses connectors 414/416 under stiffener structure 100a are electrically isolated).
Therefore it would have been obvious to a person having ordinary skill in the art, before the effective filing date, absent unexpected results, to use the dummy connecting terminals not electrically connected to the die taught by Shih ‘967 with the semiconductor package of Lo ‘736 as modified by Chen ‘233. Using Shih ‘967’s dummy connecting terminals with Lo ‘736 as modified by Chen ‘233’s package enables a stiffer package structure which “can alleviate or reduce package warpage” (Shih ‘967, Col 4, Lines 44-45) which would increase the reliability of the package.
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With respect to Claim 10 Lo ‘736 discloses a semiconductor package (package component 200 in Fig 1-11 and Fig 23-29 of Lo ‘736) comprising:
a wiring structure (60, Fig 1 of Lo ‘736, Para [0023 and 0024]) including at least one wiring layer (wiring structure 60 shows multiple wiring layers, Fig 1 of Lo ‘736, Para [0022], hereinafter WL):
a support member (support member comprised of 118 and 120, Fig 5 of Lo ‘736, Para [0044], hereinafter SM) connected to a dummy connecting terminal (connectors 112 under 118/120, Fig 6 of Lo ‘736, Para [0044-0045], hereinafter DCT) (“dummy connecting terminal” is an intended use statement. Regardless, the prior art Lo ‘736 meets the “dummy connecting terminal” intended use) and having a cavity (122, Fig 4B of Lo ‘736, Para 0040]), wherein the wiring structure (60) is disposed in the cavity (122, Fig 4A-4C of Lo ‘736 shows support member 118/120 surrounding 50 and therefore 60) and is spaced apart from an inner surface (left and right inner sides) of the cavity (122, Fig 5 of Lo ‘736 shows wiring structure 60 spaced away from the support structure) wherein the support member (118/120) comprises an organic material (Para [0045] discloses 120 as epoxy, therefore support member 118/120 comprises organic material);
a semiconductor chip (50, Fig 3 of Lo ‘736, Para [0036]) connected to the wiring structure (60) and disposed in the cavity (122, Fig 4A-4C of Lo ‘736 shows support member 118/120 surrounding 50 and therefore 60);
a first connecting terminal (left most terminal 66, Fig 1 of Lo ‘736, Para [0025], hereinafter FCT) and a second connecting terminal (right most terminal 66, Fig 1 of Lo ‘736, Para [0025], hereinafter SCT) formed on a first surface (pad 62, Fig 1 of Lo ‘736, Para [0025]) of the wiring structure (60);
a mold layer (mold layer comprised of 116, 134, 220 and 218, Fig 29 of Lo ‘736, Para [0037, 0042, 0079, 0080], hereinafter ML) filling the cavity (122, Fig 29 of Lo ‘736 shows cavity filled by ML).
a protective film (110B, Fig 2 of Lo ‘736, Para [0032]) disposed between the dummy connecting terminal (DCT) and at least one of the first (FCT) and second connecting (SCT) terminals (Fig 6 of Lo ‘736 discloses 110B disposed between DCT and FCT and SCT); and
an insulating layer (64, Fig 1 of Lo ‘736, Para [0024]) and disposed between the first (FCT) and second connecting terminals (SCT)(Fig 1 of Lo ‘736 discloses 64 disposed between FCT and SCT), wherein the insulating layer (64) is not in contact with the dummy connecting terminal (DCT) (Fig 6 of Lo ‘736 discloses 64 is not in contact with DCT)
But Lo ‘736 fails to explicitly disclose an insulating layer in contact with the protective film
Nevertheless, in a related endeavor (Fig 1A-2E of Chen ‘223), Chen ‘223 teaches an insulating layer (212, Fig 1C of Chen ‘223, Para [0039]) in contact with the protective film (Top Layer of DI2 as shown in Fig 2E of Chen ‘233)
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chen ‘233’s teaching of having the insulating layer in direct contact with the protective film into Lo ‘736’s device. The ordinary artisan would have been motivated to modify Lo ‘736 in the manner set forth above, at least, because the arrangement of the chip insulating layer in direct contact with the protective film results in a lower profile package which saves valuable vertical direction real estate.
As incorporated, the configuration of the insulating layer (210) of Chen ‘233 in direct contact with the protection film (Top Layer DI2) of Chen ‘233 in the device of Lo ‘736 (the insulating layer (64) would be in direct contact with the protection film (110B)).
Lo ‘736 as modified by Chen ‘233 fails to discloses wherein the dummy connecting terminal (DCT) and the semiconductor chip (50) are not electrically connected to each other.
Nevertheless, in a related endeavor Shih ‘967 teaches wherein the dummy connecting terminal (414c and 416C, Fig 5 of Shih ‘967, Col 5, lines 41-43) and the wiring structure (60 of Lo ‘736) are not electrically connected to each other (Col 5, lines 41-43 discloses connectors 414/416 under stiffener structure 100a are electrically isolated).
Therefore it would have been obvious to a person having ordinary skill in the art, before the effective filing date, absent unexpected results, to use the dummy connecting terminals not electrically connected to the die taught by Shih ‘967 with the semiconductor package of Lo ‘736. Using Shih ‘967’s dummy connecting terminals with Lo ‘736’s package is motivating as the dummy connecting terminals connect to a non-functioning part of the package. Isolating the terminals from the functional part of the package would assure that the terminals do not cause electrical interference or signal loss.
As incorporated, the teaching of the dummy connecting terminals not electrically connected to each other as taught by Shih ‘967 would be used in the dummy connecting terminals (DCT) of Lo ‘736 as modified by Chen ‘233.
Lo ‘736 as modified by Chen ‘233 and further modified by Shih ‘967 further discloses wherein the protective film (110B) includes a first opening (one of openings for connections to 118/120 as shown in annotated Fig 5 of Lo ‘736),
the insulating layer (64 of Lo ‘736 as modified above by 210 of Chen ‘233 so that 64 is in direct contact with protection film 110B) includes a second opening (one of the openings in 64 of Lo ‘736 as modified above by 210 of Chen ‘233 so that 64 is in direct contact with protection film 110B of Lo ‘736) extending to the first opening (one of openings for connections to 118/120 as shown in annotated Fig 5 of Lo ‘736) (64 of Lo ‘736 as modified above by 210 of Chen ‘233 so that 64 is in direct contact with protection film 110B of Lo ‘736, so the second openings in that film, where the electrical contacts of the semiconductor chip pass from the chip through the protection layer 64 as modified by Chen ‘233 so it is in direct contact to 110B of Lo ‘736 (as described above), therefore as the modified protective layer 64 is in direct contact with 110B the second openings extend to the first openings),
the first connecting terminal (FCT) is arranged within the second opening (one of the openings in 64 of Lo ‘736 as modified above by 210 of Chen ‘233 so that 64 is in direct contact with protection film 110B of Lo ‘736)(Fig 5 of Lo ‘736 discloses connecting terminals arranged with second openings in 64), and
the dummy connecting terminal (DCT) is arranged within the first opening (one of openings for connections to 118/120 as shown in annotated Fig 5 of Lo ‘736)(Fig 5 of Lo ‘736 discloses dummy terminals arranged with first opening).
With respect to Claim 11 Lo ‘736 as modified by Chen ‘233 and further modified by Shih ‘967 discloses all limitations of the semiconductor package of claim 10, and Lo ‘736 further discloses wherein the mold layer (mold layer comprised of 116, 134, 220 and 218, Fig 29 of Lo ‘736, Para [0037, 0042, 0079, 0080], hereinafter ML) covers a side surface (left or right of 114, Fig 7 of Lo ‘736, Para [0048]) of the wiring structure (60), an upper surface (top of 50, Fig 27 of Lo ‘736, Para [0048]), and a side surface (left or right of 50) of the semiconductor chip (50), and an upper surface (top of 118/120, Fig 29 of Lo ‘736, Para [0079]) and a side surface (left or right of 118/120, Fig 29 of Lo ‘736, Para [0080]) of the support member (118/120).
With respect to Claim 12 Lo ‘736 as modified by Chen ‘233 and further modified by Shih ‘967 discloses all limitations of the semiconductor package of claim 10, and Shih ‘967 further discloses wherein the dummy connecting terminal (414c and 416C, Fig 5 of Shih ‘967, Col 5, lines 41-43) and the wiring structure (wiring structure 60 of Lo ‘736) are not electrically connected to each other (Col 5, lines 41-43 discloses connectors 414/416 under stiffener structure 100a are electrically isolated).
With respect to Claim 14 Lo ‘736 as modified by Chen ‘233 and further modified by Shih ‘967 discloses all limitations of the semiconductor package of claim 10, but in the instant embodiment of Lo ‘736 (Fig 1-11 and 23-29 of Lo ‘736), Lo ‘736 as modified by Chen ‘233 and further modified by Shih ‘967 does not disclose wherein a thickness of a mold layer formed on an upper surface of the support member is thicker than a thickness of the mold layer formed on an upper surface of the semiconductor chip.
Nonetheless in a related endeavor (additional embodiment taught by Lo ‘736 as shown in Fig 32 of Lo ‘736 and Par [0116]), Lo ‘736 teaches a semiconductor package (Fig 13 and 32 of Lo ‘736, Para [0058] and [0116])
wherein a thickness of a mold layer (mold layer comprised of 116, 134, 220 and 218, Fig 29 of Lo ‘736, Para [0037, 0042, 0079, 0080], hereinafter ML) formed on an upper surface (top of 118’/120, Fig 13 of Lo ‘736, Para [0058]) of the support member (118’/120) is thicker than a thickness (thickness of mold layer (ML) above 50, Fig 32) of the mold layer (ML) formed on an upper surface (top) of the semiconductor chip (50). (Fig 13 of Lo ‘736 and Para [0058] disclose 118’/120 has a height less than a height of die 50, therefore the thickness of ML above 118’/120 is greater than thickness of ML above 50).
Therefore it would have been obvious to a person having ordinary skill in the art, before the effective filing date, absent unexpected results, to use the greater thicknesses of the mold layer over the support structure than the die taught by the further embodiment of Lo ‘736 with the semiconductor package of the prior referenced embodiment of Lo ‘736 as modified by Chen ‘233 and further modified by Shih ‘967. Using the embodiment where the molding thickness is higher on the support structure than over the die is motivating because it offers additional potential structures for this semiconductor package which would enable it to be sold into additional applications.
With respect to Claim 15 Lo ‘736 as modified by Chen ‘233 and further modified by Shih ‘967 discloses all limitations of the semiconductor package of claim 10, and Lo ‘736 further discloses comprising:
a first connecting pad (58, Fig 1 of Lo ‘736, Para [0022]) formed on a first side (bottom, Fig 1 of Lo ‘736) of the semiconductor chip (50) which faces the wiring structure (60, Fig 1 of Lo ‘736 shows 58 facing 60, Para [0022]); and
Lo ‘736 as modified by Chen ‘233 and further modified by Shih ‘967 further teaches a second connecting pad (Pads 414c, Fig 5 of Shih ‘967, Col 5, Lines 33-43) connecting the support member (100a, Fig 5 of Shih ‘967, Col 4, Lines 43-45)) and the dummy connecting terminal (DCT of Lo ‘736 as modified by Shih ‘967, described above) to each other (Fig 5 of Shih ‘967 shows connection of 414c and 416c),
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Shih ‘967’s further teaching of a second connecting pad connecting the support member and the dummy connecting terminal to each other into Lo ‘736 as modified by Chen ‘233 and further modified by Shih ‘967’s device. The ordinary artisan would have been motivated to modify Lo ‘736 as modified by Chen ‘233 and further modified by Shih ‘967 in the manner set forth above, at least because, Shih ‘967 provides a well-known conductive connection process that would provide a high level of success and would provide a reliable means of connecting device structures.
As incorporated, the teaching of Shih ‘967 providing a second connection pad (Pads 414c) would be used in the device of Lo ‘736 as modified by Chen ‘233 and further modified by Shih ‘967 to connect the support member (118/120) and the dummy connecting terminal (DCT) of Lo ‘736 as modified by Chen ‘233 and further modified by Shih ‘967.
Combining Shih ‘967 with Lo ‘736, Lo ‘736 further teaches wherein the first connecting pad (58) and the first connecting terminal (FCT) are electrically connected to each other through the wiring structure (Para [0022-0025] disclose that 58 is electrically connected to 66)
With respect to Claim 16 Lo ‘736 as modified by Chen ‘233 and further modified by Shih ‘967 discloses all limitations of the semiconductor package of claim 15, and Shih ‘967 further discloses wherein the dummy connecting terminal (414c and 416C, Fig 5 of Shih ‘967, Col 5, lines 41-43) is not electrically connected to the first connecting pad (Col 5, lines 41-43 discloses connectors 414/416 under stiffener structure 100a are electrically isolated, therefore they are not electrically connected to the die or it’s wiring pads).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Shih ‘967’s further teaching of wherein the dummy connecting terminal is not electrically connected to the first connecting pad into Lo ‘736 as modified by Chen ‘233 and further modified by Shih ‘967’s device. The ordinary artisan would have been motivated to modify Lo ‘736 as modified by Chen ‘233 and further modified by Shih ‘967 in the manner set forth above, at least because, providing a mechanical connection between the dummy connecting terminal and the first connecting pad would provide a strong and reliable connection that could easily be processed (copper connection) in the fabrication process to construct the device of Lo ‘736 as modified by Chen ‘233 and further modified by Shih ‘967.
As incorporated, the teaching of Shih ‘967 wherein the dummy connecting terminal is not electrically connected to the first connecting pad would be used between the dummy connecting terminal (DCT) and first connecting pad (58) in the device of Lo ‘736 as modified by Chen ‘233 and further modified by Shih ‘967.
With respect to Claim 23 Lo ‘736 as modified by Chen ‘233 and further modified by Shih ‘967 discloses all limitations of the semiconductor package of claim 10, and Lo ‘736 further discloses wherein the organic material comprises a polymer. (Para [0045] discloses 120 as epoxy, therefore support member 118/120 comprises organic polymer material).
With respect to Claim 24 Lo ‘736 as modified by Chen ‘233 and further modified by Shih ‘967 discloses all limitations of the semiconductor package of claim 15, but Lo ‘736 as modified by Chen ‘233 and further modified by Shih ‘967 discloses all limitations of the fails to explicitly disclose wherein the second connecting pad comprises a copper foil layer.
Nevertheless, in a related endeavor (Fig 3A-3D of Maeda ‘666), Maeda ‘666 teaches wherein the second connecting pad (31, Fig 3B of Maeda ‘666, Para [0099]) comprises a copper foil layer (Para [0099] of Maeda ‘666 discloses the use of a copper foil to form conductive patterns).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Maeda ‘666’s teaching where a connecting pad comprises a copper foil layer into Lo ‘736 as modified by Chen ‘233’s device. Using a copper foil laminated to polymer layer, as taught by Maeda ‘666 is a well-known method to create a conductive contact or seed layer. Therefore the ordinary artisan would have been motivated to modify Lo ‘736 as modified by Chen ‘233 in the manner set forth above, at least, using the well-known copper clad foil to create conductive pads would have a high level of success and the use of a copper clad laminate can save both costs and process steps in the formation of conductive pads.
As incorporated, the copper foil layer (31) of Maeda ‘666 would be used on the protective film (110B) of Lo ;’736 to form the second connecting pads (Pads 414c as taught by Shih ‘967 and incorporated in Lo ‘736 as modified by Chen ‘233 and further modified by Shih ‘967 as described above) in the device of Lo ‘736 as modified by Chen ‘233 and further modified by Shih ‘967.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Lo ‘736 in view of Chen ‘233 and in further view of Gan et al., (US 2012/0168943 A1, hereinafter Gan ‘943), in view of the following arguments.
With respect to Claim 5 Lo ‘736 as modified by Chen ‘233 discloses all limitations of the semiconductor package of claim 1, but Lo ‘736 as modified by Chen ‘233 fails to explicitly teach wherein the at least one wiring layer includes a wiring pad including a first portion and a second portion, wherein the first portion overlaps the semiconductor chip, and the second portion does not overlap the semiconductor chip.
Nonetheless in an analogous endeavor Gan ‘943 teaches wherein the at least one wiring layer (40, Fig 7 of Gan ‘943, Para [0048]) includes a wiring pad (pad to which contact 13 is connected, Fig 7 of Gan ‘943, Para [0048]) including a first portion (portion of 40 under chip 11a, Fig 7 of Gan ‘943, hereinafter P1) and a second portion (portion of 40 not under chip 11a, Fig 7 of Gan ‘943, hereinafter P2), wherein the first portion (P1) overlaps the semiconductor chip (11a), and the second portion (P2) does not overlap the semiconductor chip (Fig 7 of Gan ‘943 discloses P1 is under 11a and P2 is outside 11a).
Therefore it would have been obvious to a person having ordinary skill in the art, before the effective filing date, absent unexpected results, to use the wiring pad structure and it’s overlap of the semiconductor chip taught by Gan ‘943 with the semiconductor package of Lo ‘736 as modified by Chen ‘233. Using Gan ‘943’s wiring structure arrangement with Lo ‘736 as modified by Chen ‘233’s package enables to user to take advantage of the lower costs of fan out processing.
With respect to Claim 6 Lo ‘736 as modified by Chen ‘233 and further modified by Gan ‘943 discloses all limitations of the semiconductor package of claim 5, and Lo ‘736 further discloses wherein the mold laver (ML) covers a second surface (top side of 110, Fig 26 of Lo ‘736, Para [0080]), opposite to the first surface (bottom of 114), of the wiring structure (WS) exposed by the semiconductor chip (50). (Fig 7 of Lo ‘736 shows 134 over top of 110, Para [0048])
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898