The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 6, 9-13 and 21-28 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There is no support for the elected embodiment of figure 4A for the claimed limitation of “the bounding box area occupying all of the area within the bounding box”, as recited in claims 1 and 14.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 6, 9-14, 19 and 21-28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claimed limitation of “the bounding box area occupying all of the area within the bounding box”, as recited in claims 1 and 14 is unclear as to how the bounding box area can occupy all of the area within the bounding box since the dies occupy part of the area within the bounding box.
The claimed limitation of “the interconnect layer also having an edge area outside and surrounding the bounding box area on the interconnect layer, the edge area disposed between the bounding box and the edges”, as recited in claims 1 and 14 is unclear as to how the interconnect layer, which is disposed below a plurality of dies, can surround the bounding box area because the bounding box is outside and surrounding the bounding box area on the interconnect layer.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, 9-14, 19 and 21-29 are rejected under 35 U.S.C. 103 as being unpatentable over Hu (9,543,249) view of Thottethodi et al. (2014/0177626).
Regarding claims 1 and 14, Hu teaches in figures 5B, 10B and related text an integrated chip (the entire structure), comprising a first chip and a second chip, wherein the first chip and the second chip are packaged together and the first chip comprises:
an interconnect layer RDL2 having edges wherein the interconnect layer is a layer disposed below a plurality of dies integrated in a single package; and
a plurality of dies 541, 542 disposed on the interconnect layer, and
the plurality of dies comprising a first die Chip8, a second die Chip4 and a third die Chip0;
a bounding box forming a peripheral boundary encompassing the first die, the second die, and the third die, the bounding box enclosing a bounding box area on the interconnect layer, the bounding box area on interconnect layer RDL2 having each of the first die, the second die and the third die disposed thereon;
the bounding box area occupying all of the area within the bounding box, and
the interconnect layer also having an edge area outside and surrounding the bounding box area on the interconnect layer, the edge area disposed between the bounding box and the edges;
wherein the first die Chip8 and the third die Chip0 are interconnected to one another through direct routing in the bounding box area on the interconnect layer without crossing another die, and
wherein the second die Chip4 and the third die Chip0 are interconnected to one another through direct routing within the bounding box area on the interconnect layer without crossing another die.
Hu does not teach that the first die and the second die are interconnected to one another through routing within the edge area.
Thottethodi et al. teach in figure 2 and related text a first die 212 and a second die 205 are interconnected to one another through routing 222 within the edge area.
Hu and Thottethodi et al. are analogous art because they are directed to circuits layout and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hu because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to interconnect the first die and the second die to one another through routing within the edge area, as taught by Thottethodi, in the device of Hu, in order to reduce the real state area of the device by using conventional Chip-On-Chip structure.
Regarding claims 6 and 19, Hu teaches that the bounding box is a die top bounding box comprising a boundary formed by peripheral dies in the plurality of dies.
Regarding claim 9, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to determine the bounding box based on the peripheries of the plurality of dies defined by the sizes, shapes, and arrangements of the plurality of dies in the device of Hu, in order to optimize the size of the device according to requirements of the application in hand.
Regarding claims 10-13, Hu teaches substantially the entire claimed structure, as applied to claim 1 including an interconnect layer is a redistribution layer, an interposer, a substrate, or wherein the plurality of dies are interconnected through routing by using the uBumps, but does not explicitly state that the packaging manner of the chip is fan-out packaging, CoWoS packaging, multi-chip module packaging, or wherein each of the plurality of dies comprises uBumps.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use the packaging manner of the chip to be fan-out packaging, CoWoS packaging, multi-chip module packaging, or wherein each of the plurality of dies comprises uBumps, in the device of Hu, in order to reduce the cost of making the device by conventional packaging.
Regarding claims 21 and 24, Hu teaches in figure 10B and related text that the first die, the second die and the third die are each rectangular in shape, and the bounding box is rectangular and has boundaries that are parallel to respective outer edges of the first die, the second die and the third die.
Regarding claim 22, Hu teaches in figure 10B and related text that in a first dimension the peripheral dies of the plurality of dies comprise the first die Chip8 and the second die Chip4, and in a second dimension orthogonal to the first dimension the peripheral dies of the plurality of dies comprises the third die Chip0 which extends further in the second dimension than either the first die or the second die.
Regarding claim 23, Hu teaches in figure 10B and related text that the interconnect layer is rectangular and has a first set of parallel edges extending in the first dimension and a second set of parallel edges extending in the second dimension.
Regarding claim 25, Hu teaches in figure 10B and related text that the bounding box is sized and dimensioned (arbitrarily chosen) to define a bounding perimeter encompassing the entirety of the first die, the entirety of the second die and the entirety of the third die, a first portion of the bounding perimeter being coincident (arbitrarily chosen) with an outer edge of the first die, a second portion of the bounding perimeter being coincident with an outer edge of the second die, a third portion of the bounding perimeter being coincident with an outer edge of the third die.
Regarding claims 26-28, Hu teaches in figure 10B and related text that the bounding box comprises a geometric shape that encloses or surrounds the combination of areas the plurality of dies occupy, and wherein the geometric shape is a parallelepiped, and wherein the parallelepiped comprises a rectangle.
Response to Arguments
1. Applicants argue that there is support for the elected embodiment of figure 4A for the claimed limitation of “the bounding box area occupying all of the area within the bounding box”, as recited in claims 1 and 14, because “the bounding box area defines an area on the interconnect layer, and the dies are disposed on the interconnect layer within that area. By analogy, buildings such as USPTO headquarters constructed on land owned by the US government within Alexandria Virginia are clearly within the area of Alexandria Virginia and the US government's ownership. It would be absurd to argue the "footprints" of the USPTO's buildings ought to be "carved out" from the Alexandria VA area -- yet that appears to be analogous to what the Examiner is arguing in this case for purposes of making a rejection under 35 USC 112 (while at the same time arguing the exact opposite to reject under 35 USC 103)”.
1. In the analogy provided by applicants, claims require that the grass and roads in the land owned by the US government within Alexandria Virginia (i.e. bounding box area) must occupy ALL of the area within the bounding box. However, the grass and roads in the land owned by the US government within Alexandria Virginia does not occupy ALL of the area within in the land owned by the US government within Alexandria Virginia, because the buildings are also located in the in the land owned by the US government within Alexandria Virginia.
2. Applicants argue that “In Thottethodi et al. (2014/0177626), the through-silicon vias the FA is calling "interconnect layer" (222) is not "a layer disposed below a plurality of dies" (212 is a single die), nor is what FA calls "the edge area" in Thottethodi et al. (2014/0177626) "an area outside a bounding box area on an interconnect layer". Recall further applicant's express definition of ''bounding box area"~ as ''an area enclosed by a bounding box on an interconnect layer'' (emphasis added) which has now been expressly incorporated into the independent claims. Thottethodi et al. (2014/0177626)'s suspended-above vertical structure meets none of these definitions”.
2. Thottethodi et al. was not cited to teach an artisan that the interconnect layer is a layer disposed below a plurality of dies integrated in a single package. Hu teaches the above limitations. Thottethodi et al. was cited to teach that a first die 212 and a second die 205 are interconnected to one another through routing 222 within the edge area.
3. Applicants argue that “The FA's proposed combination would destroy this lateral design, thereby complicating what Hu wishes to simplify”.
3. As, asserted in the advisory action, Applicants did not provide any evidence to support the hypothesis that modifying Hu in view of Thottethodi et al. would render[s] the prior art reference inoperable for its intended purpose.
4. Applicants argue that “The Examiner's above statement misstates applicant's argument, which is that Hu emphasizes a lateral design, and the Examiner's proposed modification would destroy this lateral design. It would be like a property owner requesting single story connected buildings and the building contractor constructing a skyscraper instead”.
4. In response to applicants’ argument, if a building contractor constructs a skyscraper instead of a single story connected buildings for the same price, the property owner would be very happy and approve said modification.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 9 AM to 6PM (Eastern Standard Time) Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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O.N. /ORI NADAV/
3/25/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800
Prosecution Insights