DETAILED ACTION
The Office Action is sent in response to Applicant’s Communication received on 11/04/2025 for application number 17/720,935. The Office hereby acknowledges receipt of the following and placed of record in file: Applicant’s Remarks, and amendments to claims, and specification.
Examiner Notes the following: claims 10, 11, and 17 have been amended, claim 20 has been cancelled and claim 21 has been added.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 17-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Under the Alice Framework Step 1, claims recite a method and, therefore, is a process.
Under the Alice Framework Step 2A prong 1, claim 17 recites:
A computing method, comprising:
performing data computation with a memory to obtain an adder input;
obtaining an input parameter from the adder input;
determining whether the input parameter is present in a parameter table;
providing, through a pre-computation circuit, a pre-computation result corresponding to the input parameter as an adder output, and disabling an adder tree, when determining that the input parameter is present in the parameter table;
and performing an addition operation on the adder input with the adder tree to obtain the adder output when determining that the input parameter is not present in the parameter table.
The above underlined limitations are related to multiplying, adding, and accumulating data which amounts to mathematical calculations and relationships that fall under “mathematical concepts” groupings of abstract ideas (see specification paragraphs 17-35). Accordingly, the claim recite an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 17 recites the following additional elements: “a memory”, “a parameter table”, and “an adder tree”, “a pre-computation circuit”, and “disabling an adder tree”. However, the additional elements of “a memory”, “a parameter table”, “an adder tree”, and “a pre-computation circuit” are recited at a high-level of generality (i.e., as a generic computer component for multiplication; i.e., as a generic computer component for storing data; and as a generic computer component for addition) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional element of “disabling the adder tree” is merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, claim 17 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a memory”, “a parameter table”, “an adder tree”, and “a pre-computation circuit” are recited at a high-level of generality (i.e., as a generic computer component for multiplication; i.e., as a generic computer component for storing data; and as a generic computer component for addition) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional element of “disabling the adder tree” is merely adding insignificant extra-solution activities. Furthermore, the insignificant extra-solution activities of “disabling” is well-understood, routine and conventional. See Patterson et al., Computer Organization and Design: The Hardware/Software Interface, Fifth Edition, (2013), hereinafter Patterson 2013, Chapter 1 which discloses turning off parts of the chips that are not used [p. 42]. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under the Alice Framework Step 2A prong 1, Claims 18-19 recite further steps and details to multiplying, adding, and accumulating data which amounts to mathematical calculations and relationships that falls within the “mathematical Concepts” and/or “mental Processes” grouping of abstract ideas. Claim 18, is directed to the memory composing of cells that compute multiplication. Claim 19, is directed to comparing data to the parameter table and determining if it exists in the table. In particular claim 19 do not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recite an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 18 recites the following additional element: “a plurality of memory cells”. However, the additional element of “a plurality of memory cells” is recited at a high-level of generality (i.e., as a generic computer component for multiplication) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, claims 18 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “a plurality of memory cells” is recited at a high-level of generality (i.e., as a generic computer component for multiplication) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 4, 7, 10, 11, 13, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chih et al. (NPL: "An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications" From IDS filed 04/14/2022), hereinafter Chih, and in view of Imani et al. (NPL: "Program Acceleration Using Nearest Distance Associative Search"), hereinafter Imani, and further in view of Rengarajan et al. (US 10,432,436 B1), hereinafter Rengarajan.
Regarding claim 1, Chih discloses: A compute-in memory (CIM) device, comprising:
a memory comprising a plurality of memory cells, wherein each of the memory cells is configured to multiply a respective bit of input data by a respective bit of a weight to obtain a respective bit of an adder input [Figure 16.4.1 and 16.4.2 shows an CIM array prior to an adder tree];
an addition circuit configured to receive the adder input to provide an adder output, and comprising an adder tree configured to provide the adder output [Figure 16.4.1 and 16.4.2 discloses an adder tree circuit]; and
an accumulator configured to perform an accumulative adding calculation on the adder output to provide accumulated output data [Figure 16.4.1 and 16.4.2 discloses an accumulator after the adder tree, and the use of a switch for the input for the accumulator].
However, Chih does not explicitly disclose:
an addition circuit configured to receive the adder input to provide an adder output, and comprising: a pre-computation circuit, comprising: a parameter extractor configured to extract an input parameter from the adder input; and a parameter identification circuit configured to provide a pre- computation result corresponding to the input parameter as the adder output when determining that the input parameter is present in a parameter table, and provide a control signal when determining that the input parameter is not present in the parameter table; and an adder tree configured to provide the adder output according to the adder input in response to the control signal;
In the analogous art of Computational reuse implementations, Imani teaches:
an addition circuit [Figure 1, FPU] configured to receive the adder input to provide an adder output, and comprising a pre-computation circuit [Resistive Associative Unit (RAU)], comprising:
a parameter identification circuit [RAU] configured to provide a pre-computation result corresponding to the input parameter as the adder output when determining that the input parameter is present in a parameter table [ternary content addressable memory (TCAM)], and provide a control signal [FPU Activation] when determining that the input parameter is not present in the parameter table [“Associative memory prestores a set of frequent patterns“ I. Introduction, teaches the use of prestored patterns; "RAU consists of a ternary content addressable memory (TCAM) to store high frequency patterns and memory for their corresponding outputs" III. GPGPU Acceleration B. Resistive Associative Unit and its Integration; "When the GPU receives inputs the memory banks are checked for a matching pattern, and if a set matching the inputs is located, the associated output is returned. The Floating Point Unit (FPU) does not need to run when a hit occurs, saving energy" III: A. Data Locality and Approximation]; and
an adder [FPU: ADD] configured to provide the adder output according to the adder input in response to the control signal [FPU Activation; Figure 1, MUX];
It would have been obvious to one of ordinary skill in the art, that the adder [FPU: ADD] taught by Imani and the adder tree [Figure 16.4.1 and 16.4.2] disclosed by Chih both results in addition. As such, It would have been obvious to one of ordinary skill in the art, having the teachings of Chih and Imani before him before the effective filing date of the claimed invention to substitute the adder tree disclosed by Chih into the adder taught by Imani to include the Resistive Associative Unit architecture, wherein the combination of Chih and Imani is substituted into the addition circuit disclosed by Chih [Figure 16.4.1, adder tree circuit], in order to implement computational reuse that reduces redundant computations, increase energy savings and speedup [Imani: I. Introduction, II. Related Work, and VI. Conclusion]. The combination of Chih and Imani discloses an addition circuit configured to receive the adder input to provide an adder output, and comprising: a pre-computation circuit, comprising a parameter identification circuit configured to provide a pre- computation result corresponding to the input parameter as the adder output when determining that the input parameter is present in a parameter table, and provide a control signal when determining that the input parameter is not present in the parameter table; and an adder tree configured to provide the adder output according to the adder input in response to the control signal;
However, Chih and Imani does not explicitly disclose a parameter extractor configured to extract an input parameter from the adder input;
In the analogous art of arithmetic architecture for reduced power consumption, Rengarajan teaches a parameter extractor configured to extract an input parameter from the adder input [Figure 3, Address generator; "a group of bits made up of the LSBs of the predetermined number of digital words are combined by the address generator to form one DA LUT address for accessing a sum of partial products value for that LSB position" Col. 2, lines 51-55];
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, and Rengarajan before him before the effective filing date of the claimed invention to modify the RAU disclosed by the combination of Chih and Imani, to include the address generator taught by Rengarajan, in order to implement an addressable Lookup table for reduction in power consumption and memory size [Rengarajan: Col.7 ll. 49-64, and Col.8 ll. 6-19].
Regarding claim 2, Chih, Imani, and Rengarajan disclose the invention substantially as claimed. See the discussion of claim 1 above. Chih and Rengarajan does not disclose the additional limitations of claim 2.
In the analogous art of Computational reuse implementations, Imani teaches: wherein the parameter identification circuit comprises:
a parameter comparing circuit [Fig. 5, Peripheral circuitry] configured to compare the input parameter with a plurality of pre-stored parameters in the parameter table ["input data is distributed among all rows... TCAM cell with a similar stored value to the input discharges the ML" IV. RAU Hardware Design: B. Nearest Distance CAM; "An NHD detector is an resistive circuitry which samples output sense amplifier voltages in all rows... an NHD detects the first matched row(s)," IV: C. Peripheral Circuitry]; and
a storage device [resistive memory] configured to store a plurality of pre-stored results, wherein each of the pre-stored results corresponds to a respective pre-stored parameter, wherein when the input parameter is equal to one of the pre-stored parameters in the parameter table [TCAM], the parameter identification circuit is configured to determine that the input parameter is present in the parameter table, and provide the pre-stored result corresponding to the one of the pre-stored parameters as the pre-computation result ["When an input operand hits on TCAM, the corresponding row of resistive memory is activated to read the approximate result of computation." III: B.].
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, and Rengarajan before him before the effective filing date of the claimed invention to modify the adder tree disclosed by Chih to include the Resistive Associative Unit architecture, in order to implement computational reuse that reduces redundant computations, increase energy savings and speedup [Imani: I. Introduction, II. Related Work, and VI. Conclusion]
Regarding claim 4, Chih, Imani, and Rengarajan disclose the invention substantially as claimed. See the discussion of claim 1 above. Chih further discloses wherein the adder tree comprises a plurality of adders interconnected in a tree-like configuration [Figure 16.4.2 discloses an adder tree in a tree-like configuration].
Regarding claim 7, Chih, Imani, and Rengarajan disclose the invention substantially as claimed. See the discussion of claim 1 above. Chih discloses a adder tree to accumulator architecture [Figure 16.4.1].
However, Chih does not explicitly disclose a switching unit coupled between the adder tree and the accumulator, wherein when the input parameter is not present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn on the switching unit, wherein when the input parameter is present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn off the switching unit.
In the analogous art of Computational reuse implementations, Imani teaches:
a switching unit coupled between the adder and the output, wherein when the input parameter is not present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn on the switching unit, wherein when the input parameter is present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn off the switching unit [Figure 1, teaches the use of an FPU Activation and a mux (switch) for outputting between the FPU and RAU; "The Floating Point Unit (FPU) does not need to run when a hit occurs” III: A., teaches turning off the FPU when using the RAU for the output].
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, and Rengarajan before him before the effective filing date of the claimed invention to modify the adder tree disclosed by Chih to include the Mux switch for the outputs of the adder and RAU taught by Imani, in order to implement computational reuse that reduces redundant computations, increase energy savings and speedup [Imani: I. Introduction, II. Related Work, and VI. Conclusion]. The combination of Chih and Imani discloses a switching unit coupled between the adder tree and the accumulator, wherein when the input parameter is not present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn on the switching unit, wherein when the input parameter is present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn off the switching unit
Regarding claim 10, Chih disclose wherein bit number of the weight is different from bit number of the input data ["It can support input activations with programmable bit-widths (1-8 per macro), signed or unsigned, and weights with 4 different bit widths (4, 8, 12, or 16)." p. 252]
The remaining limitations of claim 10 corresponds to claim 1, wherein the combination of Chih, Imani and Rengarajan disclose the remaining limitations of claim 10 with respect to the reasons given in claim 1 and is rejected accordingly.
Claim 11 corresponds to claim 2 (and claim 1 for the parameter extractor). As such, claim 11 is rejected for the reasons given above for claim 2 (and claim 1).
Claim 13 corresponds to claim 4. As such, claim 13 is rejected for the reasons given above for claim 4.
Claim 16 corresponds to claim 7. As such, claim 16 is rejected for the reasons given above for claim 7.
Regarding claim 17, Chih discloses:
Performing data computation with a memory to obtain an adder input [Figure 16.4.1 and 16.4.2 shows an CIM array prior to an adder tree];
Performing an addition operation on the adder input with the adder tree to obtain the adder output [Figure 16.4.1 and 16.4.2 discloses an adder tree circuit];
However, Chih does not explicitly disclose:
Obtaining an input parameter from the adder input;
Determining whether the input parameter is present in a parameter table;
Providing, through a pre-computation circuit, a pre-computation result corresponding to the input parameter as an adder output, and disabling an adder tree when determining that the input parameter is present in the table; and
Performing an addition operation on the adder input with the adder tree to obtain the adder output in response to a control signal provided by the pre-computation circuit when determining that the input parameter is not present in the parameter table.
In the analogous art of Computational reuse implementations, Imani teaches:
Determining whether the input parameter is present in a parameter table [“When an input operand hits on TCAM” Sec. III.B];
Providing, through a pre-computation circuit [Resistive Associative Unit (RAU)], a pre-computation result [ternary content addressable memory (TCAM)] corresponding to the input parameter as an adder output [“Associative memory prestores a set of frequent patterns“ I. Introduction, teaches the use of prestored patterns; "RAU consists of a ternary content addressable memory (TCAM) to store high frequency patterns and memory for their corresponding outputs" III. GPGPU Acceleration B. Resistive Associative Unit and its Integration; See Fig.1, MUX that outputs the pre-computation circuit as an output; "When the GPU receives inputs the memory banks are checked for a matching pattern, and if a set matching the inputs is located, the associated output is returned" III: A. Data Locality and Approximation],
and disabling an adder tree when determining that the input parameter is present in the table [Figure 1, FPU Activation; "The Floating Point Unit (FPU) does not need to run when a hit occurs” III: A., teaches turning off the FPU when using the RAU for the output] and
Performing an addition operation on the adder input with the adder tree [Figure 1, FPU] to obtain the adder output in response to a control signal [FPU Activation; Figure 1, MUX] provided by the pre-computation circuit [Resistive Associative Unit (RAU); FPU Activation], when determining that the input parameter is not present in the parameter table [Fig.1, RAU, FPU: ADD, and FPU Activation; "The Floating Point Unit (FPU) does not need to run when a hit occurs” III:A; “we assign the less frequent data to FPUs to process. In this way, we can leave the RAU block small to support high frequency patterns” Sec.III.B.2].
It would have been obvious to one of ordinary skill in the art, that the adder [FPU: ADD] taught by Imani and the adder tree [Figure 16.4.1 and 16.4.2] disclosed by Chih both results in addition. As such, It would have been obvious to one of ordinary skill in the art, having the teachings of Chih and Imani before him before the effective filing date of the claimed invention to substitute the adder tree disclosed by Chih into the adder taught by Imani to include the Resistive Associative Unit architecture, wherein the combination of Chih and Imani is substituted into the addition circuit disclosed by Chih [Figure 16.4.1, adder tree circuit], in order to implement computational reuse that reduces redundant computations, increase energy savings and speedup [Imani: I. Introduction, II. Related Work, and VI. Conclusion]. The combination of Chih and Imani discloses determining whether the input parameter is present in a parameter table; Providing, through a pre-computation circuit, a pre-computation result corresponding to the input parameter as an adder output, and disabling an adder tree when determining that the input parameter is present in the table; and Performing an addition operation on the adder input with the adder tree to obtain the adder output in response to a control signal provided by the pre-computation circuit when determining that the input parameter is not present in the parameter table.
However, Chih and Imani does not explicitly disclose obtaining an input parameter from the adder input;
In the analogous art of arithmetic architecture for reduced power consumption, Rengarajan teaches obtaining an input parameter from the adder input [Figure 3, Address generator; "a group of bits made up of the LSBs of the predetermined number of digital words are combined by the address generator to form one DA LUT address for accessing a sum of partial products value for that LSB position" Col. 2, lines 51-55];
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, and Rengarajan before him before the effective filing date of the claimed invention to modify the RAU disclosed by the combination of Chih and Imani, to include the address generator taught by Rengarajan, in order to implement an addressable Lookup table for reduction in power consumption and memory size [Rengarajan: Col.7 ll. 49-64, and Col.8 ll. 6-19].
Claim 18 corresponds to claim 1. A mere change in statutory class is obvious. As such, claim 18 is rejected for the reasons given above for claim 1.
Claim 19 corresponds to claim 2. A mere change in statutory class is obvious. As such, claim 19 is rejected for the reasons given above for claim 2.
Claims 3 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Chih, Imani, and Rengarajan, and in view of Simkins et al. (US 9,081,634 B1), hereinafter Simkins.
Regarding claim 3, Chih, Imani, and Rengarajan disclose the invention substantially as claimed. See the discussion of claim 1 above.
Chih discloses using memory output as input into the adder tree [Figure 16.4.1].
However, Chih and Rengarajan does not explicitly disclose the additional limitations of claim 3.
In the analogous art of Computational reuse implementations, Imani teaches
the control signal for disabling the adder, wherein when the input parameter is not present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn on the adder, wherein when the input parameter is present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn off the adder [Figure 1, teaches the use of an FPU Activation; "The Floating Point Unit (FPU) does not need to run when a hit occurs' III: A., teaches turning off the FPU when using the RAU for the output].
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, and Rengarajan before him before the effective filing date of the claimed invention to modify the adder tree disclosed by Chih to include the activation signal taught by Imani, in order to implement power gating that reduces redundant computations, increase energy savings and speedup [Imani: I. Introduction, II. Related Work, and VI. Conclusion].
However, Chih, Imani, and Rengarajan does not explicitly disclose a switching unit coupled between the memory and the adder tree, wherein when the input parameter is not present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn on the switching unit, wherein when the input parameter is present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn off the switching unit.
In the analogous art of digital signal processing and power gating, Simkins teaches a switching unit between the input and an adder [Fig. 3, 322 and 321; “If inmode 202-1 is at a logic 1 state, the A path input 361 to adder/subtractor 331 is forced to 0, and if inmode 202-2 is at a logic 0 state, the D path input 362 to adder/subtractor 331 is forced to 0.” Col. 11, ll. 11-14]
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, Rengarajan, and Simkins before him before the effective filing date of the claimed invention to modify the inputs of the adder tree as disclosed by the combination of Chih and Imani, to include the power gating architecture as taught by Simkins, in order to implement a switching unit for power gating using the control signal from Imani to enable power gating to conserve power [Simkins: Col. 11, ll. 4-28]. The combination of Chih, Imani, and Simkins discloses the limitations of claim 3.
Claim 12 corresponds to claim 3. As such, claim 12 is rejected for the reasons given above for claim 3.
Claims 5, 6, 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chih, Imani, and Rengarajan, and in view of Bose et al. (US 2007/0043960 A1), hereinafter Bose.
Regarding claim 5, Chih, Imani, and Rengarajan disclose the invention substantially as claimed. See the discussion of claim 4 above. However, Chih and Rengarajan does not explicitly disclose the additional limitations of claim 5.
In the analogous art of Computational reuse implementations, Imani teaches
the control signal for disabling the adder, wherein when the input parameter is not present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn on the adder, wherein when the input parameter is present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn off the adder [Figure 1, teaches the use of an FPU Activation; "The Floating Point Unit (FPU) does not need to run when a hit occurs' III: A., teaches turning off the FPU when using the RAU for the output].
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, and Rengarajan before him before the effective filing date of the claimed invention to modify the adder tree disclosed by Chih to include the activation signal taught by Imani, in order to implement power gating that reduces redundant computations, increase energy savings and speedup [Imani: I. Introduction, II. Related Work, and VI. Conclusion].
However, Chih, Imani, and Rengarajan does not explicitly disclose a switching unit coupled between a power supply and the adders of the adder tree, wherein when the input parameter is not present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn on the switching unit, wherein when the input parameter is present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn off the switching unit.
In the analogous art of data processing and power gating, Bose teaches a switching unit coupled between a power supply and the adders that is controlled by a signal [Figure 2, Header device 68; "all functional units, such as an adder… can be implemented as a gatable component 56" Par. 48; "The virtual power supply 66 is decoupled from the power supply 62 by a header device 68" Par. 49, discloses a power gating Header device controlled by a control signal 72]
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, Rengarajan, and Bose before him before the effective filing date of the claimed invention to modify the adder tree as disclosed by the combination of Chih and Imani, to include the power gating architecture as taught by Bose, in order to implement power saving techniques for reduction of power consumption, switching and leakage of power [Bose: Par. 46 and 47]. The combination of Chih, Imani, and Bose discloses the additional limitations of claim 5.
Regarding claim 6, Chih, Imani, and Rengarajan disclose the invention substantially as claimed. See the discussion of claim 4 above. However, Chih and Rengarajan does not explicitly disclose the additional limitations of claim 6.
In the analogous art of Computational reuse implementations, Imani teaches
the control signal for disabling the adder, wherein when the input parameter is not present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn on the adder, wherein when the input parameter is present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn off the adder [Figure 1, teaches the use of an FPU Activation; "The Floating Point Unit (FPU) does not need to run when a hit occurs' III: A., teaches turning off the FPU when using the RAU for the output].
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, and Rengarajan before him before the effective filing date of the claimed invention to modify the adder tree disclosed by Chih to include the activation signal taught by Imani, in order to implement power gating that reduces redundant computations, increase energy savings and speedup [Imani: I. Introduction, II. Related Work, and VI. Conclusion].
However, Chih, Imani, and Rengarajan does not explicitly disclose a switching unit coupled between a ground and the adders of the adder tree, wherein when the input parameter is not present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn on the switching unit, wherein when the input parameter is present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn off the switching unit.
In the analogous art of data processing and power gating, Bose teaches a switching unit coupled between a ground and the adders that is controlled by a signal [Figure 2, Footer device 70; "all functional units, such as an adder… can be implemented as a gatable component 56" Par. 48; "virtual ground 64 is decoupled from the ground 60 through a footer device 70." Par. 49, discloses a power gating footer device controlled by a control signal 72]
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, Rengarajan, and Bose before him before the effective filing date of the claimed invention to modify the adder tree as disclosed by the combination of Chih and Imani, to include the power gating architecture as taught by Bose, in order to implement power saving techniques for reduction of power consumption, switching and leakage of power [Bose: Par. 46 and 47]. The combination of Chih, Imani, and Bose discloses the additional limitations of claim 6.
Claim 14 corresponds to claim 5. As such, claim 14 is rejected for the reasons given above for claim 5.
Claim 15 corresponds to claim 6. As such, claim 15 is rejected for the reasons given above for claim 6.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chih, Imani, and Rengarajan, and in view of Raha et al. (US 2021/0397414 A1), hereinafter Raha.
Regarding claim 8, Chih, Imani, and Rengarajan disclose the invention substantially as claimed. See the discussion of claim 1 above. Chih and Imani does not explicitly disclose the additional limitations of claim 8.
In the analogous art of arithmetic architecture for reduced power consumption, Rengarajan teaches a parameter extractor configured to extract an input parameter from the adder input [Figure 3, Address generator; "a group of bits made up of the LSBs of the predetermined number of digital words are combined by the address generator to form one DA LUT address for accessing a sum of partial products value for that LSB position" Col. 2, lines 51-55];
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, and Rengarajan before him before the effective filing date of the claimed invention to modify the RAU disclosed by the combination of Chih and Imani, to include the address generator, in order to implement an addressable Lookup table for reduction in power consumption and memory size [Rengarajan: Col.7 ll. 49-64, and Col.8 ll. 6-19].
However, Chih, Imani, and Rengarajan does not explicitly disclose wherein the parameter extractor is configured to count the number of 1 in binary representation of the adder input to obtain the input parameter.
In the analogous art of multiply-accumulate processing, Raha teaches wherein the parameter extractor is configured to count the number of 1 in binary representation of the adder input to obtain the input parameter [Figure 6, Conventional convolution architecture 92, includes the use of a ones circuit to process the input to index the lookup table].
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, Rengarajan, and Raha before him before the effective filing date of the claimed invention to modify the parameter extractor disclosed by the combination of Chih, Imani, and Rengarajan, to include the ones counting, in order to implement an addressable Lookup table for implementing binary based multiply accumulate operations using lookup tables for area and energy benefits [Raha: Par. 51-53]. The combination of Chih, Imani, Rengarajan, and Raha discloses the additional limitations of claim 8.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chih, Imani, and Rengarajan, and in view of Dibrino et al. (US 2016/0313976 A1), hereinafter Dibrino, and further in view of Van Lunteren (US 2016/0275013 A1), hereinafter Van.
Regarding claim 9, Chih, Imani, and Rengarajan disclose the invention substantially as claimed. See the discussion of claim 1 above. Chih and Imani does not explicitly disclose the additional limitations of claim 9.
In the analogous art of arithmetic architecture for reduced power consumption, Rengarajan teaches a parameter extractor configured to extract an input parameter from the adder input [Figure 3, Address generator; "a group of bits made up of the LSBs of the predetermined number of digital words are combined by the address generator to form one DA LUT address for accessing a sum of partial products value for that LSB position" Col. 2, lines 51-55];
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, and Rengarajan before him before the effective filing date of the claimed invention to modify the RAU disclosed by the combination of Chih and Imani, to include the address generator, in order to implement an addressable Lookup table for reduction in power consumption and memory size [Rengarajan: Col.7 ll. 49-64, and Col.8 ll. 6-19].
However, Chih, Imani, and Rengarajan does not explicitly disclose wherein the parameter extractor is configured to perform a parity function or a remainder function on the adder input to obtain the input parameter.
In the analogous art of data processing and lookup tables for divisions and root computations, Dibrino teaches a remainder function on the input for lookup tables [“column or quotient select mask 406 can include either selected column 220 (as in FIG. 5) extracted from partial remainder/root table 218… Division/root lookup logic 408 may lookup the selected column or quotient select mask using next partial remainder bits 412 ( e.g., y-index) in each iteration, and more specifically, truncated and possibly approximate resolved partial remainder bits 412”, Par. 52, teaches using partials remainder bits for lookup]
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, Rengarajan, and Dibrino before him before the effective filing date of the claimed invention to modify the parameter extractor disclosed by the combination of Chih, Imani, and Rengarajan, to include the remainder functionality, in order to implement an addressable Lookup table for implementing division and/or root using lookup tables for improved efficiency and power consumption [Dibrino: Par. 1, 3, 9, and 29].
In the analogous art of memory addressing and lookup table accessing, Van teaches a parity function on the input for lookup tables [“The term 'parity functions' may denote a function adapted for determining a parity of a data value, e.g., an address value” Par. 28; Fig. 3; “As input for the look-up table the Y-part 304 and a parity of the remaining part of the line address 302 which is equal to the memory bank internal address 306 are used” Par. 42, teaches the use of the parity function for the input for the lookup table]
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, Rengarajan, Dibrino and Van before him before the effective filing date of the claimed invention to modify the parameter extractor disclosed by the combination of Chih, Imani, and Rengarajan, to include the parity functionality, in order to implement an parity-based addressable Lookup table for a more flexible addressing schema and improved performance with access patterns [Van: Par. 2, 35, and 48]. The combination of Chih, Imani, Rengarajan, Dibrino and Van discloses the additional limitations of claim 9.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Chih, Imani, and Rengarajan, and further in view of Patterson et al. (NPL: “Computer Organization and Design RISC-V Edition: The Hardware Software Interface.”), hereinafter Patterson.
Regarding claim 21, Chih, Imani, and Rengarajan disclose the invention substantially as claimed. See the discussion of claim 17 above.
Imani discloses an TCAM that controls the FPU and the output of the Resistive memory [Fig.1, FPU Activation; “The Floating Point Unit (FPU) does not need to run when a hit occurs, saving energy” Sec.III.A; "When an input operand hits on TCAM, the corresponding row of resistive memory is activated to read the approximate result of computation." III: B.].
However, Chih, Imani, and Rengarajan does not explicitly disclose the additional limitations of claim 9.
In the analogous art of data processing and lookup tables for divisions and root computations, Patterson discloses turning off parts of the chips that are not used in a given clock cycle [“To try to address the power problem, … they turn off parts of the chip that are not used in a given clock cycle” Sec.1.7 The Power Wall]
It would have been obvious to one of ordinary skill in the art, looking at figure 1 of Imani that the TCAM of the RAU controls both the FPU:ADD and resistive memory, and that the output of the resistive memory is not needed if the FPU:ADD is activated, as the outputs are controlled by the FPU activation. As such, it would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, Rengarajan, and Patterson before him before the effective filing date of the claimed invention to modify the device disclosed by the combination of Chih and Imani, to power off parts of the components that is not in use, such as the resistive memory that is after the TCAM, as taught by Patterson, in order to reduce power consumption of the device [Patterson, p.107-110]. The Combination of Chih, Imani, Rengarajan, and Patterson, discloses the pre-computation circuit entering a power-save mode when determining that the input parameter is not present in the parameter table.
Response to Arguments
Applicant’s arguments, see page 10, filed 11/04/2025, with respect to Objections to the Specification and Claims have been fully considered and are persuasive. The Objections to the Specification and Claims of the Office Action mailed 08/06/2025 has been withdrawn.
Applicant's arguments, see page 11-13, filed 11/04/2025, with respect to Rejections under 35 U.S.C. 101 have been fully considered but they are not persuasive. Regarding claim 17, the applicant argues the claim integrates the judicial exception into a practical application and the claim is not directed to an abstract idea and does not fall within a “Mental Processes” grouping of abstract ideas. See Remarks p.12-13. However, the claim language is directed applying two different mathematical paths of addition to accumulate the products which is directed to “Mathematical Concepts” of Abstract Ideas. Furthermore, the application of the two different mathematical is done using generic components and the disabling of components not used is merely an insignificant extra solution activity that does not integrate the judicial exception into a practical application. See Rejection under 101 and Patterson 2013. The examiner respectfully disagrees with the applicant’s assertion to the contrary for at least the reason given above and for 35 U.S.C. 101.
Applicant's arguments, see page 14-18, filed 11/04/2025, with respect to Rejections under 35 U.S.C. 103 have been fully considered but they are not persuasive. Regarding claims 1, 10, and 17, the applicant argues that Imani does not disclose or teach the parameter identification circuit and adder tree, wherein the MUX is not the adder tree. See Remarks p.16-17. However, the applicant’s arguments is not directed to the rejection as made, the combination as made and an incomplete analysis of Imani, and. The Office Action states that the FPU: ADD is directed to the adder and not the MUX which is modified further on page 9 of the Office Action. See p.9 of the OA. Additionally, Figure 1 of Imani shows that the MUX is providing the output of the RAU or the output of the adder. The examiner respectfully disagrees with the applicant’s assertion to the contrary for at least the reason given above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenny K. Bui whose telephone number is (571)270-0604. The examiner can normally be reached 8:00 am to 3:00 pm on Monday, 8:00 am to 4:00 pm on Tuesday to Friday ET.
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/KENNY K. BUI/Patent Examiner, Art Unit 2182 (571)270-0604
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182