DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 17-19 and 26-27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite in that it fails to point out what is included or excluded by the claim language. The limitation of “performing, through a memory, data computation an adder input” is unclear because it is unclear if the “adder input” is an output of the memory or the input of the memory due to the grammatical errors. For purposes of examination, “performing, through a memory, data computation an adder input” will be considered “performing, through a memory, data computation to output an adder input” in view of the prior claims listing.
Claims 18-19 and 26-27 effectively depend on claim 17 They are rejected for the same reasons.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Chih et al. (NPL: "An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications" From IDS filed 04/14/2022), hereinafter Chih, and in view of Imani et al. (NPL: "Program Acceleration Using Nearest Distance Associative Search"), hereinafter Imani, and further in view of Rengarajan et al. (US 10,432,436 B1), hereinafter Rengarajan, and further in view of Chen et al. (NPL: “Electronic Design Automation: Chapter 2 – Fundamentals of CMOS design”), hereinafter Chen.
Regarding claim 1, Chih discloses: A compute-in memory (CIM) device, comprising:
a memory comprising a plurality of memory cells, wherein each of the memory cells is configured to multiply a respective bit of input data by a respective bit of a weight to obtain a respective bit of an adder input [Figure 16.4.1 and 16.4.2 shows an CIM array prior to an adder tree];
an addition circuit configured to receive the adder input to provide an adder output, and comprising an adder tree configured to provide the adder output [Figure 16.4.1 and 16.4.2 discloses an adder tree circuit]; and
an accumulator configured to perform an accumulative adding calculation on the adder output to provide accumulated output data [Figure 16.4.1 and 16.4.2 discloses an accumulator after the adder tree, and the use of a switch for the input for the accumulator].
However, Chih does not explicitly disclose:
an addition circuit configured to receive the adder input to provide an adder output, and comprising: a pre-computation circuit, comprising: a parameter extractor configured to extract an input parameter from the adder input; and a parameter identification circuit configured to provide a pre-computation result corresponding to the input parameter as the adder output when determining that the input parameter is present in a parameter table, and provide a control signal when determining that the input parameter is not present in the parameter table; an adder tree configured to provide the adder output according to the adder input in response to the control signal; and an accumulator directly connected to the parameter identification circuit and the adder tree.
In the analogous art of Computational reuse implementations, Imani teaches:
an addition circuit [Figure 1, FPU] configured to receive the adder input to provide an adder output, and comprising a pre-computation circuit [Resistive Associative Unit (RAU)], comprising:
a parameter identification circuit [RAU] configured to provide a pre-computation result corresponding to the input parameter as the adder output when determining that the input parameter is present in a parameter table [ternary content addressable memory (TCAM)], and provide a control signal [FPU Activation] when determining that the input parameter is not present in the parameter table [“Associative memory prestores a set of frequent patterns“ I. Introduction, teaches the use of prestored patterns; "RAU consists of a ternary content addressable memory (TCAM) to store high frequency patterns and memory for their corresponding outputs" III. GPGPU Acceleration B. Resistive Associative Unit and its Integration; "When the GPU receives inputs the memory banks are checked for a matching pattern, and if a set matching the inputs is located, the associated output is returned. The Floating Point Unit (FPU) does not need to run when a hit occurs, saving energy" III: A. Data Locality and Approximation]; and
an adder [FPU: ADD] configured to provide the adder output according to the adder input in response to the control signal [FPU Activation; Figure 1, MUX];
It would have been obvious to one of ordinary skill in the art, that the adder [FPU: ADD] taught by Imani and the adder tree [Figure 16.4.1 and 16.4.2] disclosed by Chih both results in addition. As such, It would have been obvious to one of ordinary skill in the art, having the teachings of Chih and Imani before him before the effective filing date of the claimed invention to substitute the adder tree disclosed by Chih into the adder taught by Imani to include the Resistive Associative Unit architecture, wherein the combination of Chih and Imani is substituted into the addition circuit disclosed by Chih [Figure 16.4.1, adder tree circuit], in order to implement computational reuse that reduces redundant computations, increase energy savings and speedup [Imani: I. Introduction, II. Related Work, and VI. Conclusion]. The combination of Chih and Imani discloses an addition circuit configured to receive the adder input to provide an adder output, and comprising: a pre-computation circuit, comprising a parameter identification circuit configured to provide a pre- computation result corresponding to the input parameter as the adder output when determining that the input parameter is present in a parameter table, and provide a control signal when determining that the input parameter is not present in the parameter table; and an adder tree configured to provide the adder output according to the adder input in response to the control signal;
However, Chih and Imani does not explicitly disclose a parameter extractor configured to extract an input parameter from the adder input; and an accumulator directly connected to the parameter identification circuit and the adder tree.
In the analogous art of arithmetic architecture for reduced power consumption, Rengarajan teaches a parameter extractor configured to extract an input parameter from the adder input [Figure 3, Address generator; "a group of bits made up of the LSBs of the predetermined number of digital words are combined by the address generator to form one DA LUT address for accessing a sum of partial products value for that LSB position" Col. 2, lines 51-55];
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, and Rengarajan before him before the effective filing date of the claimed invention to modify the RAU disclosed by the combination of Chih and Imani, to include the address generator taught by Rengarajan, in order to implement an addressable Lookup table for reduction in power consumption and memory size [Rengarajan: Col.7 ll. 49-64, and Col.8 ll. 6-19]. The combination of Chih, Imani, and Rengarajan discloses a parameter extractor configured to extract an input parameter from the adder input;
However, Chih, Imani, and Rengarajan does not explicitly disclose an accumulator directly connected to the parameter identification circuit and the adder tree.
Chih discloses the accumulator after the adder tree [Fig.16.4.1]
Imani teaches the use of an multiplexer to select between the parameter identification circuit [RAU] and the adder tree [FPU: ADD].
In the analogous art of multiplexer implementation and circuit design techniques, Chen teaches multiplexer implementations such as a Transmission gate multiplexer that connects the inputs to the outputs [See Figure 2.26(b)]
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, Rengarajan, and Chen before him before the effective filing date of the claimed invention to modify the multiplexer disclosed by the combination of Chih and Imani, to implement the multiplexer using transistor gates as taught by Chen, in order to implement a circuit that does not require power supply, reduce the number transistors required, and reduce gate delays [Chen: Sec.2.4.1]. the combination of Chih, Imani, and Chen discloses an accumulator directly connected to the parameter identification circuit and the adder tree.
Regarding claim 2, Chih, Imani, Rengarajan, and Chen disclose the invention substantially as claimed. See the discussion of claim 1 above. Chih does not disclose the additional limitations of claim 2.
In the analogous art of Computational reuse implementations, Imani teaches: wherein the parameter identification circuit comprises:
a parameter comparing circuit [Fig. 5, Peripheral circuitry] configured to compare the input parameter with a plurality of pre-stored parameters in the parameter table ["input data is distributed among all rows... TCAM cell with a similar stored value to the input discharges the ML" IV. RAU Hardware Design: B. Nearest Distance CAM; "An NHD detector is an resistive circuitry which samples output sense amplifier voltages in all rows... an NHD detects the first matched row(s)," IV: C. Peripheral Circuitry]; and
a storage device [resistive memory] configured to store a plurality of pre-stored results, wherein each of the pre-stored results corresponds to a respective pre-stored parameter, wherein when the input parameter is equal to one of the pre-stored parameters in the parameter table [TCAM], the parameter identification circuit is configured to determine that the input parameter is present in the parameter table, and provide the pre-stored result corresponding to the one of the pre-stored parameters as the pre-computation result ["When an input operand hits on TCAM, the corresponding row of resistive memory is activated to read the approximate result of computation." III: B.].
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, and Imani before him before the effective filing date of the claimed invention to modify the adder tree disclosed by Chih to include the Resistive Associative Unit architecture, in order to implement computational reuse that reduces redundant computations, increase energy savings and speedup [Imani: I. Introduction, II. Related Work, and VI. Conclusion]
Regarding claim 4, Chih, Imani, Rengarajan, and Chen disclose the invention substantially as claimed. See the discussion of claim 1 above. Chih further discloses wherein the adder tree comprises a plurality of adders interconnected in a tree-like configuration [Figure 16.4.2 discloses an adder tree in a tree-like configuration].
Claims 3, 10-11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Chih, Imani, Rengarajan, Chen, and in view of Bikshalu et al. (NPL: “Design and Simulation of 16 Bit Arithmetic Unit using Gating Techniques in Cadence 45nm Technology”), hereinafter Bikshalu.
Regarding claim 3, Chih, Imani, Rengarajan, and Chen disclose the invention substantially as claimed. See the discussion of claim 1 above.
Chih discloses using memory output as input into the adder tree [Figure 16.4.1].
However, Chih does not explicitly disclose the additional limitations of claim 3.
In the analogous art of Computational reuse implementations, Imani teaches
the control signal for disabling the adder, wherein when the input parameter is not present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn on the adder, wherein when the input parameter is present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn off the adder [Figure 1, teaches the use of an FPU Activation; "The Floating Point Unit (FPU) does not need to run when a hit occurs' III: A., teaches turning off the FPU when using the RAU for the output].
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, and Rengarajan before him before the effective filing date of the claimed invention to modify the adder tree disclosed by Chih to include the activation signal taught by Imani, in order to implement power gating that reduces redundant computations, increase energy savings and speedup [Imani: I. Introduction, II. Related Work, and VI. Conclusion].
However, Chih, Imani, Rengarajan, and Chen does not explicitly disclose a switching unit coupled between the memory and the adder tree, wherein when the input parameter is not present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn on the switching unit, wherein when the input parameter is present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn off the switching unit.
In the analogous art of digital signal processing and power gating, Bikshalu, teaches a switching unit between the input and an arithmetic unit [Fig. 2.2 Input Gating; “CMOS switches are used to provide power to the circuitry” Sec.2.2; “Input Gating… technique inputs are fed to only one block whose ENABLE signal is made HIGH” Sec.2.5]
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, Rengarajan, Chen, and Bikshalu before him before the effective filing date of the claimed invention to modify the inputs of the adder tree as disclosed by the combination of Chih and Imani, to include the input gating architecture as taught by Bikshalu, in order to implement a switching unit for power gating using the control signal from Imani to reduce power consumption resulting from unnecessary switching in the other blocks [Bikshalu: Fig.2.2 and Sec.2.2 and 2.5]. The combination of Chih, Imani, and Bikshalu discloses the limitations of claim 3.
Regarding claim 10, Chih disclose wherein bit number of the weight is different from bit number of the input data ["It can support input activations with programmable bit-widths (1-8 per macro), signed or unsigned, and weights with 4 different bit widths (4, 8, 12, or 16)." p. 252]
The remaining limitations of claim 10 corresponds to claims 1 and 3, wherein the combination of Chih, Imani, Rengarajan, Chen, and Bikshalu disclose the remaining limitations of claim 10 with respect to the reasons given in claim 1 and 3 and is rejected accordingly.
Claim 11 corresponds to claim 2 (and claim 1 for the parameter extractor). As such, claim 11 is rejected for the reasons given above for claim 2 (and claim 1).
Claim 13 corresponds to claim 4. As such, claim 13 is rejected for the reasons given above for claim 4.
Claims 5, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Chih, Imani, Rengarajan, and Chen, and in view of Bose et al. (US 2007/0043960 A1), hereinafter Bose.
Regarding claim 5, Chih, Imani, Rengarajan, and Chen disclose the invention substantially as claimed. See the discussion of claim 4 above. However, Chih does not explicitly disclose the additional limitations of claim 5.
In the analogous art of Computational reuse implementations, Imani teaches
the control signal for disabling the adder, wherein when the input parameter is not present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn on the adder, wherein when the input parameter is present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn off the adder [Figure 1, teaches the use of an FPU Activation; "The Floating Point Unit (FPU) does not need to run when a hit occurs' III: A., teaches turning off the FPU when using the RAU for the output].
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, and Imani before him before the effective filing date of the claimed invention to modify the adder tree disclosed by Chih to include the activation signal taught by Imani, in order to implement power gating that reduces redundant computations, increase energy savings and speedup [Imani: I. Introduction, II. Related Work, and VI. Conclusion].
However, Chih, Imani, Rengarajan, and Chen does not explicitly disclose a switching unit coupled between a power supply and the adders of the adder tree, wherein when the input parameter is not present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn on the switching unit, wherein when the input parameter is present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn off the switching unit.
In the analogous art of data processing and power gating, Bose teaches a switching unit coupled between a power supply and the adders that is controlled by a signal [Figure 2, Header device 68; "all functional units, such as an adder… can be implemented as a gatable component 56" Par. 48; "The virtual power supply 66 is decoupled from the power supply 62 by a header device 68" Par. 49, discloses a power gating Header device controlled by a control signal 72]
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, Rengarajan, Chen, and Bose before him before the effective filing date of the claimed invention to modify the adder tree as disclosed by the combination of Chih and Imani, to include the power gating architecture as taught by Bose, in order to implement power saving techniques for reduction of power consumption, switching and leakage of power [Bose: Par. 46 and 47]. The combination of Chih, Imani, and Bose discloses the additional limitations of claim 5.
Regarding claim 6, Chih, Imani, Rengarajan, and Chen disclose the invention substantially as claimed. See the discussion of claim 4 above. However, Chih and Rengarajan does not explicitly disclose the additional limitations of claim 6.
In the analogous art of Computational reuse implementations, Imani teaches
the control signal for disabling the adder, wherein when the input parameter is not present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn on the adder, wherein when the input parameter is present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn off the adder [Figure 1, teaches the use of an FPU Activation; "The Floating Point Unit (FPU) does not need to run when a hit occurs' III: A., teaches turning off the FPU when using the RAU for the output].
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, and Imani before him before the effective filing date of the claimed invention to modify the adder tree disclosed by Chih to include the activation signal taught by Imani, in order to implement power gating that reduces redundant computations, increase energy savings and speedup [Imani: I. Introduction, II. Related Work, and VI. Conclusion].
However, Chih, Imani, Rengarajan, and Chen does not explicitly disclose a switching unit coupled between a ground and the adders of the adder tree, wherein when the input parameter is not present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn on the switching unit, wherein when the input parameter is present in the parameter table, the parameter identification circuit is configured to provide the control signal to turn off the switching unit.
In the analogous art of data processing and power gating, Bose teaches a switching unit coupled between a ground and the adders that is controlled by a signal [Figure 2, Footer device 70; "all functional units, such as an adder… can be implemented as a gatable component 56" Par. 48; "virtual ground 64 is decoupled from the ground 60 through a footer device 70." Par. 49, discloses a power gating footer device controlled by a control signal 72]
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, Rengarajan, Chen, and Bose before him before the effective filing date of the claimed invention to modify the adder tree as disclosed by the combination of Chih and Imani, to include the power gating architecture as taught by Bose, in order to implement power saving techniques for reduction of power consumption, switching and leakage of power [Bose: Par. 46 and 47]. The combination of Chih, Imani, and Bose discloses the additional limitations of claim 6.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chih, Imani, Rengarajan, and Chen, and in view of Raha et al. (US 2021/0397414 A1), hereinafter Raha.
Regarding claim 8, Chih, Imani, Rengarajan, and Chen disclose the invention substantially as claimed. See the discussion of claim 1 above. Chih and Imani does not explicitly disclose the additional limitations of claim 8.
In the analogous art of arithmetic architecture for reduced power consumption, Rengarajan teaches a parameter extractor configured to extract an input parameter from the adder input [Figure 3, Address generator; "a group of bits made up of the LSBs of the predetermined number of digital words are combined by the address generator to form one DA LUT address for accessing a sum of partial products value for that LSB position" Col. 2, lines 51-55];
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, and Rengarajan before him before the effective filing date of the claimed invention to modify the RAU disclosed by the combination of Chih and Imani, to include the address generator, in order to implement an addressable Lookup table for reduction in power consumption and memory size [Rengarajan: Col.7 ll. 49-64, and Col.8 ll. 6-19].
However, Chih, Imani, Rengarajan, and Chen does not explicitly disclose wherein the parameter extractor is configured to count the number of 1 in binary representation of the adder input to obtain the input parameter.
In the analogous art of multiply-accumulate processing, Raha teaches wherein the parameter extractor is configured to count the number of 1 in binary representation of the adder input to obtain the input parameter [Figure 6, Conventional convolution architecture 92, includes the use of a ones circuit to process the input to index the lookup table].
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, Rengarajan, Chen, and Raha before him before the effective filing date of the claimed invention to modify the parameter extractor disclosed by the combination of Chih, Imani, and Rengarajan, to include the ones counting, in order to implement an addressable Lookup table for implementing binary based multiply accumulate operations using lookup tables for area and energy benefits [Raha: Par. 51-53]. The combination of Chih, Imani, Rengarajan, Chen, and Raha discloses the additional limitations of claim 8.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chih, Imani, Rengarajan, and Chen, and in view of Dibrino et al. (US 2016/0313976 A1), hereinafter Dibrino, and further in view of Van Lunteren (US 2016/0275013 A1), hereinafter Van.
Regarding claim 9, Chih, Imani, Rengarajan, and Chen disclose the invention substantially as claimed. See the discussion of claim 1 above. Chih and Imani does not explicitly disclose the additional limitations of claim 9.
In the analogous art of arithmetic architecture for reduced power consumption, Rengarajan teaches a parameter extractor configured to extract an input parameter from the adder input [Figure 3, Address generator; "a group of bits made up of the LSBs of the predetermined number of digital words are combined by the address generator to form one DA LUT address for accessing a sum of partial products value for that LSB position" Col. 2, lines 51-55];
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, and Rengarajan before him before the effective filing date of the claimed invention to modify the RAU disclosed by the combination of Chih and Imani, to include the address generator, in order to implement an addressable Lookup table for reduction in power consumption and memory size [Rengarajan: Col.7 ll. 49-64, and Col.8 ll. 6-19].
However, Chih, Imani, Rengarajan, and Chen does not explicitly disclose wherein the parameter extractor is configured to perform a parity function or a remainder function on the adder input to obtain the input parameter.
In the analogous art of data processing and lookup tables for divisions and root computations, Dibrino teaches a remainder function on the input for lookup tables [“column or quotient select mask 406 can include either selected column 220 (as in FIG. 5) extracted from partial remainder/root table 218… Division/root lookup logic 408 may lookup the selected column or quotient select mask using next partial remainder bits 412 ( e.g., y-index) in each iteration, and more specifically, truncated and possibly approximate resolved partial remainder bits 412”, Par. 52, teaches using partials remainder bits for lookup]
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, Rengarajan, and Dibrino before him before the effective filing date of the claimed invention to modify the parameter extractor disclosed by the combination of Chih, Imani, and Rengarajan, to include the remainder functionality, in order to implement an addressable Lookup table for implementing division and/or root using lookup tables for improved efficiency and power consumption [Dibrino: Par. 1, 3, 9, and 29].
In the analogous art of memory addressing and lookup table accessing, Van teaches a parity function on the input for lookup tables [“The term 'parity functions' may denote a function adapted for determining a parity of a data value, e.g., an address value” Par. 28; Fig. 3; “As input for the look-up table the Y-part 304 and a parity of the remaining part of the line address 302 which is equal to the memory bank internal address 306 are used” Par. 42, teaches the use of the parity function for the input for the lookup table]
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, Rengarajan, Dibrino and Van before him before the effective filing date of the claimed invention to modify the parameter extractor disclosed by the combination of Chih, Imani, and Rengarajan, to include the parity functionality, in order to implement an parity-based addressable Lookup table for a more flexible addressing schema and improved performance with access patterns [Van: Par. 2, 35, and 48].
The combination of Chih, Imani, Rengarajan, Chen, Dibrino and Van discloses the additional limitations of claim 9.
Claims 17-19, 22, and 26-27 are rejected under 35 U.S.C. 103 as being unpatentable over Chih, Imani, Rengarajan, and Chen, and further in view of Patterson et al. (NPL: “Computer Organization and Design RISC-V Edition: The Hardware Software Interface.”), hereinafter Patterson.
Regarding claim 17, Chih discloses: a computing method, comprising:
Performing, through a memory, data computation to output an adder input [Figure 16.4.1 and 16.4.2 shows an CIM array prior to an adder tree];
Performing, through the adder tree, an addition operation on the adder input to obtain the adder output [Figure 16.4.1 and 16.4.2 discloses an adder tree circuit];
Performing, through an accumulator, an accumulative adding calculation on the adder output to provide accumulated output data [Figure 16.4.1 and 16.4.2 discloses an accumulator after the adder tree, and the use of a switch for the input for the accumulator].
However, Chih does not explicitly disclose:
Obtaining, through an addition circuit, an input parameter from the adder input;
Determining, through a pre-computation circuit, whether the input parameter is present in a parameter table;
Providing, through the pre-computation circuit, a pre-computation result corresponding to the input parameter as an adder output, and disabling, through the pre-computation circuit, an adder tree when determining that the input parameter is present in the table;
Performing, through the adder tree, an addition operation on the adder input to obtain the adder output in response to a control signal provided by the pre-computation circuit, and the pre-computation circuit entering a power-save mode when determining that the input parameter is not present in the parameter table; and
Wherein the accumulator is directly connected to the parameter identification circuit and the adder tree.
In the analogous art of Computational reuse implementations, Imani teaches:
Determining, through a pre-computation circuit [Resistive Associative Unit (RAU)], whether the input parameter is present in a parameter table [“When an input operand hits on TCAM” Sec. III.B];
Providing, through a pre-computation circuit [RAU], a pre-computation result [ternary content addressable memory (TCAM)] corresponding to the input parameter as an adder output [“Associative memory prestores a set of frequent patterns“ I. Introduction, teaches the use of prestored patterns; "RAU consists of a ternary content addressable memory (TCAM) to store high frequency patterns and memory for their corresponding outputs" III. GPGPU Acceleration B. Resistive Associative Unit and its Integration; See Fig.1, MUX that outputs the pre-computation circuit as an output; "When the GPU receives inputs the memory banks are checked for a matching pattern, and if a set matching the inputs is located, the associated output is returned" III: A. Data Locality and Approximation],
and disabling, through the pre-computation circuit [RAU], an adder tree when determining that the input parameter is present in the table [Figure 1, FPU Activation; "The Floating Point Unit (FPU) does not need to run when a hit occurs” III: A., teaches turning off the FPU when using the RAU for the output] and
Performing, through the adder tree, an addition operation on the adder input [Figure 1, FPU] to obtain the adder output in response to a control signal [FPU Activation; Figure 1, MUX] provided by the pre-computation circuit [Resistive Associative Unit (RAU); FPU Activation], when determining that the input parameter is not present in the parameter table [Fig.1, RAU, FPU: ADD, and FPU Activation; "The Floating Point Unit (FPU) does not need to run when a hit occurs” III:A; “we assign the less frequent data to FPUs to process. In this way, we can leave the RAU block small to support high frequency patterns” Sec.III.B.2].
an addition circuit [figure 1, Floating Point unit]
an TCAM that controls the FPU and the output of the Resistive memory [Fig.1, FPU Activation; “The Floating Point Unit (FPU) does not need to run when a hit occurs, saving energy” Sec.III.A; "When an input operand hits on TCAM, the corresponding row of resistive memory is activated to read the approximate result of computation." III: B.].
It would have been obvious to one of ordinary skill in the art, that the adder [FPU: ADD] taught by Imani and the adder tree [Figure 16.4.1 and 16.4.2] disclosed by Chih both results in addition. As such, It would have been obvious to one of ordinary skill in the art, having the teachings of Chih and Imani before him before the effective filing date of the claimed invention to substitute the adder tree disclosed by Chih into the adder taught by Imani to include the Resistive Associative Unit architecture, wherein the combination of Chih and Imani is substituted into the addition circuit disclosed by Chih [Figure 16.4.1, adder tree circuit], in order to implement computational reuse that reduces redundant computations, increase energy savings and speedup [Imani: I. Introduction, II. Related Work, and VI. Conclusion]. The combination of Chih and Imani discloses determining whether the input parameter is present in a parameter table; Providing, through a pre-computation circuit, a pre-computation result corresponding to the input parameter as an adder output, and disabling an adder tree when determining that the input parameter is present in the table; and Performing an addition operation on the adder input with the adder tree to obtain the adder output in response to a control signal provided by the pre-computation circuit when determining that the input parameter is not present in the parameter table.
However, Chih and Imani does not explicitly disclose obtaining, through an addition circuit, an input parameter from the adder input; the pre-computation circuit entering a power-save mode when determining that the input parameter is not present in the parameter table; and Wherein the accumulator is directly connected to the parameter identification circuit and the adder tree.
In the analogous art of arithmetic architecture for reduced power consumption, Rengarajan teaches obtaining an input parameter from the adder input [Figure 3, Address generator; "a group of bits made up of the LSBs of the predetermined number of digital words are combined by the address generator to form one DA LUT address for accessing a sum of partial products value for that LSB position" Col. 2, lines 51-55];
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, and Rengarajan before him before the effective filing date of the claimed invention to modify the addition circuit’s RAU disclosed by the combination of Chih and Imani, to include the address generator taught by Rengarajan, in order to implement an addressable Lookup table for reduction in power consumption and memory size [Rengarajan: Col.7 ll. 49-64, and Col.8 ll. 6-19]. The combination of Chih, Imani, and Rengarajan discloses obtaining, through an addition circuit, an input parameter from the adder input;
However, Chih, Imani, and Rengarajan does not explicitly disclose the pre-computation circuit entering a power-save mode when determining that the input parameter is not present in the parameter table, and Wherein the accumulator is directly connected to the parameter identification circuit and the adder tree.
In the analogous art of multiplexer implementation and circuit design techniques, Chen teaches multiplexer implementations such as a Transmission gate multiplexer that connects the inputs to the outputs [See Figure 2.26(b)]
It would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, Rengarajan, and Chen before him before the effective filing date of the claimed invention to modify the multiplexer disclosed by the combination of Chih and Imani, to implement the multiplexer using transistor gates as taught by Chen, in order to implement a circuit that does not require power supply, reduce the number transistors required, and reduce gate delays [Chen: Sec.2.4.1]. The combination of Chih, Imani, and Chen discloses an accumulator directly connected to the parameter identification circuit and the adder tree.
However, Chih, Imani, Rengarajan, and Chen does not explicitly disclose the pre-computation circuit entering a power-save mode when determining that the input parameter is not present in the parameter table.
In the analogous art of power saving architectures, Patterson discloses turning off parts of the chips that are not used in a given clock cycle [“To try to address the power problem, … they turn off parts of the chip that are not used in a given clock cycle” Sec.1.7 The Power Wall]
It would have been obvious to one of ordinary skill in the art, looking at figure 1 of Imani that the TCAM of the RAU controls both the FPU:ADD and resistive memory, and that the output of the resistive memory is not needed if the FPU:ADD is activated, as the outputs are controlled by the FPU activation. As such, it would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, Rengarajan, Chen and Patterson before him before the effective filing date of the claimed invention to modify the device disclosed by the combination of Chih and Imani, to power off parts of the components that is not in use, such as the resistive memory that is after the TCAM, as taught by Patterson, in order to reduce power consumption of the device [Patterson, p.107-110]. The Combination of Chih, Imani, and Patterson, discloses the pre-computation circuit entering a power-save mode when determining that the input parameter is not present in the parameter table.
Regarding Claim 18, Chih, Imani, Rengarajan, Chen, and Patterson disclose the invention substantially as claimed. See the discussion of claim 17 above. Chih discloses wherein each of the memory cells is configured to multiply a respective bit of input data by a respective bit of a weight to obtain a respective bit of an adder input [Figure 16.4.1 and 16.4.2 shows an CIM array prior to an adder tree];
Regarding Claim 19, Chih, Imani, Rengarajan, Chen, and Patterson disclose the invention substantially as claimed. See the discussion of claim 17 above. A mere change in statutory class is obvious. Claim 19 is directed to claim 2, and is rejected for the reasons given in claim 2.
Regarding claim 22, Chih, Imani, Rengarajan, and Chen, disclose the invention substantially as claimed. See the discussion of claim 1 above.
Imani discloses an TCAM that controls the FPU and the output of the Resistive memory based on a hit [Fig.1, FPU Activation; “The Floating Point Unit (FPU) does not need to run when a hit occurs, saving energy” Sec.III.A; "When an input operand hits on TCAM, the corresponding row of resistive memory is activated to read the approximate result of computation." III: B.].
However, Chih, Imani, Rengarajan, and Chen does not explicitly disclose the additional limitations.
In the analogous art of data processing and lookup tables for divisions and root computations, Patterson discloses turning off parts of the chips that are not used in a given clock cycle [“To try to address the power problem, … they turn off parts of the chip that are not used in a given clock cycle” Sec.1.7 The Power Wall]
It would have been obvious to one of ordinary skill in the art, looking at figure 1 of Imani that the TCAM of the RAU controls both the FPU:ADD and resistive memory, and that the output of the resistive memory is not needed if the FPU:ADD is activated, as the outputs are controlled by the FPU activation. As such, it would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, Rengarajan, and Patterson before him before the effective filing date of the claimed invention to modify the device disclosed by the combination of Chih and Imani, to power off parts of the components that is not in use, such as the resistive memory that is after the TCAM, as taught by Patterson, in order to reduce power consumption of the device [Patterson, p.107-110]. The Combination of Chih, Imani, Rengarajan, and Patterson, discloses the pre-computation circuit entering a power-save mode when determining that the input parameter is not present in the parameter table.
Regarding claim 26, Chih, Imani, Rengarajan, Chen, and Patterson disclose the invention substantially as claimed. See the discussion of claim 17 above. Chih does not explicitly disclose the additional limitations.
Imani teaches the parameter identification circuit has a non-volatile memory [“conventional CMOS-based TCAM consists of two SRAM blocks” Sec.II]
However, Chih, Imani, Rengarajan, and Chen does not explicitly disclose the power-save mode.
In the analogous art of data processing and lookup tables for divisions and root computations, Patterson discloses turning off parts of the chips that are not used in a given clock cycle [“To try to address the power problem, … they turn off parts of the chip that are not used in a given clock cycle” Sec.1.7 The Power Wall]
It would have been obvious to one of ordinary skill in the art, looking at figure 1 of Imani that the TCAM of the RAU controls both the FPU:ADD and resistive memory, and that the output of the resistive memory is not needed if the FPU:ADD is activated, as the outputs are controlled by the FPU activation. As such, it would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, Rengarajan, and Patterson before him before the effective filing date of the claimed invention to modify the device disclosed by the combination of Chih and Imani, to power off parts of the components that is not in use, such as the resistive memory that is after the TCAM, as taught by Patterson, in order to reduce power consumption of the device [Patterson, p.107-110]. The Combination of Chih, Imani, Rengarajan, and Patterson, discloses the additional limitations.
Regarding claim 27, Chih, Imani, Rengarajan, Chen, and Patterson disclose the invention substantially as claimed. See the discussion of claim 17 above.
Imani teaches the parameter identification circuit has a volatile memory [“Resistive Random Access Memory (ReRAM) and Magnetic RAMs (MRAMs) are two common types of non-volatile memories used in memory design” Sec.II]
However, Chih, Imani, Rengarajan, and Chen does not explicitly disclose the power-save mode.
In the analogous art of data processing and lookup tables for divisions and root computations, Patterson discloses turning off parts of the chips that are not used in a given clock cycle [“To try to address the power problem, … they turn off parts of the chip that are not used in a given clock cycle” Sec.1.7 The Power Wall]
It would have been obvious to one of ordinary skill in the art, looking at figure 1 of Imani that the TCAM of the RAU controls both the FPU:ADD and resistive memory, and that the output of the resistive memory is not needed if the FPU:ADD is activated, as the outputs are controlled by the FPU activation. As such, it would have been obvious to one of ordinary skill in the art, having the teachings of Chih, Imani, Rengarajan, and Patterson before him before the effective filing date of the claimed invention to modify the device disclosed by the combination of Chih and Imani, to power off parts of the components that is not in use, such as the resistive memory that is after the TCAM, as taught by Patterson, in order to reduce power consumption of the device [Patterson, p.107-110]. The Combination of Chih, Imani, Rengarajan, and Patterson, discloses the additional limitations.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Chih, Imani, Rengarajan, Chen, and Bikshalu, and further in view of Patterson et al. (NPL: “Computer Organization and Design RISC-V Edition: The Hardware Software Interface.”), hereinafter Patterson.
Regarding claim 23, Chih, Imani, Rengarajan, Chen, and Bikshalu disclose the invention substantially as claimed. See the discussion of claim 10 above. Claim 23 is directed to claim 22, and is rejected for the reasons given in claim 22
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Chih, Imani, Rengarajan, Chen, and Bikshalu, and further in view of Raha.
Regarding claim 24, Chih, Imani, Rengarajan, Chen, and Bikshalu disclose the invention substantially as claimed. See the discussion of claim 11 above. Claim 24 is directed to claim 8, and is rejected for the reasons given in claim 8
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Chih, Imani, Rengarajan, Chen, and Bikshalu, and further in view of Dibrino, and further in view of Van.
Regarding claim 25, Chih, Imani, Rengarajan, Chen, and Bikshalu disclose the invention substantially as claimed. See the discussion of claim 11 above. Claim 25 is directed to claim 9, and is rejected for the reasons given in claim 9
Response to Amendment
Applicant’s amendment to claim 17 is non-compliant with 37 CFR 1.121(c)(2) due to not showing the deleted matter by strike-through (or double brackets). This issue has been waived for this amendment. Examiner warns that any future non-compliant amendment will result in a notice of non-compliant amendment.
Response to Arguments
Applicant’s arguments, see pages 10-14, filed 04/04/2026, with respect to Rejection under 35 U.S.C. 101 have been fully considered and are persuasive. The Rejection under 35 U.S.C. 101 of the Office Action mailed 02/14/2026 has been withdrawn.
Applicant's arguments, see pages 15-20, filed 04/04/2026, with respect to Rejections under 35 U.S.C. 103 have been fully considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the arguments.
Conclusion
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/KENNY K. BUI/Patent Examiner, Art Unit 2182 (571)270-0604
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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