Status of Claims
Claims 1-20 pending.
Claims 8-20 withdrawn from consideration.
Response to Amendment
The amendment filed 11/10/2025 has been accepted and entered.
Response to Arguments
Applicant’s arguments (in addition to the replacement drawing), filed 11/10/2025, with respect to the claim objections and drawings have been fully considered and are persuasive. The claim objections and drawings objection have been withdrawn.
Applicant’s arguments (in view of the amendment to claim 1), filed 11/10/2025, with respect to the 35 U.S.C. 112(b) rejections of claim 1 and subsequently the dependent claims 2-7 have been fully considered and are persuasive. The 35 U.S.C. 112(b) rejection to claim 1 has been withdrawn.
Applicant’s amendments to independent claim 1, and its respective dependent claims and corresponding arguments, see page 9-10 of Applicant’s remarks filed 11/10/2025, with respect to the 35 U.S.C. 102 rejections of claim 1 has been fully considered and is persuasive. Liebmann does not teach all of the limitations of amended claim 1 (i.e. the first lower transistor comprising a first nanosheet stack and the second lower transistor comprising a second nanosheet stack). The 35 U.S.C. 102 rejection of claim 1 has been withdrawn.
Applicant’s amendments to independent claim 1, and its respective dependent claims and corresponding arguments, see page 10-11 of Applicant’s remarks filed 11/10/2025, with respect to the 35 U.S.C. 103 rejections of claim 1 has been fully considered and is persuasive. Smith does not teach all of the limitations of amended claim 1, specifically, Smith does not explicitly provide a motivation for incorporating a cross connection between independent vertically stacked nanosheet devices, therefore the rejection is withdrawn.
In view of the amendment to independent claim 1, new references have been applied (new reference includes, US 2022/0416048 A1 Smith et al, US 2021/0143159 A1 Zhang et al, US 2020/0075574 A1 Smith et al, US 2022/0181318A1 Liebmann, see below). Claims 1 and 3-5 now stand rejected under 35 U.S.C. 103 as being unpatentable over Smith in view of Zhang. Claims 2 and 6 now stand rejected under 35 U.S.C. 103 as being unpatentable over Smith in view of Zhang and further in view of Smith2.
Applicant’s argument to dependent claim 7, see page 11-12 of Applicant’s remarks filed 11/10/2025, with respect to the 35 U.S.C. 103 rejections of claim 7 has been fully considered and is persuasive. Smith does not teach all of the limitations of amended claim 1, specifically, Smith does not explicitly provide a motivation for incorporating a cross connection between independent vertically stacked nanosheet devices, therefore the rejection is withdrawn.
In view of the amendment to independent claim 1, new references have been applied (new reference includes, US 2022/0416048 A1 Smith et al, US 2021/0143159 A1 Zhang et al, US 2020/0075574 A1 Smith et al, US 2022/0181318A1 Liebmann, see below). Claim 7 now stands rejected under 35 U.S.C. 103 as being unpatentable over Smith in view of Zhang and further in view of Liebmann.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0416048 A1 Smith et al (herein “Smith”) in view of US 2021/0143159 A1 Zhang et al (herein “Zhang”).
Regarding Claim 1, Smith discloses:
A semiconductor device (see generally Fig. 20 and paragraph [0030]-[0044]) comprising:
a first pair of stacked transistors (see annotated Fig. 20 below) comprising a first upper transistor (#1U, see below) and a first lower transistor (#1L, see below), the first lower transistor comprising a first nanosheet stack (Fig. 20, [0008]);
a second pair of stacked transistors (see annotated Fig. 20 below) comprising a second upper transistor (#2U, see below) and a second lower transistor (#2L, see below), the second lower transistor comprising a second nanosheet stack;
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Smith Fig. 20 – Annotated by Examiner
Smith does not explicitly disclose:
a first cross-connection between the gate of the first upper transistor and the gate of the second lower transistor.
However, in analogous art, Zhang teaches:
See Fig. 17. See [0004], [0028]-[0030], [0082]-[0089]. Zhang discloses cross connections electrically contacting the gate structures and/or the S/D epitaxial structures, which are electrically connected to the gate structures of each respective transistor in the first or second stacked transistor structures.
a first cross-connection (#354-2) between the gate of the first upper transistor (#1U, see annotated Fig. 17 below) and the gate of the second lower transistor (#2L, see annotated Fig. 17 below).
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Zhang Fig. 17 – Annotated by Examiner
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Zhang to the device disclosed by Smith and form cross-connections between diagonally adjacent transistor structures, i.e. the first upper transistor and the second lower transistor, like the cross-connection shown in Zhang Fig. 17. Doing so would allow the stacked transistor structure to allow bits to be stored on the four transistors as a cross-coupled inverter (Zhang [0028]).
Regarding Claim 3, Smith in view of Zhang discloses:
The semiconductor device according to claim 1, wherein the first upper transistor is a first FET (field effect transistor) (see Smith [0035]) and the second lower transistor is a second FET (see Smith [0035]), and wherein the first cross-connection (see annotated Fig. 17 above) forms a first gate connecting the first FET (see Smith [0035]) to the second FET (see Smith [0035]).
Note, electrically connecting the first upper gate to the second lower gate, like under the combination disclosed by Smith in view of Zhang would result in a structure akin to a common gate. In other words, by connecting the two together in the manner previously disclosed, although not explicitly disclosed, would have the qualities of a common gate. In addition, see Smith [0025] and [0050].
Regarding Claim 4, Smith discloses:
The semiconductor device according to claim 1, wherein the first upper transistor is nFET and the second lower transistor is pFET (see paragraph [0034] in reference to Fig. 1, “Each of the semiconductor devices 101a, 101b, 102a, 102b, 103a, 103b, 104a and 104b can include a PMOS device or an NMOS device.”).
Note, Depending on the selection of the first/second and upper/lower transistor, a person skilled in the art before the effective filing date of the claimed invention would recognize the ability to select an nFET or a pFET transistor and the included linking techniques (see rejections for claims 1-3) and form the device such that the first/second and upper/lower transistor is pFET or nFET respectively.
Regarding Claim 5, Smith discloses:
The semiconductor device according to claim 1, wherein the first transistor is pFET and the second transistor is nFET (see paragraph [0034] in reference to Fig. 1, “Each of the semiconductor devices 101a, 101b, 102a, 102b, 103a, 103b, 104a and 104b can include a PMOS device or an NMOS device.”).
Note, Depending on the selection of the first/second and upper/lower transistor, a person skilled in the art before the effective filing date of the claimed invention would recognize the ability to select an nFET or a pFET transistor and the included linking techniques (see rejections for claims 1-3) and form the device such that the first/second and upper/lower transistor is pFET or nFET respectively.
Claim 2 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0416048 A1 Smith et al in view of US 2021/0143159 A1 Zhang et al and further in view of US 2020/0075574 A1 Smith et al (herein “Smith2”).
Regarding Claim 2, Smith in view of Zhang discloses: the semiconductor device according to claim 1.
Smith in view of Zhang does not explicitly disclose:
further comprising a second cross-connection between the gate of the first lower transistor and the gate of the second upper transistor.
However, in analogous art, Smith2 teaches:
See Fig. 8. Smith teaches backside connections (and subsequently generic via connections on the frontside of the semiconductor device) to the gate structure of the bottom transistor structures.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Smith2 to the device disclosed by Smith in view of Zhang and include a second cross connection electrically connecting the gates of the first lower transistor and the second upper transistor. Smith in view of Zhang discloses the use of cross connections to connect gates of diagonally adjacent transistor structures, and Smith2 discloses other connections (like for instance the cross connections previously taught) attached to the front side of each of the gate structures, as well as a shared gate structure as can be seen in Fig. 8 between neighboring transistor structures. A person skilled in the art before the effective filing date of the claimed invention would recognize the ability to connect the individual gate structures using a cross connection, like the one disclosed by Zhang and using a structure like the one disclosed by Smith2 utilizing the vias connected to the front side of each gate, and link together diagonally adjacent gates using these conductive pathways in order to form an inverter, which claim 1 and subsequent dependent claim 2 appears to be.
Regarding Claim 6, Smith in view of Zhang discloses: The semiconductor device according to claim 1,
Smith in view of Zhang does not explicitly disclose:
wherein the first cross-connection comprises a front side connection.
However, in analogous art, Smith2 teaches:
wherein the first cross-connection comprises a front side connection.
See Fig. 8 showing a vertical conductive connection to front side of transistor structure #730a,b,c. As discussed in rejection for claim 1, a person skilled in the art before the effective filing date of the claimed invention would recognize the ability to form cross connection to merge two corresponding gate structures, in this case utilizing a front side contact/connection like the vias shown in Fig. 8 as the cross connection.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Smith2 to the device disclosed by Smith in view of Zhang and form the cross connection such that it is formed as a front side connection. Doing so would be a simple substitution that a person skilled in the art would recognize as a way to form a common gate between diagonally adjacent gates by utilizing a via connector like the ones shown in Smith2 Fig. 8.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0416048 A1 Smith et al in view of US 2021/0143159 A1 Zhang et al and further in view of US 2022/0181318 A1 Liebmann et al (herein “Liebmann”).
Regarding Claim 7, Smith in view of Zhang discloses The semiconductor device according to claim 1,
Smith does not explicitly disclose:
wherein the first cross-connection comprises a back side connection.
However, in analogous art, Liebmann teaches:
wherein the first cross-connection comprises a back side connection (see generally Fig. 5, Gate structure #503 with front side connection #523 and subsequent backside connection to gate structure #507).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Liebmann to the device disclosed by Smith and include backside connections like the one shown in Fig. 5 to vertically merge corresponding gate structures. Doing so would be a simple substitution that a person skilled in the art would recognize as a way to form a common gate between diagonally adjacent gates by utilizing a via connector like the ones shown in Liebman Fig. 5.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ANDREW VICTOR PROSTOR/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812