The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7, 18-20 and 25-26 are rejected under 35 U.S.C. 103 as being unpatentable over Jones et al. (5,541,450), in view of Yuan et al. (2017/0092626) Cleeves (6,004,874) and Yamazaki (7,413,937).Regarding claim 7, Jones et al. teach in figure 1 and related text a rewiring package chip, comprising:
a chip 18;
a plurality of pads 22, disposed on a surface of the chip,
wherein each of the plurality of pads comprises a first surface and a second surface opposite to the first surface, and the second surface of each of the plurality of pads is in direct contact with the surface of the chip 18; and
a dielectric layer 24, covering the surface of the chip where the plurality of pads are disposed and covering the plurality of pads,
wherein the dielectric layer 24 is in direct contact with the first surface of each of the plurality of pads 22, the dielectric layer comprises dielectric, and a conductive surface of each of the plurality of pads 22 is in direct contact with the dielectric, and
the dielectric layer comprises a first dielectric layer 24 and a second dielectric layer (top part of element 24), entire first dielectric layer is only disposed between the second dielectric layer and the surface of the chip, and the first dielectric layer and a part of the second dielectric layer are stacked with each other on the first surface of each of the plurality of pads.
Jones et al. do not teach that the first dielectric layer and the second dielectric layer are made of different materials, a material of the first dielectric layer is the silicon dioxide and the second dielectric layer comprises resin.
Yuan et al. teach in figure 1F and related text that encapsulant 126 comprises combination of silicon oxide and silicon nitride.
Cleeves teaches in figure 4 and related text that it conventional to use ONO as a dielectric material.
Yamazaki teaches in figure 1D and related text a first dielectric layer 115 comprising silicon oxide and a second dielectric layer 116 comprises resin.
Yamazaki, Cleeves, Jones et al. and Yuan et al. are analogous art because they are directed to dielectric materials and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jones et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use ONO as the dielectric material, as taught by Cleeves and Yuan et al., in the device of Jones et al., in order to reduce the cost of making the device by using conventional material and in order to provide better protection to the chip.
It is noted that substitution of materials is not patentable even when the substitution is new and useful. Safetran Systems Corp. v. Federal Sign & Signal Corp. (DC NIII, 1981) 215 USPQ 979.
It is further held that it is within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007) (“The combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results.”).
Regarding claim 18, Jones et al. teach in figure 1 and related text that the conductive surface of each of the plurality of pads is in direct contact with the dielectric layer.
Regarding claim 19, in the combined device, all of the silicon dioxide is disposed between the second dielectric layer and the surface of the chip.
Regarding claim 20, Jones et al. teach in figure 1 and related text that the top part of the dielectric layer is configured to wrap around the bottom of the first dielectric layer and the chip. Therefore, in the combined device, the second dielectric layer is configured to wrap around the first dielectric layer and the chip.
Regarding claim 25, Jones et al. teach in figure 1 and related text that each of the plurality of pads is embedded in the dielectric layer, so that all surfaces of each of the plurality of pads, except for the second surface, are in direct contact with the dielectric layer.
Regarding claim 26, in the combined device, the material of the second dielectric layer comprises resin, the first dielectric layer is in direct contact with the first surface of each of the plurality of pads, and the second dielectric layer is configured to wrap around the first dielectric layer and the chip.
Claims 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Jones et al. (5,541,450), Yuan et al. (2017/0092626), Cleeves (6,004,874) and Yamazaki (7,413,937), as applied to claim 7 above, and further in view of Paik et al. (5,879,964).Regarding claim 22, Yamazaki, Cleeves, Jones et al. and Yuan et al. teach substantially the entire claimed structure, as applied to the claims above, except having the dielectric layer defines a through hole at a position corresponding to each of the plurality of pads.
Paik et al. teach in figure 4A and related text a dielectric layer 4 defines a through hole 8 at a position corresponding to each of a plurality of pads which may be placed on chip 1.
Yamazaki, Paik et al., Cleeves, Jones et al. and Yuan et al. are analogous art because they are directed to dielectric materials and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jones et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use the dielectric layer defines a through hole at a position corresponding to each of the plurality of pads, as taught by Paik et al., in prior art’s device, in order to provide better protection to the electrical connection to the chip by not exposing the electrical wiring connection to the environment.
Regarding claim 23, Paik et al. teach in figure 4A and related text a conductive post, received in the through hole, wherein an end of the conductive post is connected to each of the plurality of pads (of the combined device), and the other end of the conductive post 8 is exposed from the dielectric layer.
: a conductive post, received in the through hole, wherein an end of the conductive post is connected to each of the plurality of pads, and the other end of the conductive post is exposed from the dielectric layer 4.
Regarding claim 24, the claimed limitations of “the through hole is an acid etched hole or a plasma bombardment hole”, these are process limitations which would not carry patentable weight in this claim drawn to a structure, because distinct structure is not necessarily produced. The formation of the through hole by using an acid etched hole or a plasma bombardment hole does not produce a structure which is different from a structure wherein the through hole is formed by other methods.
Note that a “product by process” claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. Note that the applicant has the burden of proof in such cases, as the above case law makes clear.
Claims 27-30 are rejected under 35 U.S.C. 103 as being unpatentable over Jones et al. (5,541,450), in view of Tanaka et al. (7,544,981).
Regarding claims 27-30, Jones et al. teach substantially the entire claimed structure, as applied to the claims above, including the first dielectric layer comprises a top surface away from the chip and a bottom surface that is in direct contact with the chip, and entire top surface of the first dielectric layer is in direct contact with the second dielectric layer.
Jones et al. do not teach having the dielectric layer consists of a first dielectric layer and a second dielectric layer, the first dielectric layer and the second dielectric layer are made of different materials, a material of the first dielectric layer is the silicon dioxide.
Tanaka et al. teach in figure 12D and related text a dielectric layer 1129 consists of a first dielectric layer and a second dielectric layer, the first dielectric layer and the second dielectric layer are made of different materials, a material of the first dielectric layer is the silicon dioxide and a material of the second dielectric layer comprises resin.
Jones et al. and Tanaka et al. are analogous art because they are directed to dielectric materials and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jones et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use a laminated dielectric layer consists of a first dielectric layer and a second dielectric layer, the first dielectric layer and the second dielectric layer are made of different materials, a material of the first dielectric layer is the silicon dioxide and a material of the second dielectric layer comprises resin, as taught by Tanaka et al., in the device of Jones et al., in order to provide better protection to the chip.
It is noted that substitution of materials is not patentable even when the substitution is new and useful. Safetran Systems Corp. v. Federal Sign & Signal Corp. (DC NIII, 1981) 215 USPQ 979.
It is further held that it is within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007) (“The combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results.”).
Response to Arguments
1. Applicants argue that “From FIG. 1 of Jones, it can be seen that the encapsulating enclosure 24 is a single, continuous layer to cover the semiconductor die 18, the wire bonds 19, and a portion of substrate 11. It can also be seen that the encapsulating enclosure 24 has a nearly flat top surface and shows no visible demarcation line that would indicate it is composed of two distinct, stacked material layers.
Applicants continue with the same arguments in various recitation in the arguments, including with respect to Tanaka.
1. It is noted that the claims recite "the dielectric layer comprises a first dielectric layer 24 and a second dielectric layer”. If applicants insist that their one dielectric layer can comprise two layers, and the applied reference cannot have one continuous layer, then this issue will be address as a 112 objection.
2. Applicants argue that in Yamazaki, “The silicon oxide film 115 is not in direct contact with any pad, as shown in FIG. 1D of Yamazaki. That is, the teaching of Yamazaki is: the silicon oxide film 115 that is covered by the inter-layer insulating film 116 resin is not indirect contact with any pad”.
2. Yamazaki was not cited to teach an artisan that the silicon oxide film is in direct contact with a pad. The primary reference to Jones et al. teaches that the silicon oxide film is in direct contact with a pad. Yamazaki was cited to teach an artisan that a first dielectric layer 115 comprising silicon oxide and a second dielectric layer 116 comprises resin.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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O.N. /ORI NADAV/
11/11/2025 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800
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