DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
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Status of claim(s) to be treated in this office action:
Independent: 1, 10 and 21.
Pending: 1-13 and 21-27.
Canceled: 14-20.
Response to Arguments
Applicant' s arguments with respect to claim(s) 1-7 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Ando et al., US PG pub. 20200373482 A1.
Re: Independent Claim 1, Ando discloses an active region (260, FIG. 11);
a conductive gate electrode (136, Fig. 11) disposed over the active region (260, FIG. 11), wherein an upper surface of the conductive gate electrode (136, Fig. 11) defines a first recess (136 formed a recess where 134 formed in it, fig. 11);
a conductive layer (134, fig. 9 and 11) disposed over the conductive gate electrode (136, Fig. 11), wherein an upper surface of the conductive layer (134, fig. 9 and 11) defines a second recess (315, fig. 9) that is disposed within the first recess (136 formed a recess where 134 formed in it, fig. 11);
a silicon-containing layer (310, fig. 10-11) disposed over a first portion of the conductive layer (134, fig. 9 and 11) and partially filling the second recess (315, fig. 9);
a dielectric layer (210, fig. 11) disposed over a second portion of the conductive layer (134, fig. 9 and 11); and
a gate via (240, fig. 11) vertically extending through the silicon-containing layer (310, fig. 10-11), wherein the gate via (240, fig. 11) is disposed over, and electrically coupled to, the conductive gate electrode (136, Fig. 11).
Re: Claim 2, Ando disclose(s) all the limitations of claim 1 on which this claim depends. Ando further discloses: wherein the silicon-containing layer (310, fig. 10-11) and the dielectric layer (210, fig. 11) have different material compositions (310 an ILD layer is made of silicon oxide and 210 switch layer is made of high dielectric material such as HfO (¶0027 and ¶0033)).
Re: Claim 3, Ando disclose(s) all the limitations of claim 1 on which this claim depends. Ando further discloses: wherein the silicon-containing layer (310, fig. 10-11) contains silicon, silicon oxide, or silicon nitride (¶0027).
Re: Claim 4, Ando disclose(s) all the limitations of claim 1 on which this claim depends. Ando further discloses: wherein the conductive layer (134, fig. 9 and 11) contains tungsten or chlorine (¶0031, fig. 11).
Re: Claim 5, Ando disclose(s) all the limitations of claim 1 on which this claim depends. Ando further discloses: wherein the second recess (315, fig. 9) includes a sidewall segment (114, fig. 11) of the conductive layer (134, fig. 9 and 11), the sidewall segment (114, fig. 11) extending at least partially in a vertical direction.
Re: Claim 6, Ando disclose(s) all the limitations of claim 1 on which this claim depends. Ando further discloses: wherein:
an upper surface of the conductive gate electrode (136, Fig. 11) defines a recess;
the first portion of the conductive layer (134, fig. 9 and 11) is disposed in the first recess (136 formed a recess where 134 formed in it, fig. 11); and
the second portion of the conductive layer (134, fig. 9 and 11) is disposed outside of the first recess (136 formed a recess where 134 formed in it, fig. 11).
Re: Claim 7, Ando disclose(s) all the limitations of claim 1 on which this claim depends. Ando further discloses: gate spacers (114, fig. 11) disposed on sidewalls of the conductive gate electrode (136, Fig. 11) and the dielectric layer (210, fig. 11), wherein at least the dielectric layer (210, fig. 11) is in direct physical contact (corner of 114 share a corner with 210) with the gate spacers (114, fig. 11).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ando et al., US PG pub. 20200373482 A1 in view of Fukuo et al., US patent 10256167 B1.
Re: Claim 8, Ando disclose(s) all the limitations of claim 1 on which this claim depends. Ando further discloses: the conductive gate electrode (136, Fig. 11) is a first conductive gate electrode (136, Fig. 11) of a first transistor.
Ando is silent regarding: the device further includes a second transistor having a shorter channel than the first transistor; the second transistor includes a second conductive gate electrode (136, Fig. 11); and an uppermost surface of the first conductive gate electrode (136, Fig. 11) has a substantially similar vertical elevation as an uppermost surface of the second conductive gate electrode (136, Fig. 11).
Fukuo discloses in figure 1, fig. 24 and fig. 26 the conductive gate electrode 752 is a first conductive gate electrode 752 of a first transistor 702; the device further includes a second transistor 704 having a shorter channel than the first transistor 702 includes a second conductive gate electrode 752 and an uppermost surface of the first conductive gate electrode 752 has a substantially similar vertical elevation as an uppermost surface of the second conductive gate electrode 752.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include one transistor to have shorter channel than another transistor since a memory device can balancing performance for example fast transistors for critical path such as wordline activation this can increase respond time with memory device.
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Yu et al., US PG pub. 20180005869 A1”) discloses a substrate having a hardmask layer thereover. The hardmask layer is patterned to expose the substrate. The substrate is etched through the patterned hardmask layer to form a first fin element and a second fin element extending from the substrate. An isolation feature between the first and second fin elements is formed, where the isolation feature has a first etch rate in a first solution. A laser anneal process is performed to irradiate the isolation feature with a pulsed laser beam. A pulse duration of the pulsed laser beam is adjusted based on a height of the isolation feature. The isolation feature after performing the laser anneal process has a second etch rate less than the first etch rate in the first solution.
* (“Chen et al., US PG pub. 20170186849 A1”) discloses a semiconductor device includes a first gate structure disposed on a substrate and extending in a first direction. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode, first sidewall spacers disposed on opposing side faces of the first gate electrode and the first cap insulating layer and second sidewall spacers disposed over the first sidewall spacers. The semiconductor device further includes a first protective layer formed over the first cap insulating layer, the first sidewall spacers and the second sidewall spacers. The first protective layer has a π-shape having a head portion and two leg portions in a cross section along a second direction perpendicular to the first direction.
* (“Kim et al., US PG pub. 20180219010 A1”) discloses an integrated circuit device includes a substrate including a device active region, a fin-type active region protruding from the substrate on the device active region, a gate line crossing the fin-type active region and overlapping a surface and opposite sidewalls of the fin-type active region, an insulating spacer disposed on sidewalls of the gate line, a source region and a drain region disposed on the fin-type active region at opposite sides of the gate line, a first conductive plug connected the source or drain regions, and a capping layer disposed on the gate line and extending parallel to the gate line. The capping layer includes a first part overlapping the gate line, and a second part overlapping the insulating spacer. The first and second parts have different compositions with respect to each other. The second part contacts the first part and the first conductive plug.
Allowable Subject Matter
Claims 10-13 and 21-27 are allowed, as stated in Non-Final Rejection Office Action dated 12/30/2025 regarding to claims 10-13 and 21-27 are allowable.
Claim(s) 9 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re: Claim 9, the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: wherein the conductive layer is a first conductive layer, the dielectric layer is a first dielectric layer, and the gate via is a first gate via, and wherein the second transistor further includes:
a second conductive layer disposed over the second conductive gate electrode, the second conductive layer and the first conductive layer having substantially similar material compositions;
a second dielectric layer disposed over the second conductive layer, the second dielectric layer and the first dielectric layer having substantially similar material compositions; and
a second gate via disposed over the second conductive layer, wherein the second gate via vertically extends through the second dielectric layer and is in direct physical contact with the second dielectric layer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached on 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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