Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/3/2025 has been entered.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the previously mailed PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Response to Arguments
Applicant's arguments directed to the newly amended claims filed 2/19/2026 have been fully considered but they are not persuasive.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Patil et al. ( US 20210351145 A1) in view of Hsu et al. (US 8476735 B2) in view of BHATTACHERJEE et al. (WO 2021173205 A1).
Claim 1. Patil discloses a package comprising: a printed circuit board; an interposer coupled to the printed circuit board 289, the interposer 200 including:
a substrate 270 including at least one via; a multilayer structure 206/202 disposed above the substrate, the multilayer structure including a top layer with an array including a plurality of passive devices 210/212/216 integrated into at least one of the substrate or a dielectric 250 of the multilayer structure, wherein the at least one via couples the plurality of passive devices to the printed circuit board (Fig. 3); and a trace 242 disposed above the multilayer structure and connecting at least one passive device of the plurality of passive devices to a pad 242 disposed above the multilayer structure (Note: the passive devices are shown the capable of being directly and/or indirectly electrically connected thought the upper most UBM trace level all the way to the bottom most PCB level through vias, and metallization/RDL levels of the multilayer structure. Generic electrical routing as claimed is a known obvious design choice in the art in order to integrate components for direct coupling to a PCB. As detailed in Patil, such design in integrating arrays of passive devices in a multilayer/level interposer with metallization levels that include vias and traces for routing is a known engineering practice to optimize space and performance by allowing for direct coupling of devices to a PCB. As such would be a obvious, logical and straightforward choice for one of ordinary skill in the art of circuit board design.) ; the array including a property defined by the at least one passive device which is connected to the trace; and a die 304 coupled to the pad, the plurality of passive devices 210/212/216 being positioned beneath the die 304 (Patil, Fig. 3).
Patil may however be silent upon the implied structural limitation of wherein the interposer is configured to enable mask-based adjustment of the trace connecting the passive devices, by changing a top mask of the interposer, for iterative tuning of the die to improve radio frequency (RF) performance. At the time of the invention, advanced interposers were known and capable of being modified/tuned. Such interposes are disclosed in BHATTACHERJEE et al. paragraph 51, which teaches interposers for which die and chips are or will be attached may be modified and/or tuned. Such interposers further include traces and passive devices for RF circuits that are part of the interposer.
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Further as specified in Hsu et al., the passive devices of a interposer may be connected and unconnected for the purpose of post manufacture-tuning. See Claims 1, 7 and 11 of Hsu for a direct explicit and concise teaching. In the Hsu document, the analogous device structure as claimed is disclosed. Hsu teaches:
a printed circuit board 50 (Col. 8 ln 60+ interpose may on a PCB during post manufacture tuning.);
an interposer 100 coupled to the printed circuit board 50 (Hsu, Abstract [interposer] & Col. 8 – interposer may be on a package substrate such as a PCB), the interposer including:
a substrate 130 including at least one via (Hsu figs. 4-9B- all embodiments demonstrate the inclusion of at least one via. See fig. 5, element 143 for a example.);
a multilayer 135 structure disposed above the substrate, the multilayer structure including a top layer with an array including a plurality of passive devices integrated into at least one of the substrate or a dielectric of the multilayer structure (Hsu Abstract), wherein the at least one via couples the plurality of passive devices to the printed circuit board (Hsu figs. 4-9B- all embodiments demonstrate the inclusion of at least one via. See fig. 5, element 143 for a example. The purposes of a VIA is to provide electrical connection thought a device and or layer to another level.);
a trace 105a/215/243 disposed above the multilayer structure and connecting at least one passive device of the plurality of passive devices to a pad disposed above the multilayer structure; the array including a property defined by the at least one passive device which is connected to the trace (Hsu- Col. 10 & Figs. 7B 8a-9B – trace and trace pads are used to selectively connect passive devices of the interposer.); and
a die coupled to the pad, the plurality of passive devices being positioned beneath the die (Hsu figs. 10C & 12A-C);
wherein the interposer is configured to enable mask-based adjustment of the trace connecting the passive devices, by changing a top mask of the interposer, for iterative tuning of the die to improve radio frequency (RF) performance (Hsu, Figs. 7A-7C & Col. 9),
the interposer comprising one or more passive devices integrated into the interposer and unconnected to the trace,the one more passive devices being configured to adjust an RF response of the die (Hsu – Abstract & claims 1, 7 & 11).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the interposer of Patil with “tunable” interposer of BHATTACHERJEE et al. and/or Hsu et al, since applying a known technique (mask tunable) to a known device ready for improvement (a interposer comprising RF passive circuity) to yield predictable results (lower cost being able to tune the interposer as needed) is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
Regarding the further limitation of “the one or more passive devices being configured in series or parallel relative to one another to provide a predetermined resistance or capacitance value allowed by the trace connecting the one or more passive devices, the plurality of passive devise comprising a first set of device and a second set of devices, the first set of devices being coupled to the trace and the second set of devices being unconnected to the trace, the second set of devices being provided to adjust resistance or capacitance of the plurality of passive devices in an additional mask fabrication without refabricating an underlying layer,” this language fails to provide any meaningful structural distinction over the prior art teachings of Hsu. It is a fundamental principle of RF circuitry that passive devices (resistors, capacitors, inductors) must be configured in series or parallel to achieve specific electrical characteristics. Because Hsu explicitly teaches the presence of these devices on an interposer, the claimed configurations are not just suggested; they are necessitated by the functional requirements of the circuit. The use of a “first set” (connected) and “second set” (unconnected) of devices is a textbook method for post-manufacture tuning, as shown in Fig. 3 of Hsu. A PHOSITA would understand that providing extra, unconnected components is a routine design choice to allow for resistance of capacitance adjustments via mask fabrication. Such tuning naturally results in a device where some components are coupled to the trace and others remain isolated. Therefore, the claimed arrangement is nothing more than the predictable result of applying standard tuning techniques to the structures already disclosed by Hsu1 [Fig. 3].
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Claim 2. Patil in view of BHATTACHERJEE et al. in view of Hsu et al. discloses a package of claim 1, wherein the array includes at least one additional passive device which is not connected to the pad by the trace, wherein the property of the array is adjustable by connecting the at least one passive device with the at least one additional passive device by the trace for tuning the die (Patil et al. Figs. 3-11; See also regarding claim 1.).
Claim 3. Patil in view of BHATTACHERJEE et al. in view of Hsu et al. discloses a package of claim 1, further comprising an additional die (Patil disclose a plurality of integrated devices such as die may be coupled to the PCB.) coupled to the printed circuit board; wherein the array includes at least one additional passive device which is not connected to the pad by the trace, wherein the at least one additional passive device is coupled to the additional die (Patil et al. Figs. 3-11; See also regarding claim 1.).
Claim(s) 4-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Patil et al. ( US 20210351145 A1) in view of BHATTACHERJEE et al. (WO 2021173205 A1)in view of Viswanathan et al. (US 20140070397 A1).
Claim 4. Patil in view of BHATTACHERJEE et al. in view of Hsu et al. discloses a package of claim 3, however may be silent upon the capability of wherein the at least one additional passive device is coupled to the additional die by a wire-bond. At the time of the invention, it was known in the art that wire bonding was a known and understood means of connecting active and passive devices in interposer device structures. For support see Viswanathan et al. ¶18 and figures 3-6.
When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill in the art has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co v. Teleflex Inc.
Claim 5. Patil in view of BHATTACHERJEE et al. in view of Hsu et al. in view of Viswanathan discloses a package of claim 3, wherein the interposer includes a through via and an additional trace disposed above the multilayer structure; wherein the additional trace connects the through via and the at least one additional passive device; wherein the at least one additional passive device is coupled to the additional die by the through via (Patil et al. Figs. 3-11; See also regarding claim 1.).
Claim 6. Patil in view of BHATTACHERJEE et al. in view of Hsu et al. in view of Viswanathan discloses a package of claim 1, wherein the interposer is a passive interposer (Patil et al. Figs. 3-11; See also regarding claim 1.).
Claim(s) 7-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Patil et al. ( US 20210351145 A1) in view of BHATTACHERJEE et al. (WO 2021173205 A1) in view of Hsu et al. (US 8476735 B2) in view of Viswanathan et al. (US 20140070397 A1) in view of Reigngruber et al. (US 10651102 B2).
Claim 7. Patil in view of BHATTACHERJEE et al. in view of Hsu et al. in view of Viswanathan discloses a package of claim 1, however may be silent upon the capability of wherein the printed circuit board defines a cavity, wherein the interposer is disposed in the cavity. At the time of the invention, it was known in the art that PCB substrates may have a recessed shape such that a interposer may be recessed within a cavity. See Reigngruber et al. entire document. It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the PCB of Patil with a PCB having a cavity/recess as taught by Reigngruber, since simple substitution of one known element for another to obtain predictable results is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
Claim 8. Patil in view of Hsu et al. in view of Viswanathan in view of Reigngruber discloses a package of claim 1, wherein the die is coupled to the pad by an interconnect (Patil et al. Figs. 3-11; See also regarding claim 1.).
Claim 9. Patil in view of BHATTACHERJEE et al. in view of Hsu et al. in view of Viswanathan in view of Reigngruber discloses a package of claim 1, wherein the package comprises a radio frequency module (Patil et al. ¶61).
Claim 10. Patil in view of BHATTACHERJEE et al. in view of Hsu et al. in view of Viswanathan in view of Reigngruber discloses a interposer 301 comprising: a substrate including at least one via 272; a multilayer structure 200/301 disposed above the substrate, the multilayer structure including a top layer with an array including a plurality of passive devices integrated into at least one of the substrate or a dielectric of the multilayer structure, wherein the at least one via couples the plurality of passive devices 210/212/216 to a first pad disposed on a bottom of the substrate by which the interposer is configured to couple to a printed circuit board 282-288; the plurality of passive devices 210/212/216 being positioned beneath the die 304 coupled to the interposer 200 (Patil, Fig. 3); and a trace 242 UBM Trace disposed above the multilayer structure and connecting at least one passive device of the plurality of passive devices to a second pad 242 242 UBM Trace disposed above the multilayer structure by which the interposer is configured to couple to a die 304; wherein the array includes a property defined by the at least one passive device connected to the trace (Patil et al. Figs. 3-11; See also regarding claim 1. Note, the limitation regarding a property to define the passive device does not provide any clear structural distinction.).
Patil may however be silent upon the implied structural limitation of wherein the interposer is configured to enable mask-based adjustment of the trace connecting the passive devices, by changing a top mask of the interposer, for iterative tuning of the die to improve radio frequency (RF) performance. At the time of the invention, advanced interposers were known and capable of being modified/tuned. Such interposes are disclosed in BHATTACHERJEE et al. paragraph 51, which teaches interposers for which die and chips are or will be attached may be modified and/or tuned. Such interposers further include traces and passive devices for RF circuits that are part of the interposer.
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Further as specified in Hsu et al., the passive devices of a interposer may be connected and unconnected for the purpose of post manufacture-tuning. See Claims 1, 7 and 11 of Hsu for a direct explicit and concise teaching. In the Hsu document, the analogous device structure as claimed is disclosed. Hsu teaches:
a printed circuit board 50 (Col. 8 ln 60+ interpose may on a PCB during post manufacture tuning.);
an interposer 100 coupled to the printed circuit board 50 (Hsu, Abstract [interposer] & Col. 8 – interposer may be on a package substrate such as a PCB), the interposer including:
a substrate 130 including at least one via (Hsu figs. 4-9B- all embodiments demonstrate the inclusion of at least one via. See fig. 5, element 143 for a example.);
a multilayer 135 structure disposed above the substrate, the multilayer structure including a top layer with an array including a plurality of passive devices integrated into at least one of the substrate or a dielectric of the multilayer structure (Hsu Abstract), wherein the at least one via couples the plurality of passive devices to the printed circuit board (Hsu figs. 4-9B- all embodiments demonstrate the inclusion of at least one via. See fig. 5, element 143 for a example. The purposes of a VIA is to provide electrical connection thought a device and or layer to another level.);
a trace 105a/215/243 disposed above the multilayer structure and connecting at least one passive device of the plurality of passive devices to a pad disposed above the multilayer structure; the array including a property defined by the at least one passive device which is connected to the trace (Hsu- Col. 10 & Figs. 7B 8a-9B – trace and trace pads are used to selectively connect passive devices of the interposer.); and
a die coupled to the pad, the plurality of passive devices being positioned beneath the die (Hsu figs. 10C & 12A-C);
wherein the interposer is configured to enable mask-based adjustment of the trace connecting the passive devices, by changing a top mask of the interposer, for iterative tuning of the die to improve radio frequency (RF) performance (Hsu, Figs. 7A-7C & Col. 9),
the interposer comprising one or more passive devices integrated into the interposer and unconnected to the trace,the one more passive devices being configured to adjust an RF response of the die (Hsu – Abstract & claims 1, 7 & 11).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the interposer of Patil with “tunable” interposer of BHATTACHERJEE et al. and/or Hsu et al, since applying a known technique (mask tunable) to a known device ready for improvement (a interposer comprising RF passive circuity) to yield predictable results (lower cost being able to tune the interposer as needed) is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
Regarding the further limitation of “the one or more passive devices being configured in series or parallel relative to one another to provide a predetermined resistance or capacitance value allowed by the trace connecting the one or more passive devices, the plurality of passive devise comprising a first set of device and a second set of devices, the first set of devices being coupled to the trace and the second set of devices being unconnected to the trace, the second set of devices being provided to adjust resistance or capacitance of the plurality of passive devices in an additional mask fabrication without refabricating an underlying layer,” this language fails to provide any meaningful structural distinction over the prior art teachings of Hsu. It is a fundamental principle of RF circuitry that passive devices (resistors, capacitors, inductors) must be configured in series or parallel to achieve specific electrical characteristics. Because Hsu explicitly teaches the presence of these devices on an interposer, the claimed configurations are not just suggested; they are necessitated by the functional requirements of the circuit. The use of a “first set” (connected) and “second set” (unconnected) of devices is a textbook method for post-manufacture tuning, as shown in Fig. 3 of Hsu. A PHOSITA would understand that providing extra, unconnected components is a routine design choice to allow for resistance of capacitance adjustments via mask fabrication. Such tuning naturally results in a device where some components are coupled to the trace and others remain isolated. Therefore, the claimed arrangement is nothing more than the predictable result of applying standard tuning techniques to the structures already disclosed by Hsu2 [Fig. 3].
Claim 11. Patil in view of BHATTACHERJEE et al. in view of Hsu et al. in view of Viswanathan in view of Reigngruber discloses a interposer of claim 10, wherein the array further comprises at least one additional passive device which is not connected to the second pad by the trace (Patil et al. Figs. 3-11; See also regarding claim 1.).wherein the property of the array is adjustable by connecting the at least one passive device with the at least one additional passive device by the trace for tuning the die (This limitation is not understood to provide any further structural distinction, as it is a statement of intended use.).
Claim 12. Patil in view of BHATTACHERJEE et al. in view of Hsu et al. in view of Viswanathan in view of Reigngruber discloses a interposer of claim 10, further comprising a through via and an additional trace disposed above the multilayer structure; wherein the array includes at least one additional passive device which is not connected to the second pad disposed above the multilayer structure by the trace; wherein the additional trace connects the through via and the at least one additional passive device; wherein the through via is connected to the first pad disposed on the bottom of the substrate (Patil et al. Figs. 3-11; See also regarding claim 1.).
Claim(s) 13-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Patil et al. ( US 20210351145 A1) in view of BHATTACHERJEE et al. (WO 2021173205 A1) in view of Hsu et al. (US 8476735 B2) in view of Viswanathan et al. (US 20140070397 A1) in view of Reigngruber et al. (US 10651102 B2) in view of Gandhi et al. (US 20210366873 A1).
Claim 13. Patil in view of BHATTACHERJEE et al. in view of Hsu et al. in view of Viswanathan in view of Reigngruber discloses a interposer of claim 10, however may be silent upon when wherein the substrate is one of a silicon substrate or a glass substrate. At the invention silicon and glass substrates were known to be included in interposer structures. For support see Gandhi et al which teaches a multilevel interposer having passive devices and a bottom substrate being of silicon and including TSVs for mounting on a PCB. One of ordinary skill in the art would select glass or silicon as opposed to the encapsulant material as disclosed in Patil for the conventionally recognized benefit of added rigidity if needed.
When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill in the art has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co v. Teleflex Inc.
Claim 14. Patil in view of BHATTACHERJEE et al. in view of Hsu et al. in view of Viswanathan in view of Reigngruber in view of Gandhi discloses a interposer of claim 10, wherein the property of the array is a resistance, wherein the at least one passive device includes a thin-film resistor (Patil et al. Figs. 3-11; Patil ¶61 – resistors, capacitors, and inductors).
Claim 15. Patil in view of BHATTACHERJEE et al. in view of Hsu et al. in view of Viswanathan in view of Reigngruber in view of Gandhi discloses a interposer of claim 10, wherein the property of the array is a capacitance, wherein the at least one passive device includes a metal-insulator-metal capacitor integrated into the dielectric or a deep trench capacitor integrated into the substrate (Patil et al. Figs. 3-11; Patil ¶61 – resistors, capacitors, and inductors).
Claim 16. Patil in view of BHATTACHERJEE et al. in view of Hsu et al. in view of Viswanathan in view of Reigngruber in view of Gandhi discloses a interposer of claim 10, wherein the property of the array is an inductance, wherein the at least one passive device includes an inducto (Patil et al. Figs. 3-11; Patil ¶61 – resistors, capacitors, and inductors).
Claim 17. Patil in view of BHATTACHERJEE et al. in view of Hsu et al. in view of Viswanathan in view of Reigngruber in view of Gandhi discloses a interposer of claim 10, wherein the substrate further comprises one or more additional passive components (Patil et al. Figs. 3-11; Patil ¶61 – resistors, capacitors, and inductors).
Claim 18. Patil in view of BHATTACHERJEE et al. in view of Hsu et al. in view of Viswanathan in view of Reigngruber in view of Gandhi discloses a interposer of claim 17, wherein the one or more additional passive components include a deep trench capacitor (Gandhi ¶59 – deep trench capacitors are common passive devices used in RF components of integrated interposers..
Claim 19. Patil in view of BHATTACHERJEE et al. in view of Hsu et al. in view of Viswanathan in view of Reigngruber in view of Gandhi discloses a communication device comprising: a motherboard; and a radio frequency module including: a printed circuit board coupled to the motherboard; an interposer coupled to the printed circuit board, the interposer including: a substrate including at least one via; a multilayer structure disposed above the substrate, the multilayer structure including a top layer with an array including a plurality of passive devices integrated into at least one of the substrate or a dielectric of the multilayer structure, wherein the at least one via couples the plurality of passive devices to the printed circuit board; and a trace disposed above the multilayer structure and connecting at least one passive device of the plurality of passive devices to a pad disposed above the multilayer structure; the array including a property defined by the passive device which is connected to the trace; and a die coupled to the trace (Patil et al. Figs. 3-11; See also regarding claim 1.); the plurality of passive devices 210/212/216 being positioned beneath the die 304 coupled to the interposer 200 (Patil, Fig. 3);
Patil may however be silent upon the implied structural limitation of wherein the interposer is configured to enable mask-based adjustment of the trace connecting the passive devices, by changing a top mask of the interposer, for iterative tuning of the die to improve radio frequency (RF) performance. At the time of the invention, advanced interposers were known and capable of being modified/tuned. Such interposes are disclosed in BHATTACHERJEE et al. paragraph 51, which teaches interposers for which die and chips are or will be attached may be modified and/or tuned. Such interposers further include traces and passive devices for RF circuits that are part of the interposer.
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Further as specified in Hsu et al., the passive devices of a interposer may be connected and unconnected for the purpose of post manufacture-tuning. See Claims 1, 7 and 11 of Hsu for a direct explicit and concise teaching. In the Hsu document, the analogous device structure as claimed is disclosed. Hsu teaches:
a printed circuit board 50 (Col. 8 ln 60+ interpose may on a PCB during post manufacture tuning.);
an interposer 100 coupled to the printed circuit board 50 (Hsu, Abstract [interposer] & Col. 8 – interposer may be on a package substrate such as a PCB), the interposer including:
a substrate 130 including at least one via (Hsu figs. 4-9B- all embodiments demonstrate the inclusion of at least one via. See fig. 5, element 143 for a example.);
a multilayer 135 structure disposed above the substrate, the multilayer structure including a top layer with an array including a plurality of passive devices integrated into at least one of the substrate or a dielectric of the multilayer structure (Hsu Abstract), wherein the at least one via couples the plurality of passive devices to the printed circuit board (Hsu figs. 4-9B- all embodiments demonstrate the inclusion of at least one via. See fig. 5, element 143 for a example. The purposes of a VIA is to provide electrical connection thought a device and or layer to another level.);
a trace 105a/215/243 disposed above the multilayer structure and connecting at least one passive device of the plurality of passive devices to a pad disposed above the multilayer structure; the array including a property defined by the at least one passive device which is connected to the trace (Hsu- Col. 10 & Figs. 7B 8a-9B – trace and trace pads are used to selectively connect passive devices of the interposer.); and
a die coupled to the pad, the plurality of passive devices being positioned beneath the die (Hsu figs. 10C & 12A-C);
wherein the interposer is configured to enable mask-based adjustment of the trace connecting the passive devices, by changing a top mask of the interposer, for iterative tuning of the die to improve radio frequency (RF) performance (Hsu, Figs. 7A-7C & Col. 9),
the interposer comprising one or more passive devices integrated into the interposer and unconnected to the trace, the one more passive devices being configured to adjust an RF response of the die (Hsu – Abstract & claims 1, 7 & 11).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the interposer of Patil with “tunable” interposer of BHATTACHERJEE et al. and/or Hsu et al, since applying a known technique (mask tunable) to a known device ready for improvement (a interposer comprising RF passive circuity) to yield predictable results (lower cost being able to tune the interposer as needed) is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
Regarding the further limitation of “the one or more passive devices being configured in series or parallel relative to one another to provide a predetermined resistance or capacitance value allowed by the trace connecting the one or more passive devices, the plurality of passive devise comprising a first set of device and a second set of devices, the first set of devices being coupled to the trace and the second set of devices being unconnected to the trace, the second set of devices being provided to adjust resistance or capacitance of the plurality of passive devices in an additional mask fabrication without refabricating an underlying layer,” this language fails to provide any meaningful structural distinction over the prior art teachings of Hsu. It is a fundamental principle of RF circuitry that passive devices (resistors, capacitors, inductors) must be configured in series or parallel to achieve specific electrical characteristics. Because Hsu explicitly teaches the presence of these devices on an interposer, the claimed configurations are not just suggested; they are necessitated by the functional requirements of the circuit. The use of a “first set” (connected) and “second set” (unconnected) of devices is a textbook method for post-manufacture tuning, as shown in Fig. 3 of Hsu. A PHOSITA would understand that providing extra, unconnected components is a routine design choice to allow for resistance of capacitance adjustments via mask fabrication. Such tuning naturally results in a device where some components are coupled to the trace and others remain isolated. Therefore, the claimed arrangement is nothing more than the predictable result of applying standard tuning techniques to the structures already disclosed by Hsu3 [Fig. 3].
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Claim 20. Patil in view of BHATTACHERJEE et al. in view of Hsu et al. in view of Viswanathan in view of Reigngruber in view of Gandhi discloses a communication device of claim 19, wherein the die is configured to at least one of filter a radio frequency signal of the motherboard or amplify a power of the radio frequency signal (Patil et al. Figs. 3-11; See also regarding claim 1.).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
3/2/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
1 Hsu – “When a desired interposer specification (such as circuit functions, devices parameters, interposer type) is obtained after the development stage, the integrated circuit product enters mass production phase. A customer can coordinate with an interposer vendor, a circuit die manufacturer (e.g. foundry) and an assembly site to produce packaged products in large scale. For example, after an integrated circuit is designed and prototype circuit die is evaluated at the system level on an evaluation board, an integrated circuit layout database is finalized and interposer parameters are decided upon. The circuit layout database is sent to a semiconductor manufacturing facility (FAB) for mass production. Wafers produced from a FAB are shipped to an assembly site for packaging. In selecting an interposer that provides, for instance, RF functions to said integrated circuit product, a customer may send an interposer specification to an independent interposer vendor and specify that "custom mask" is the scheme to be used for interposer manufacturing. The customer may then select, from a pre-developed, base array interposer library, a desired base array interposer layout database and design a custom mask/masks for device interconnections. The fully developed interposer layout database (with custom mask/masks) may be manufactured by the interposer vendor, for example, and finished interposers may be sent to said assembly site for packaging. At the assembly site, a customer may choose the proper packaging scheme matching the integrate circuit die and silicon interposer, to achieve desired circuit performance. The described customer-driven packaging flow is illustrated in FIG. 11.”
2 Hsu – “When a desired interposer specification (such as circuit functions, devices parameters, interposer type) is obtained after the development stage, the integrated circuit product enters mass production phase. A customer can coordinate with an interposer vendor, a circuit die manufacturer (e.g. foundry) and an assembly site to produce packaged products in large scale. For example, after an integrated circuit is designed and prototype circuit die is evaluated at the system level on an evaluation board, an integrated circuit layout database is finalized and interposer parameters are decided upon. The circuit layout database is sent to a semiconductor manufacturing facility (FAB) for mass production. Wafers produced from a FAB are shipped to an assembly site for packaging. In selecting an interposer that provides, for instance, RF functions to said integrated circuit product, a customer may send an interposer specification to an independent interposer vendor and specify that "custom mask" is the scheme to be used for interposer manufacturing. The customer may then select, from a pre-developed, base array interposer library, a desired base array interposer layout database and design a custom mask/masks for device interconnections. The fully developed interposer layout database (with custom mask/masks) may be manufactured by the interposer vendor, for example, and finished interposers may be sent to said assembly site for packaging. At the assembly site, a customer may choose the proper packaging scheme matching the integrate circuit die and silicon interposer, to achieve desired circuit performance. The described customer-driven packaging flow is illustrated in FIG. 11.”
3 Hsu – “When a desired interposer specification (such as circuit functions, devices parameters, interposer type) is obtained after the development stage, the integrated circuit product enters mass production phase. A customer can coordinate with an interposer vendor, a circuit die manufacturer (e.g. foundry) and an assembly site to produce packaged products in large scale. For example, after an integrated circuit is designed and prototype circuit die is evaluated at the system level on an evaluation board, an integrated circuit layout database is finalized and interposer parameters are decided upon. The circuit layout database is sent to a semiconductor manufacturing facility (FAB) for mass production. Wafers produced from a FAB are shipped to an assembly site for packaging. In selecting an interposer that provides, for instance, RF functions to said integrated circuit product, a customer may send an interposer specification to an independent interposer vendor and specify that "custom mask" is the scheme to be used for interposer manufacturing. The customer may then select, from a pre-developed, base array interposer library, a desired base array interposer layout database and design a custom mask/masks for device interconnections. The fully developed interposer layout database (with custom mask/masks) may be manufactured by the interposer vendor, for example, and finished interposers may be sent to said assembly site for packaging. At the assembly site, a customer may choose the proper packaging scheme matching the integrate circuit die and silicon interposer, to achieve desired circuit performance. The described customer-driven packaging flow is illustrated in FIG. 11.”