Prosecution Insights
Last updated: August 30, 2026
Application No. 17/726,990

PRINTED CIRCUIT BOARD WITH EMBEDDED BUMP PADS

Final Rejection §102
Filed
Apr 22, 2022
Examiner
BURNS, TREMESHA WILLIS
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SanDisk Technologies Inc.
OA Round
6 (Final)
78%
Grant Probability
Favorable
7-8
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
695 granted / 890 resolved
+10.1% vs TC avg
Strong +17% interview lift
Without
With
+17.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
50 currently pending
Career history
938
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
33.6%
-6.4% vs TC avg
§102
46.5%
+6.5% vs TC avg
§112
18.2%
-21.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 890 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment Applicant's arguments with respect to claims 1 – 6, 16 – 19, 21 – 25, and 28 - 32 have been considered but are moot in view of the new ground(s) of rejection. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 – 6, 16 – 19, 21 – 25, and 28 - 32 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shih (U.S. Patent No. 9,922,845). Regarding claim 1, in Figure 20 (with Figure 20 being upside down), Shih discloses a printed circuit board, comprising: a bump pad layer (21) comprising a unitary bump pad (322) embedded in a first dielectric material (21), the unitary bump pad being a single, integrally-formed conductive structure, a first portion of the unitary bump pad extending above a first surface of the first dielectric material and operable to receive a solder ball (622) and a second portion of the unitary bump pad being embedded within the first dielectric material and having a bottom surface that is substantially planar with respect to a second surface of the first dielectric material (Figure 20); and a trace metal layer (201) separate from the bump pad layer (layer 21, 322 is adjacent to pads 204, but are separate layers; see Figure 10 of the claimed invention in which bump pad layer 410 is adjacent to trace metal layer 710), the trace metal layer comprising a trace (204) plated on the bottom surface of the second portion of the unitary bump pad, the trace metal layer being embedded in a second dielectric material (201). Regarding claim 2, Shih discloses wherein the first portion of the bump pad is adapted to electrically couple to a pillar of an electronic component mounted on the printed circuit board (Figure 20). Regarding claim 3, Shih discloses wherein the bump pad layer prevents a solder bridge from forming between connection points on the printed circuit board when an electronic component is mounted on the printed circuit board (Figure 20). Regarding claim 4, Shih discloses wherein the bump pad layer prevents solder non-wetting between the bump pad in the bump pad layer and the solder ball when an electronic component is mounted on the printed circuit board (Figure 20). Regarding claim 5, Shih discloses wherein the bump pad extends approximately ten micrometers or less above the first surface of the first dielectric material (Figure 20). Regarding claim 6, Shih discloses wherein the bump pad layer substantially covers the trace metal layer (Figure 20). Regarding claim 16, in Figure 20 (with Figure 20 being upside down), Shih discloses a printed circuit board, comprising: a bump pad layer (21) comprising a connection means (322) embedded in an etched dielectric material (21), the connection means being a single, integrally-formed conductive structure, the etched dielectric material having a thickness that is less than a thickness of the connection means such that a first portion of the connection means extends above a surface of the etched dielectric material (Figure 20) and is operable to receive a coupling means (622) and wherein a second portion of the connection means is embedded within the etched dielectric material and has a bottom surface that is substantially planar with respect to a second surface of the etched dielectric material (Figure 20); and a trace metal layer (201) separate from the bump pad layer (layer 21, 322 is adjacent to pads 204, but are separate layers; see Figure 10 of the claimed invention in which bump pad layer 410 is adjacent to trace metal layer 710) and comprising a signal transmission means (204) embedded in a second dielectric material (201) wherein the signal transmission means is electrically coupled to the bottom surface of the second portion of the connection means (Figure 20). Regarding claim 17, Shih discloses wherein the first portion of the connection means extends approximately ten micrometers or less above the surface of the etched dielectric material (Figure 20). Regarding claim 18, Shih discloses wherein the signal transmission means is plated on the bottom surface of the second portion of the first connection means (Figure 20). Regarding claim 19, Shih discloses wherein the bump pad layer substantially covers the trace metal layer (Figure 20). Regarding claim 21, Shih discloses wherein the connection means prevents non-wetting between the connection means and the coupling means when an electronic component is mounted on the printed circuit board (Figure 20). Regarding claim 22, Shih discloses wherein the connection means prevents a bridge from forming between adjacent connection means on the printed circuit board when an electronic component is mounted on the printed circuit board (Figure 20). Regarding claim 23, in Figure 20 (with Figure 20 being upside down), Shih discloses a printed circuit board, comprising: a first layer (21) comprising: a first dielectric material (21) etched to a first height; and a unitary bump pad (322) embedded in and extending through the first dielectric material, the unitary bump pad being a single, integrally-formed conductive structure and having a second height that is greater than the first height (Figure 20), such that: a first portion of the unitary bump pad extends above a first surface of the first dielectric material; and is operable to receive a bonding material (622); and a second portion of the unitary bump pad is embedded in the first dielectric material such that a bottom surface of the second portion of the unitary bump pad is planar with respect to a second surface of the first dielectric material (Figure 20); and a second layer (201) comprising: a second dielectric material (201); and a trace (204) embedded in the second dielectric material and directly coupled to the bottom surface of the second portion of the unitary bump pad (Figure 20). Regarding claim 24, Shih discloses wherein the first portion of the unitary bump pad is electrically coupleable to a pillar of an electronic component (Figure 20). Regarding claim 25, Shih discloses wherein the trace is plated to the bottom surface of the second portion of the unitary bump pad (Figure 20). Regarding claim 28, Shih discloses wherein the unitary bump pad prevents solder non-wetting between the unitary bump pad and the bonding material when an electronic component is mounted on the printed circuit board (Figure 20). Regarding claim 29, Shih discloses wherein the unitary bump pad prevents a bridge from forming between adjacent connection points on the printed circuit board when an electronic component is mounted on the printed circuit board (Figure 20). Regarding claim 30, Shih discloses wherein the second layer extends substantially along the first layer (Figure 20). Regarding claim 31, Shih discloses wherein the first portion of the unitary bump pad and the second portion of the unitary bump pad are plated as a single, unitary structure (Figure 20). Regarding claim 32, Shih discloses wherein the connection means is a unitary structure (Figure 20). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. TREMESHA W. BURNS Primary Examiner Art Unit 2847 /TREMESHA W BURNS/Primary Examiner, Art Unit 2847
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Prosecution Timeline

Show 13 earlier events
Jun 04, 2025
Response Filed
Sep 10, 2025
Final Rejection mailed — §102
Dec 04, 2025
Response after Non-Final Action
Dec 23, 2025
Request for Continued Examination
Jan 16, 2026
Response after Non-Final Action
Jan 28, 2026
Non-Final Rejection mailed — §102
Apr 28, 2026
Response Filed
Jul 16, 2026
Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

7-8
Expected OA Rounds
78%
Grant Probability
95%
With Interview (+17.3%)
2y 6m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 890 resolved cases by this examiner. Grant probability derived from career allowance rate.

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