DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous action: claims 1 through 16 rejected, claims 17 through 20 non-elected
Present action: claims 1 through 11 and 14 through 16 rejected, claim 12 canceled, claims 17 through 20 non-elected.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10, 11, 13, 14, 15, and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation "the first plurality of dies" in line 8. There is insufficient antecedent basis for this limitation in the claim.
Claim 10 recites the limitation "the second plurality of dies" in line 10. There is insufficient antecedent basis for this limitation in the claim.
Claims 11, 13, 14, 15, and 16 depend from and incorporate claim 10.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 4, 5, 6, and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2019/0355637) in view of Chen (US 2020/0402960).
Regarding claim 1.
Chen (637) a microelectronic assembly, comprising: a stack of layers comprising dies (fig 2,8d:201; [para 0023]), adjacent layers being coupled by at least fusion bonds (fig 8c; [para 0059]); a package substrate (fig 2,8d:101; [para 0023]) coupled to a first layer (fig 2:2034,1134; [para 0023]) in the stack of layers (fig 2:201; [para 0023]); one or more dummy dies (fig 2,8d:2034; [para 0023]) and one or more integrated circuit (IC) dies (fig 2,8d:1134; [para 0023]) in the first layer (fig 2:2034,1134; [para 0023]);
and one or more dummy dies (fig 2:2033; [para 0023]) and one or more IC dies (fig 2:1133; [para 0023]) in a second layer in the stack of layers (fig 2,8d:201; [para 0023]), the one or more IC dies (fig 2:1133; [para 0023]) of the second layer coupled to the one or more IC dies (fig 2,8d:1134; [para 0023]) of the first layer by metal-to-metal bonds (fig 7e; [para 0050,0028]), […].
Chen (637) does not teach a copper lining.
Chen (960)a copper lining (fig 20:60a; [para 0087,0088]) is between adjacent surfaces (fig 20:100s; [para 0087]) of any two adjacent dies (fig 20,21:60a; [para 0087]) in at least one of the first layer (fig 20:10a(1); [para 0087]) and the second layer (fig 20:10a(2); [para 0087]), and the copper lining (fig 20:60a; [para 0087,0088]) contacts and substantially covers the adjacent surfaces (fig 20:100s; [para 0087]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a copper layer on the surfaces in order to provide shielding from electromagnetic interference (Chen [para 0088])
Regarding claim 3.
Chen (637) in view of Chen (690) teaches the microelectronic assembly of claim 1, further:
Chen (637) teaches the fusion bonds comprise oxide (fig 7d,7e:7031; [para 0032,0049]) – oxide (fig 7d,7e:501; [para 0032,0034]) bonds.
Regarding claim 4.
Chen (637) in view of Chen (690) teaches the microelectronic assembly of claim 1, further:
Chen (637) teaches the dummy dies are one of: semiconductor dies without any ICs, and semiconductor dies (fig 2,8d:2031-2034; [para 0023]) having non-functional ICs, and the IC dies (fig 2,8d:1131-1134; [para 0023]) comprise semiconductor dies having functional ICs.
Regarding claim 5
Chen (637) in view of Chen (690) teaches the microelectronic assembly of claim 4, further:
Chen (637) teaches each of the IC dies (fig 2,8d:1131-1134; [para 0023]) comprises a substrate (fig 4b:405; [para 0027]) and a metallization stack (fig 4b:407; [para 0027]), an active region (fig 4b; [para 0029]) is between the substrate (fig 4b:405; [para 0027]) and the metallization stack (fig 4b:407; [para 0027]), the metallization stack (fig 4b:407; [para 0027]) comprises a plurality of layers of interlayer dielectric (ILD) material (fig 4b:411; [para 0030]) and conductive traces (fig 4b:413; [para 0030]) connected by conductive vias (fig 4b:413; [para 0030]) through the ILD material (fig 4b:411; [para 0030]).
Regarding claim 6
Chen (637) in view of Chen (690) teaches the microelectronic assembly of claim 4, further:
Chen (637) teaches a subset of the dummy dies (fig 2,8d:2031-2034; [para 0023,0065]) is proximate to a peripheral region of the microelectronic assembly (annotated figure below).
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Regarding claim 7
Chen (637) in view of Chen (690) teaches the microelectronic assembly of claim 6, further:
Chen (637) teaches another subset of the dummy dies (fig 2,8d:2031-2034; [para 0023,0065]) is in a medial region of the microelectronic assembly (annotated figure above).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2019/0355637) in view of Chen (US 2020/0402960) as applied to claim 1 and further in view of Lee (US 2017/0025361)
Regarding claim 2.
Chen (637) in view of Chen (960) teaches the microelectronic assembly of claim 1.
Chen (637) in view of Chen (960) does not teach the thickness of the copper layer,
Lee teaches a copper lining that is approximately 10 microns wide (fig 5; [para 0045]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the copper lining 10 microns wide in order to provide a sufficient electromagnetic shield (paragraph 6).
Further, given the teaching of the references, it would have been obvious to determine the optimum lining thicknesses. See In re Aller, Lacey and Hall (10 USPQ 233-237) It is not inventive to discover optimum or workable ranges by routine experimentation. Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575,1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2019/0355637) in view of Chen (US 2020/0402960) as applied to claim 7 and further in view of Hsieh (US 2022/0285289)
Regarding claim 8.
Chen (637) in view of Chen (960) teaches the microelectronic assembly of claim 7.
Chen (637) in view of Chen (960) does not teach the spacing between die.
Hsieh teaches the dummy dies (fig 3b:1320a; [para 0041]) in the another subset are located between two IC dies (fig 3b:1200a,c; [para 0041]) that are spaced (fig 3b:G1; [para 0041]) at least 500 micrometers apart (fig 3b; [para 0041]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to place dummy die in spaces between stacks of die in order to minimize vacancy space and thereby reduce warpage (paragraph 44).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2019/0355637) in view of Chen (US 2020/0402960) as applied to claim 1 and further in view of Teshiba (US 2018/0175476)
Regarding claim 9.
Chen (637) in view of Chen (960) teaches the microelectronic assembly of claim 1.
Chen (637) teaches the metal-metal bonds (fig 7e; [para 0050,0028]) have a pitch between adjacent ones of the metal-metal bonds.
Chen (637) in view of Chen (960) does not teach the metal bond pitch.
Teshiba teaches metal-metal bonds (fig 4:412a,c; [para 0027]) have a pitch of less than 10 micrometers between adjacent ones of the metal-metal bonds (fig 4; [para 0027]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the metal bond pitch to be less than 10 microns in order to have a high connection density which will increase the amount of data that can be transferred between die.
Claim(s) 10, 11, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2019/0355637) in view of Chen (US 2020/0402960) in view of Yang (US 2022/0045034).
Regarding claim 10.
Chen (637) teaches an IC package, comprising: a first layer comprising a plurality of dies (fig 2,8d:1134,2034; [para 0023]) comprising one or more dummy dies (fig 2,8d:2034; [para 0023]) and one or more integrated circuit (IC) dies (fig 2,8d:1134; [para 0023]); a second layer comprising a plurality of dies (fig 2,8d:1133,2033; [para 0023]) comprising one or more dummy dies (fig 2,8d:2033; [para 0023]) and one or more integrated circuit (IC) dies (fig 2,8d:1133; [para 0023]), wherein the first and second layers are bonded […] by at least fusion bonds (fig 8c; [para 0059]) and the one or more IC dies (fig 2,8d:1134; [para 0023]) of the first layer are coupled to the one or more IC dies (fig 2,8d:1133; [para 0023]) of the second layer by metal-to-metal bonds (fig 7e; [para 0050,0028]); and a package substrate (fig 2,8d:101; [para 0023]) coupled to the first plurality of dies (fig 2,8d:1134,2034; [para 0023]), wherein: the first plurality of dies (fig 2,8d:1134,2034; [para 0023]) is between the second plurality of dies (fig 2,8d:1133,2033; [para 0023]) and the package substrate (fig 2,8d:101; [para 0023]), […].
Chen (637) does not teach a copper lining.
Chen (960) a copper lining (fig 20:60a; [para 0087,0088]) is between adjacent surfaces (fig 20:100s; [para 0087]) of any two adjacent dies (fig 20,21:60a; [para 0087]) in the first plurality of dies (fig 20:10a(1); [para 0087]) or the second plurality of dies (fig 20:10a(2); [para 0087]), and the copper lining (fig 20:60a; [para 0087,0088]) contacts and substantially covers the adjacent surfaces (fig 20:100s; [para 0087]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a copper layer on the surfaces in order to provide shielding from electromagnetic interference (Chen; [para 0088])
Chen (637) does not teach bonding die face to face.
Yang teaches an IC package comprising a plurality of die wherein the first (fig 1:116; [para 0026]) and second (fig 1:120; [para 0026]) layers are bonded face to face (fig 1; [para 0026])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to bond die face to face in order to enable more IO connections and thinner die (Yang; [para 0064]).
Regarding claim 11
Chen (637) in view of Chen (690) in view of Yang teaches the IC package of claim 10, further:
Chen (637) teaches the dummy dies (fig 2,8d:2031-2034; [para 0023]) are one of: semiconductor dies without any integrated circuits, and semiconductor dies having non-functional integrated circuits, and the IC dies (fig 2,8d:1131,1134; [para 0023]) comprise semiconductor dies with functional integrated circuits.
Regarding claim 14
Chen (637) in view of Chen (690) in view of Yang teaches the IC package of claim 10, further:
Chen (637) teaches more than one die (fig 2,8d:1131-1133; [para 0023]) in the second plurality of dies is coupled to one of the dies (fig 2,8d:1134; [para 0023]) in the first plurality of dies (fig 2,8d:1134,2034; [para 0023]).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2019/0355637) in view of Chen (US 2020/0402960) in view of Yang (US 2022/0045034) as applied to claim 11 and further in view of Yu (US 2021/0327778)
Regarding claim 13.
Chen (637) in view of Chen (960) in view of Yang teaches the IC package of claim 11.
Chen (637) in view of Chen (960) in view of Yang does not teach a first and a second subset of die bonded to one of the die.
Yu teaches a first subset in the second plurality of dies comprises IC dies (fig 12:68; [para 0019]), the IC dies in the first subset are coupled to a medial region of one of the dies in the first plurality of dies (fig 12:96; [para 0020]), a second subset in the second plurality of dies (fig 12:68; [para 0019]) comprises dummy dies (fig 12:106; [para 0038]) coupled to a peripheral region of the one of the dies in the first plurality of dies (fig 12:96; [para 0038]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to bond a dummy die and an ic die to a first ic die in order to provide a greater variability in die size and related die function in the stacked arrangement of die.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2019/0355637) in view of Chen (US 2020/0402960) in view of Yang (US 2022/0045034) as applied to claim 10 and further in view of Hsieh (US 2022/0285289) in view of Agarwal (US 2019/0189590)
Regarding claim 15.
Chen (637) in view of Chen (960) in view of Yang teaches the IC package of claim 10.
Chen (637) in view of Chen (960) in view of Yang does not teach the spacing between die.
Hsieh teaches dies in the first plurality of dies or the second plurality of dies and a dummy die (fig 3a,3b:1320A; [para 0041]) is located in any space (fig 3b:G1,G2; [para 0041]) larger than approximately 500 micrometers between adjacent IC dies.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to place dummy die in spaces in order to minimize vacancy space and thereby reduce warpage (paragraph 44).
Chen (637) in view of Chen (960) in view of Yang does not teach the spacing between the first plurality of dies or the second plurality of dies is less than 10 microns.
Agarwal teaches dies in the first plurality of dies (fig 2,6:265,280,22; [para 0036]) or the second plurality of dies are not more than [40] micrometers apart (para 0034])Given the teaching of the references, it would have been obvious to determine the optimum spacing of die to be not more than 10 microns. See In re Aller, Lacey and Hall (10 USPQ 233-237) It is not inventive to discover optimum or workable ranges by routine experimentation. Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575,1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to place dummy die in spaces in order to minimize vacancy space and thereby reduce warpage (paragraph 44).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2019/0355637) in view of Chen (US 2020/0402960) in view of Yang (US 2022/0045034) as applied to claim 10 and further in view of Doan (US 2005/0167799)
Regarding claim 16.
Chen (637) in view of Chen (960) in view of Yang teaches the IC package of claim 10.
Chen (960) teaches die (fig 20:10a: [para 0084]) in contact with the copper lining (fig 20:60; [para 0087])
Chen (637) in view of Chen (960) in view of Yang does not teach silicon nitride coating
Doan teach surfaces of the dies (fig 9:102; [para 0030]) have a coating (fig 9,10:130,142; [para 0029,0043]) of a compound comprising silicon and nitrogen ([para 0007])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the die with a coating of silicon nitride in order to seal the die from moisture and contamination (paragraph 7)
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 10 have been considered but are moot because the new ground of rejection does not rely on any reference combination applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Newly applied rejection over Chen (US 2019/0355637) in view of Chen (US 2020/0402960) anticipates the claim.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 March 13, 2026