Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The instant detailed action is in response to Applicant's submission filed on 17 October 2025.
REJECTIONS NOT BASED ON PRIOR ART
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1-24 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per MPEP 2173.03, “A claim, although clear on its face, may also be indefinite when a conflict or inconsistency between the claimed subject matter and the specification disclosure renders the scope of the claim uncertain as inconsistency with the specification disclosure or prior art teachings may make an otherwise definite claim take on an unreasonable degree of uncertainty. In re Moore, 439 F.2d 1232, 1235-36, 169 USPQ 236, 239 (CCPA 1971); In re Cohn, 438 F.2d 989, 169 USPQ 95 (CCPA 1971); In reHammack, 427 F.2d 1378, 166 USPQ 204 (CCPA 1970).“
Applicant previously argued Malina did not disclose the subject matter of claims 1, 9, and 17 because Malina is designed to use only the DSD that is indicated in the transport attribute (or an attribute of data) and not “an appropriate substitute” (see Appeal Brief Page 9). Claims 7,15, 23 recites wherein the first SSD personality type is different than the second SSD personality type. It is unclear how claims 7, 15, 23 are further limiting because according to the applicant’s pervious argument claims 1, 9, and 17 specify a first type different from a second type.
For purposes of examination, the first and second SSD personality type as recited in claims 1,9, and 17 have been interpreted to encompass the first type is same or different from the second type.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1,3-9,11-17,19-24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated Hayashida (US PG PUB No. 20180260135)
As per claim [1,9,17], a computer system comprising one or more processors having one or more circuits to:
provide a first memory application programming interface (API) corresponding to a first solid state device (SSD) personality type (see Hayashida FIG 3: 312 and [0030]:” Ethernet NIC 312 can be coupled to an Ethernet network and can communicate with an enterprise server or other computing system using an NVMe over Fabric protocol.”)
[Hayashida discloses NVMe comprises application programming interface (see Hayashida “[0005]: “One example is Non-Volatile Memory Express (NVMe), a logical device communications interface or protocol specifically developed for SSDs that provides parallel, multi-queue application program interface (API) over PCIe, for a local storage device directly connected to a computer through a PCIe bus, or over a switch fabric, for a remote storage device that is connected via a communications network, such as the Ethernet, using remote direct memory access (RDMA).”).]
select a second SSD personality type from a set of interface personality types supported by a set of solid state memory devices based (see Hayashida [0023]: “The properties will include, for example, memory type (e.g., eMLC NAND, TLC NAND, or NVRAM), capacity (e.g., 500 Gigabytes, 1K Gigabytes), interface type (e.g., PCIe, SATA), and protocol (e.g., NVMe, iSCSI).”), at least in part, on the first SSD personality type (see Hayashida FIG 2A: 218 and ; and [0025]: “Namespaces 252 and 254 associated with a TLC memory 244 of NVM device 234 and namespace 256 associated with a TLC memory 246 of NVM device 236 have capacities as defined by the user and are mapped to NVM devices 234 and 236, respectively, because, for example, the performance of a TLC NAND-type memory satisfies the defined performance (e.g., higher latency but lower cost).“)
[Hayashida discloses the namespace is configured with storage corresponding to the specified SSD personality type and further discloses temporarily substituting a different SSD personality type.]
in response to a request to interact with memory received via the first memory API, fulfil the request using a memory device from the set of solid state memory devices using the second SSD personality type (see Hayashida [0036]: “ For example, in one embodiment host computer 462 sends a RDMA write command to NVM device 428 and NIC 458 writes the data to low-latency NVRAM device 438. Thus the data is written to integrated drive 400 with low latency. At some later time host computer 462 sends a RDMA move command to NVM device 424 to move the data from NVM device 428 to NVM device 424.”).
As per claim [3,11,19], the computer system of claim 1,
wherein: the request to interact with memory is a memory allocation request; and the request to interact with memory is fulfilled by providing access to an amount of memory via the first memory interface SSD personality type (see Hayashida [0007]: “In one embodiment, the at least one user-defined memory parameter is one of a group consisting of a capacity, a quality of service level, an assured number of I/O operations per second, a bandwidth, a latency, and an endurance. In one embodiment, the controller is configured to create a namespace corresponding to a first set of memory addresses in the at least one solid state memory device of the first type and a second set of memory addresses in the at least one solid state memory device of the second type.”)
As per claim [4,12,20], the computer system of claim 1,
wherein the set of solid state memory devices includes memory devices having different erasure characteristics (see Hayashida [0023]: “ In creating the management rules for the memory devices, the controller also considers various characteristics of the memory devices including but not limited to latency (e.g., nanoseconds for NVRAM, tens of microseconds for NAND), endurance (e.g., one thousand program/erase cycles (P/E) for TLC, fifty thousand P/E for eMLC, and no limit for NVRAM), capacity versus cost (e.g., large for TLC, medium for eMLC, small for NVRAM), accessibility (e.g., block protocol for NAND, memory semantic for NVRAM), and addressable width (e.g. byte addressable for NVRAM, page addressable for NAND).”)
As per claim [5,13,21], the computer system of claim 1,
further comprising one or more circuits to select the memory device from the set of solid state memory devices for use based at least in part on an erasure characteristic of the memory device (see Hayashida [0007]: “In one embodiment, the at least one user-defined memory parameter is one of a group consisting of a capacity, a quality of service level, an assured number of I/O operations per second, a bandwidth, a latency, and an endurance. In one embodiment, the controller is configured to create a namespace corresponding to a first set of memory addresses in the at least one solid state memory device of the first type and a second set of memory addresses in the at least one solid state memory device of the second type.”).
As per claim [6,14,22], the computer system of claim 1,
wherein the request that identifies the first SSD personality type indicates a memory access pattern (see Hayashida [0023]: “ For example, in one embodiment, if the NVM devices include TLC NAND, eMLC NAND, and NVRAM devices, the controller uses at least the following heuristics to create the rules for managing the memory devices: frequently accessed (“hot”) data should not be stored in a TLC memory, infrequently accessed (“cold”) data should be stored in a TLC memory, frequently accessed data should be stored in an NVRAM memory or an SLC memory, byte addressable (i.e., less than a page) data should be buffered in an NVRAM memory, “cold” data stored in an eMLC memory should be moved to a TLC memory, data requiring high speed and low latency write performance should be stored in an SLC memory in preference to a MLC memory, and heavily read data may be replicated on a plurality of TLC NAND devices to increase parallelism.”).
As per claim [7,15,23], the computer system of claim 1,
wherein the first SSD personality type is different than the second SSD personality type (see Hayashida [0036]: “ For example, in one embodiment host computer 462 sends a RDMA write command to NVM device 428 and NIC 458 writes the data to low-latency NVRAM device 438. Thus the data is written to integrated drive 400 with low latency. At some later time host computer 462 sends a RDMA move command to NVM device 424 to move the data from NVM device 428 to NVM device 424.”).
As per claim [8,16,24], the computer system of claim 1,
wherein the first memory API is provided in response to a request that identifies the first SSD personality type (see Hayashida FIG 2A: 218 and [0024]).
[Creating a namespace having the received user-defined values for parameters is taken as providing the first memory API in response to a request.]
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2,10,18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hayashida (US PG PUB No. 20180260135), as applied to claim 1, 9, and 17 above and further in view of Curewitz (US PG PUB No. 20210081326)
As per claim [2, 10, 18], the computer system of claim 1,
However, Lee does not expressly disclose but in the same field of endeavor Curewitz discloses
wherein the computer system includes a software-programmable multi-core CPU (see e.g., Curewitz FIG 7: 602 and [0076]), a network interface (see Curewitz FIG 7: 608), and at least one acceleration engine (see Curewitz [0165]: “Processing device 602 can also be one or more special - purpose processing devices such as an application specific integrated circuit ( ASIC ) , a field pro grammable gate array ( FPGA ) , a digital signal processor ( DSP ) , network processor , or the like”).
It would have been obvious before the effective filing date of the invention to further implement a computer system including a processing device, network interface and digital signal processor as taught by Curewitz.
The suggestion/motivation for doing so would have been for the benefit of a machine that can operate in the capacity of a server or a client machine (see Curewitz [0162]).
Therefore it would have been obvious before the effective filing date of the invention to further implement a computer system as taught Curewitz for the benefit of a machine that can operate in the capacity of a server or a client machine to arrive at the invention as specified in the claims.
RESPONSE TO ARGUMENTS
1sT ARGUMENT:
As an initial matter, Applicant respectfully submits that the rejections of claims 25-27 are rendered moot in light of the cancellation of these claims. Applicant further submits that the rejections to claims 1-24 are rendered moot at least because the amended claims no longer recite "a first memory interface type" or a "second memory interface type," which the Office alleges is the unclear portion of the claim.
Examiner maintains the amendments do not resolve if claims 1, 9, and 17 are drawn to a first type that is different from the second type. Applicant previously argued the claims require a first type that is different from a second type. Examiner pointed out in the previous interview claims 7, 15 and 23 recite the first type is different from the second type and therefore it is unclear if Applicant intends claim 1, 9 and 17 to encompass a first type that is same or different as a second type.
CONCLUSION
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KALPIT PARIKH whose telephone number is (571)270-1173. The examiner can normally be reached MON THROUGH FRI 9:30 TO 6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KALPIT PARIKH/
Primary Examiner, Art Unit 2137
KALPIT . PARIKH
Primary Examiner
Art Unit 2137