DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment with respect to claims 1, 13 and 18 filed on 09/02/2025 have been fully considered for examination based on their merits. The previously presented claims 2-10, 14-17, and 19-22 have been considered. Claims 11-12 are canceled.
Response to Arguments
Applicant’s arguments, see Remarks, pages 7-11, filed 09/02/2025, with respect to the rejection(s) of claim(s) 1, 13, and 18 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of WU.
Regarding Claim 11. Applicant mentioned the independent claim 11 has been amended, see Remarks page 8, however, the Claim 11 is canceled in the claim amendment filed on 09/02/2025. Therefore, the Examiner respectfully point out this inconsistency for the clear record.
Regarding Independent Claims 1, 13 and 18. Applicant amended claims 1, 13 and 18, now recite, “wherein the first chip pad is connected to only the first bonding wire” and the Applicant further argued that the prior art CHOI showed multiple corresponding bonding wires are connected to each corresponding chip pad, therefore teaches away the feature claimed in the instant application. The Examiner agrees and thus the rejection as been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of WU. WU (US 20190081012 A1) teaches in Figure 1, a stack package (Fig. 1, chip packaging structure, [0018]) comprising: wherein the first chip pad (Fig. 1, 22) is connected to only the first bonding wire (Fig. 1, 302, metal wire). Therefore, the Examiner maintains the rejection of Claims 1, 13 and 18 based on the new grounds of art, WU.
The dependent claims have been treated in the similar manner as mentioned above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 13, 15, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over by Keun-ho CHOI (hereinafter CHOI), US 20150091168 A1, in view of Bilal Khalaf et al, (hereinafter KHALAF), US 20210074668 A1, and further in view of Baoquan Wu et al, (hereinafter WU), US 20190081012 A1.
Regarding Claim 1, CHOI teaches in Figure 4, a stack package (100a, multi-chip package) comprising:
a packaging substrate (110a);
a first bond finger (120a, bonding finger) disposed on the packaging substrate (110a), wherein the first bond finger includes a first portion and a second portion (120a, bonding finger, annotated Figure 4).
a chip stack disposed over the packaging substrate (110a), wherein the chip stack includes a second semiconductor chip (150) including a second chip pad (152) that is stacked over a first semiconductor chip (140) including a first chip pad (142);
a first bonding wire (160, first conductive wire) connecting the first chip pad (142) to the first portion of the first bond finger (120a, bonding finger, annotated Figure 4); and
a second bonding wire (162, second conductive wire) connecting the second chip pad (Fig. 4, 152) to the second portion of the first bond finger (120a, bonding finger, annotated Figure 4);
wherein the second portion of the first bond finger is closer to the chip stack than the first portion of the first bond finger (120a, bonding finger, annotated Figure 4).
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CHOI though teaches a stack package wherein the first and second bonding wires are connected to the bonding fingers that are spaced apart and may include bonding portion and body portion arranged in a zigzag pattern ([0059]), CHOI does not explicitly disclose the first bonding finger disposed over the packaging substrate, wherein the first bond finger includes a first portion and a second portion that are contiguous.
KHALAF teaches in Figure 1A, a stack package (100, electronic device), wherein the first bond finger (106) includes a first portion (122, first location) and a second portion (124, second location) that are contiguous (at a second location, 124 adjacent the first location, 122, [0033]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified CHOI to incorporate the teaching of KHALAF such that a stack package, wherein the first bond finger includes a first portion and a second portion that are contiguous. The adjacent arrangement of first and second locations such as 122 and 124, minimize the bond finger size while maximizing electrical current supplied to the semiconductor dies of an electronic device (100) package (KHALAF, [0030], [0042-0043]).
CHOI as modified by KHALAF does not explicitly disclose a stack package comprising: wherein the first chip pad is connected to only the first bonding wire.
WU teaches in Figure 1, a stack package (Fig. 1, chip packaging structure, [0018]) comprising: wherein the first chip pad (Fig. 1, 22) is connected to only the first bonding wire (Fig. 1, 302, metal wire).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified CHOI as modified by KHALAF to incorporate the teaching of WU such that a stack package, comprising: wherein the first chip pad is connected to only the first bonding wire, so that the metal wire is tangent to the upper surface of the package, that is the distance between the metal wire and upper surface of the package is short so that when the static electricity reaches the upper surface of the package and enters the package, the static electricity may quickly enter the metal wire at the tangent point where the metal wire is tangent to the upper surface of the package so as to be conducted out (WU, [0013]).
Regarding Claim 13, CHOI teaches in Figure 4, a stack package (100a, multi-chip package) comprising:
a second semiconductor chip (150) stacked over a first semiconductor chip (140) that is disposed over a packaging substrate (110a);
a first bond finger (120a, bonding finger, annotated Figure 4) disposed on the packaging substrate;
a first bonding wire (160, first conductive wire) connected between the first bond finger at a first position and a first chip pad (142) of the first semiconductor chip; and
a second bonding wire (162, second conductive wire) connected between the first bond finger at a second position and a second chip pad (Fig. 4, 152) of the second semiconductor chip, wherein the second position of the first bond finger is closer to the first semiconductor chip than the first position of the first bond finger;
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CHOI though teaches a stack package wherein the first and second bonding wires are connected to the bonding fingers that are spaced apart and may include bonding portion and body portion arranged in a zigzag pattern ([0059]), CHOI does not explicitly disclose the first bonding finger disposed over the packaging substrate, wherein the first bond finger includes a first portion and a second portion that are contiguous.
KHALAF teaches in Figure 1A, a stack package (100, electronic device), wherein the first bond finger (106) includes a first portion (122, first location) and a second portion (124, second location) that are contiguous (at a second location, 124 adjacent the first location, 122, [0033]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified CHOI to incorporate the teaching of KHALAF such that a stack package, wherein the first bond finger includes a first portion and a second portion that are contiguous. The adjacent arrangement of first and second locations such as 122 and 124, minimize the bond finger size while maximizing electrical current supplied to the semiconductor dies of an electronic device (100) package (KHALAF, [0030], [0042-0043]).
CHOI as modified by KHALAF does not explicitly disclose a stack package comprising: wherein the first chip pad is connected to only the first bonding wire.
WU teaches in Figure 1, a stack package (Fig. 1, chip packaging structure, [0018]) comprising: wherein the first chip pad (Fig. 1, 22) is connected to only the first bonding wire (Fig. 1, 302, metal wire).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified CHOI as modified by KHALAF to incorporate the teaching of WU such that a stack package, comprising: wherein the first chip pad is connected to only the first bonding wire, so that the metal wire is tangent to the upper surface of the package, that is the distance between the metal wire and upper surface of the package is short so that when the static electricity reaches the upper surface of the package and enters the package, the static electricity may quickly enter the metal wire at the tangent point where the metal wire is tangent to the upper surface of the package so as to be conducted out (WU, [0013]).
Regarding Claim 15, CHOI as modified by KHALAF and WU, CHOI further teaches in Figure 7, the stack package (100c, multi-chip package) of claim 13,
wherein the second semiconductor chip (150c) is offset-stacked (in a cross-sectional view) over the first semiconductor chip (140c).
The claim 1 (discussed above) relied upon Figure 4 for the 103 rejection, wherein the two chip stacks are shown with no “off-stacked” in a cross-sectional view. However, the Claim 3, dependent on Claim 1, requires a prior-art to demonstrate the semiconductor chips that are “off-stacked”. Therefore, Figure 7 from CHOI is cited in the above paragraph with the elements showing the “off-stacked” features of (150c) over (140c). Both Figures 1 and 7 are considered in one embodiment per the specification, wherein the multi-chip packages (100c) in Figure 7 may include the package substrate (110a) in Figure 4 or the package substrate (110b) in Figure 7 (CHOI, [0069]).
Regarding Claim 18, CHOI teaches in Figure 4, a stack package (100a, multi-chip package) comprising:
a second semiconductor chip (150) stacked over a first semiconductor chip (140) that is disposed over a packaging substrate (110a);
a first bond finger (120a, bonding finger) formed in a conductive pattern on the packaging substrate (110a);
a first bonding wire (160, first conductive wire) connected between the first bond finger at a first position (120a, bonding finger, annotated Figure 4) and a first chip pad (142) of the first semiconductor chip (140); and
a second bonding wire (162, second conductive wire) connected between the first bond finger at a second position (120a, bonding finger, annotated Figure 4) and a second chip pad (152) of the second semiconductor chip (150), wherein the second position of the first bond finger (120a, bonding finger, annotated Figure 4) is closer to the first semiconductor chip (140) than the first position of the first bond finger (120a, bonding finger, annotated Figure 4).
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CHOI though teaches a stack package wherein the first and second bonding wires are connected to the bonding fingers that are spaced apart and may include bonding portion and body portion arranged in a zigzag pattern ([0059]), CHOI does not explicitly disclose the first bonding finger disposed over the packaging substrate, wherein the first bond finger includes a first portion and a second portion that are contiguous.
KHALAF teaches in Figure 1A, a stack package (100, electronic device), wherein the first bond finger (106) includes a first portion (122, first location) and a second portion (124, second location) that are contiguous (at a second location, 124 adjacent the first location, 122, [0033]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified CHOI to incorporate the teaching of KHALAF such that a stack package, wherein the first bond finger includes a first portion and a second portion that are contiguous. The adjacent arrangement of first and second locations such as 122 and 124, minimize the bond finger size while maximizing electrical current supplied to the semiconductor dies of an electronic device (100) package (KHALAF, [0030], [0042-0043]).
CHOI as modified by KHALAF does not explicitly disclose a stack package comprising: wherein the first chip pad is connected to only the first bonding wire.
WU teaches in Figure 1, a stack package (Fig. 1, chip packaging structure, [0018]) comprising: wherein the first chip pad (Fig. 1, 22) is connected to only the first bonding wire (Fig. 1, 302, metal wire).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified CHOI as modified by KHALAF to incorporate the teaching of WU such that a stack package, comprising: wherein the first chip pad is connected to only the first bonding wire, so that the metal wire is tangent to the upper surface of the package, that is the distance between the metal wire and upper surface of the package is short so that when the static electricity reaches the upper surface of the package and enters the package, the static electricity may quickly enter the metal wire at the tangent point where the metal wire is tangent to the upper surface of the package so as to be conducted out (WU, [0013]).
Regarding Claim 20, CHOI as modified by KHALAF and WU, CHOI further teaches in Figure 7, the stack package (100c, multi-chip package) of claim 18.
wherein the second semiconductor chip (150c) is offset-stacked (in a cross-sectional view) over the first semiconductor chip (140c) in a step-like configuration ([0068]). The claim 1 (discussed above) relied upon Figure 4 for the 103 rejection, wherein the two chip stacks are shown with no “off-stacked” in a cross-sectional view. However, the Claim 3, dependent on Claim 1, requires a prior-art to demonstrate the semiconductor chips that are “off-stacked”. Therefore, Figure 7 from CHOI is cited in the above paragraph with the elements showing the “off-stacked” features of (150c) over (140c). Both Figures 1 and 7 are considered in one embodiment per the specification, wherein the multi-chip packages (100c) in Figure 7 may include the package substrate (110a) in Figure 4 or the package substrate (110b) in Figure 7 (CHOI, [0069]).
Claims 2, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over CHOI, in view of KHALAF, further in view of WU, and further in view of Tae-Gyu Kang (hereinafter KANG), US 20110024919 A1.
Regarding Claim 2, CHOI as modified by KHALAF and WU, CHOI further teaches in Figure 6, the stack package (100b, multi-chip package) of claim 1,
wherein the first bond finger (120b, bonding finger) extends in a horizontal direction (second direction) with respect to a side of the chip stack (150, second semiconductor chip).
CHOI as modified by KHALAF and WU does not explicitly disclose the stack package, wherein the first bond finger extends in a diagonal direction with respect to a side of the chip stack.
KANG teaches in Figure 3, the stack package (100, semiconductor package ) of claim 1, wherein the first bond finger (124, second bonding pad with 129, inclined side portion) extends in a diagonal direction (per the vocabulary.com, the synonym of “a diagonal direction” refers to slanting or inclined in direction or courses or position –neither parallel nor perpendicular nor right angled) with respect to a side of the chip stack (200, semiconductor chip) [annotated Figure 3].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have CHOI as modified by KHALAF and WU to incorporate the teachings of KANG such the first bond finger extends in a diagonal direction with respect to a side of the chip stack so that the inclined second bonding pad arrangement will facilitate for non-overlapping of adjacent bond wires with respect to other nearest bonding pads of stack package with respect to other nearest bonding pads. (KANG, Fig. 3, [0058-0060]).
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Regarding Claim 14, CHOI as modified by KHALAF and WU, CHOI further teaches in Figure 6, the stack package (100b, multi-chip package) of claim 13.
CHOI as modified by KHALAF and WU does not explicitly disclose the stack package, wherein the first bond finger extends in at an angle with respect to a side of the first semiconductor chip.
KANG teaches in Figure 3, the stack package (100, semiconductor package ) of claim 1, wherein the first bond finger (124, second bonding pad with 129, inclined side portion) extends in at an angle with respect to a side of the first semiconductor chip (200, semiconductor chip) [annotated Figure 3].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have CHOI as modified by KHALAF and WU to incorporate the teachings of KANG such the first bond finger extends in at an angle with respect to a side of the first semiconductor chip so that the inclined second bonding pad arrangement will facilitate for non-overlapping of adjacent bond wires with respect to other nearest bonding pads of stack package with respect to other nearest bonding pads. (KANG, Fig. 3, [0058-0060]).
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Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over CHOI, in view of KHALAF, further in view of WU, and further in view of Hye-jin Kim et. al (hereinafter KIM-1), US 20150001737 A1.
Regarding Claim 3, CHOI as modified by KHALAF and WU, CHOI further teaches in Figure 7, the stack package (100c, multi-chip package) of Claim 1, wherein the second semiconductor chip (150c) is offset-stacked (in a cross-sectional view) over the first semiconductor chip (140c) in a step-like configuration ([0068]). The claim 1 (discussed above) relied upon Figure 4 for the 103 rejection, wherein the two chip stacks are shown with no “off-stacked” in a cross-sectional view. However, the Claim 3, dependent on Claim 1, requires a prior-art to demonstrate the semiconductor chips that are “off-stacked”. Therefore, Figure 7 from CHOI is cited in the above paragraph with the elements showing the “off-stacked” features of (150c) over (140c). Both Figures 1 and 7 are considered in one embodiment per the specification, wherein the multi-chip packages (100c) in Figure 7 may include the package substrate (110a) in Figure 4 or the package substrate (110b) in Figure 7 (CHOI, [0069]).
CHOI as modified by KHALAF and WU does not explicitly disclose the stack package wherein the second semiconductor chip is offset-stacked over the first semiconductor chip by a certain distance along a direction in which a side of the chip stack closest to the first bond finger extends, in a plan view, such that the second chip pad is farther from the first chip pad.
KIM-1 teaches in Figure 6, the stack package (semiconductor package, [0025]), wherein the second chip (150, fifth semiconductor chip) is offset-stacked over the first semiconductor (140, fourth semiconductor chip) by a certain distance along a direction in which a side of the chip stack closest to the first bond finger (104) extends, in a plan view, such that the second chip pad (164, fourth redistribution pads) is farther from the first chip pad (154, third redistribution pads) [annotated Figure 5].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have CHOI as modified by KHALAF and WU to incorporate the teachings of KIM-1 such that the stack package wherein the second semiconductor chip is offset-stacked over the first semiconductor chip by a certain distance along a direction in which a side of the chip stack closest to the first bond finger extends, in a plan view, such that the second chip pad is farther from the first chip pad to provide compact wiring of chip pads with bonding fingers to manufacture an highly integrated stack package (KIM-1, Fig. 6).
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Claim 4, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over CHOI, in view of KHALAF, further in view of WU, and further in view of Yun-rae Cho (hereinafter CHO), US 20100109143 A1.
Regarding Claim 4, CHOI as modified by KHALAF and WU, CHOI further teaches in Figure 7, the stack package (100c, multi-chip package) of Claim 1, wherein the second semiconductor chip (150c) is offset-stacked (in a cross-sectional view) over the first semiconductor chip (140c).
CHOI as modified by KHALAF and WU does not explicitly disclose the stack package wherein the second semiconductor chip is offset-stacked over the first semiconductor chip such that, in a plan view the second chip pad of the second semiconductor chip is positioned between the first chip pad of the first semiconductor chip and another chip pad of the first semiconductor chip adjacent to the first chip pad.
CHO teaches in Figure 6C, the stack package (100, semiconductor package) wherein the second semiconductor chip (120, second substrate) is offset-stacked over the first semiconductor chip (110, first substrate) such that, in a plan view the second chip pad (126, second connection pad) of the second semiconductor chip (120, second substrate) is positioned between the first chip pad (116, first connection pad) of the first semiconductor chip (110, first substrate) and another chip pad (116, first connection pad) of the first semiconductor chip (110, first substrate) adjacent to the first chip pad (116, first connection pad) [annotated Figure 6C].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have CHOI as modified by KHALAF and WU to incorporate the teachings of CHO such that the stack package, wherein the second semiconductor chip is offset-stacked over the first semiconductor chip such that in a plan view, the second chip pad of the second semiconductor chip is positioned between the first chip pad of the first semiconductor chip and another chip pad of the first semiconductor chip adjacent to the first chip pad. This arrangement in a plan view enable a clear-cut positioning of chip connection pads for effecting bonding via wires with the bonding portions or bonding fingers on a package substrate (CHO, Fig. 6C).
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Regarding Claim 19, CHOI as modified by KHALAF and WU, CHOI further teaches in Figure 7, the stack package (100c, multi-chip package) of claim 18, wherein the second semiconductor chip (150c) is offset-stacked (in a cross-sectional view) over the first semiconductor chip (140c). The claim 1 (discussed above) relied upon Figure 4 for the 103 rejection, wherein the two chip stacks are shown with no “off-stacked” in a cross-sectional view. However, the Claim 3, dependent on Claim 1, requires a prior-art to demonstrate the semiconductor chips that are “off-stacked”. Therefore, Figure 7 from CHOI is cited in the above paragraph with the elements showing the “off-stacked” features of (150c) over (140c). Both Figures 1 and 7 are considered in one embodiment per the specification, wherein the multi-chip packages (100c) in Figure 7 may include the package substrate (110a) in Figure 4 or the package substrate (110b) in Figure 7 (CHOI, [0069]).
CHOI as modified by KHALAF and WU does not explicitly disclose the stack package wherein the second semiconductor chip is offset-stacked over the first semiconductor chip such that the second chip pad of the second semiconductor chip is positioned between consecutive chip pads of the first semiconductor chip in a first direction, wherein the consecutive chip pads of the first semiconductor chip include the first chip pad.
CHO teaches in Figure 6C, the stack package (100, semiconductor package) wherein the second semiconductor chip (120, second substrate) is offset-stacked over the first semiconductor chip (110, first substrate) such that, the second chip pad (126, second connection pad) of the second semiconductor chip (120, second substrate) is positioned between the consecutive chip pads (116, first connection pad) of the first semiconductor chip (110, first substrate) and the first chip pad (116, first connection pad) [annotated Figure 6C].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have CHOI as modified by KHALAF and WU to incorporate the teachings of CHO such that the stack package, wherein the second semiconductor chip is offset-stacked over the first semiconductor chip such that the second chip pad of the second semiconductor chip is positioned between consecutive chip pads of the first semiconductor chip in a first direction, wherein the consecutive chip pads of the first semiconductor chip include the first chip pad. This arrangement in a plan view enable a clear-cut positioning of chip connection pads for effecting bonding via wires with the bonding portions or bonding fingers on a package substrate (CHO, Fig. 6C).
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Claims 5 is rejected under 35 U.S.C. 103 as being unpatentable over CHOI, in view of KHALAF, further in view of WU, and further in view of Minoru Morita et al, (hereinafter MORITA), WO 2006109506 A1.
Regarding Claim 5, CHOI as modified by KHALAF and WU, CHOI further teaches in Figure 4, the stack package (100a, multi-chip package) of claim 1, comprising the first bonding wire (160, first conductive wire) connected to the first chip pad (142) to the first portion of the first bond finger (120a, bonding finger, annotated Figure 4).
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CHOI as modified by KHALAF and WU though teaches a stack package comprising the first bonding wire that are connected between the semiconductor chip pad and the bonding finger, CHOI as modified by KHALAF and WU does not explicitly disclose that the stack package further comprising an insulation coating layer covering the first bonding wire.
MORITA teaches in Figure 6, the stack package (10a, semiconductor device) further comprising an insulation coating layer (26, insulating coating layer) covering ([0037]) the first bonding wire (16a, gold wire).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have CHOI as modified by KHALAF and WU to incorporate the teaching of MORITA such that the stack package, further comprising an insulation coating layer covering the first bonding wire so that this arrangement will enable to avoid the contact between the upper semiconductor element and the wire portion to the lower semiconductor element (MORITA, [0006]).
Claims 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over CHOI, in view of KHALAF, further in view of WU, and further in view Jong Hoon Kim (hereinafter KIM-2), US 20110031600 A1.
Regarding Claim 6, CHOI as modified by KHALAF and WU, CHOI further teaches in Figure 4, the stack package (100c, multi-chip package) of Claim 1, wherein the chip stack comprising first semiconductor chip (140) and second semiconductor chip (140).
CHOI as modified by KHALAF and WU does not explicitly disclose the stack package, wherein the chip stack further includes a third semiconductor chip disposed between the first semiconductor chip and the second semiconductor chip.
KIM-2 teaches in Figure 1, the stack package (semiconductor package, [0031]), wherein the chip stack (122) further includes a third semiconductor chip (122) disposed between the first semiconductor chip (122) and the second semiconductor chip (122) [annotated Figure 1].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have CHOI as modified by KHALAF and WU to incorporate the teachings of KIM-2 such that the chip stack further includes a third semiconductor chip disposed between the first semiconductor chip and the second semiconductor chip to improve the chip integration density and stack package functionality. (KIM-2, Fig. 1).
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Regarding Claim 7, CHOI as modified by KHALAF, WU and KIM-2, KIM-2 further teaches in Figure 1, the stack package, wherein the chip stack (122) further includes a fourth semiconductor chip (122) stacked over the second semiconductor chip (122) [annotated Figure 1 above].
Regarding Claim 8, CHOI as modified by KHALAF, WU and KIM-2, KIM-2 further teaches in Figure 1, the stack package of Claim 7, wherein the packaging substrate (110) further includes a second bond finger (annotated Figure 1 above) to which the third semiconductor chip (122) and the fourth semiconductor chip (122) are electrically connected together by additional bonding wires (140, metal wires, annotated Figure 1).
Regarding Claim 9, CHOI as modified by KHALAF, WU and KIM-2, CHOI further teaches in Figure 4, the stack package (100a, multi-chip package) of claim 8, wherein the second bond finger (120a, bonding finger, annotated Figure 4) is on an opposite side of the chip stack in relation to the first bond finger (120a, bonding finger, annotated Figure 4).
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Regarding Claim 10, CHOI as modified by KHALAF and WU, CHOI further teaches in Figure 4, the stack package (100a, multi-chip package) of Claim 1, wherein the chip stack includes a first semiconductor chip (140) and a second semiconductor chip (150) that are sequentially stacked over the packaging substrate (110).
CHOI as modified by KHALAF and WU does not explicitly disclose the stack package of claim 1, wherein the chip stack further includes a third semiconductor chip and a fourth semiconductor chip that are sequentially stacked over the second semiconductor chip.
KIM-2 teaches in Figure 4, the stack package of claim 1, wherein the chip stack (422) further includes a third semiconductor chip (422) and a fourth semiconductor chip (422) that are sequentially stacked over the second semiconductor chip (422, annotated Figure 4).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have CHOI as modified by KHALAF and WU to incorporate the teachings of KIM-2 such that the stack package, wherein the chip stack further includes a third semiconductor chip and a fourth semiconductor chip that are sequentially stacked over the second semiconductor chip to improve the chip integration density and stack package functionality. (KIM-2, Figure 4).
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Claims 16-17, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over by CHOI, view of KHALAF, further in view of WU, and further in view of Keun-ho CHOI, (hereinafter CHOIK), US 20140008796 A1.
Regarding Claim 16, CHOI as modified by KHALAF and WU, CHOI further teaches in Figure 4, the stack package (100a, multi-chip package) of Claim 13.
CHOI as modified by KHALAF and WU though teaches the stack package with the second semiconductor chip over the first semiconductor, CHOI as modified by KHALAF and WU does not disclose explicitly the stack package further comprising: a fourth semiconductor chip stacked over a third semiconductor chip that is stacked over the second semiconductor chip; a second bond finger disposed on the packaging substrate; a third bonding wire connected between the second bond finger at a third position and a third chip pad of the third semiconductor chip; and a fourth bonding wire connected between the second bond finger at a fourth position and a fourth chip pad of the fourth semiconductor chip, wherein the fourth position of the second bond finger is closer to the first semiconductor chip than the third position of the second bond finger; wherein the third bonding wire is electrically connected to the fourth bonding wire through the second bond finger.
CHOIK teaches in Figure 13, the stack package (19, semiconductor package) further comprising:
a fourth semiconductor chip (500) stacked over a third semiconductor chip (400) that is stacked over the second semiconductor chip (300);
a second bond finger (110, first bond pad) disposed on the packaging substrate (100, board);
a third bonding wire (850) connected between the second bond finger (110, first bond pad) at a third position (annotated Figure 13) and a third chip pad (402, third chip pad) of the third semiconductor chip; and
a fourth bonding wire (850) connected between the second bond finger (110, first bond pad) at a fourth position (annotated Figure 13) and a fourth chip pad (802, seventh chip pad) of the fourth semiconductor chip (800, eight semiconductor chip),
wherein the fourth position (annotated Figure 13) of the second bond finger (110, first bond pad) is closer to the first semiconductor chip (200) than the third position (annotated Figure 13) of the second bond finger (110, first bond pad); In this claim limitation though the fourth position of the second bond figure is farther to the first semiconductor chip than the third position of the second bond finger, and this claim limitation further depends on Claim 1, it is obvious to incorporate the teachings of Claim 1 prior-art, by CHOI, wherein
CHOI further teaches in Figure 4, the stack package (100a, multi-chip package) of claim 13, wherein the second portion of the first bond finger is closer to the chip stack than the first portion of the first bond finger (120a, bonding finger, annotated Figure 4 in Claim 1 above).
KHALAF further teaches in Figure 3, a stack package (300, electronic device) of claim 13, wherein the third bonding wire (312c, third bond wire) is electrically connected ([0032]) to the fourth bonding wire (312d, third bond wire) through the second bond finger (306, bond finger).
Regarding Claim 17, CHOI as modified by KHALAF, WU and CHOIK, CHOIK further teaches in Figure 13, the stack package (19, semiconductor package) of claim 16, wherein the first semiconductor chip (200) has a first side opposite to a second side (annotated Figure 4), and wherein the first bond finger (110, first bonding pad) is disposed near the first side (annotated Figure 4) and the second bond finger (120, second bonding pad) is disposed near the second side (annotated Figure 4).
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Regarding Claim 21, CHOI as modified by KHALAF and WU, CHOI further teaches in Figure 4, the stack package (100a, multi-chip package) of claim 18.
CHOI as modified by KHALAF and WU though teaches the stack package with the second semiconductor chip over the first semiconductor, CHOI as modified by KHALAF and WU does not disclose explicitly the stack package further comprising: a fourth semiconductor chip stacked over a third semiconductor chip that is stacked over the second semiconductor chip; a second bond finger formed in a second conductive pattern on the packaging substrate; a third bonding wire connected between the second bond finger at a third position and a third chip pad of the third semiconductor chip; and a fourth bonding wire connected between the second bond finger at a fourth position and a fourth chip pad of the fourth semiconductor chip, wherein the fourth position of the second bond finger is closer to the first semiconductor chip than the third position of the second bond finger; wherein the third bonding wire is electrically connected to the fourth bonding wire through the second bond finger.
CHOIK teaches in Figure 13, the stack package (19, semiconductor package)further comprising:
a fourth semiconductor chip (500) stacked over a third semiconductor chip (400) that is stacked over the second semiconductor chip (300);
a second bond finger (110, first bond pad) formed in a second conductive pattern on the packaging substrate (100, board);
a third bonding wire (850) connected between the second bond finger (110, first bond pad) at a third position (annotated Figure 13) and a third chip pad (402, third chip pad) of the third semiconductor chip; and
a fourth bonding wire (850) connected between the second bond finger (110, first bond pad) at a fourth position (annotated Figure 13) and a fourth chip pad (802, seventh chip pad) of the fourth semiconductor chip (800, eight semiconductor chip),
wherein the fourth position (annotated Figure 13) of the second bond finger (110, first bond pad) is closer to the first semiconductor chip (200) than the third position (annotated Figure 13) of the second bond finger (110, first bond pad); In this claim limitation though the fourth position of the second bond figure is farther to the first semiconductor chip than the third position of the second bond finger, and this claim limitation further depends on Claim 1, it is obvious to incorporate the teachings of Claim 1 prior-art, by CHOI, wherein
CHOI further teaches in Figure 4, the stack package wherein the second portion of the first bond finger is closer to the chip stack than the first portion of the first bond finger (120a, bonding finger, annotated Figure 4).
KHALAF further teaches in Figure 3, a stack package (300, electronic device), wherein the third bonding wire (312c, third bond wire) is electrically connected ([0032]) to the fourth bonding wire (312d, third bond wire) through the second bond finger (306, bond finger).
Regarding Claim 22, CHOI as modified by KHALAF, WU and CHOIK, CHOIK further teaches in Figure 13, the stack package (19, semiconductor package), wherein the first semiconductor chip (200) has a first side opposite to a second side (annotated Figure 4), and wherein the first bond finger (110, first bonding pad) is disposed near the first side (annotated Figure 4) and the second bond finger (120, second bonding pad) is disposed near the second side (annotated Figure 4).
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Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2812
/CHRISTINE S. KIM/ Supervisory Patent Examiner, Art Unit 2812