Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-11 is/are rejected under 35 U.S.C. 102(a)(1)/(2) as being anticipated by Or-Bach (Pub. No.: US 2021/0358794).
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Re claim 1, Or-Bach, Fig. 22 [as shown above] teaches a device comprising:
a host substrate [S] including two or more circuit regions, wherein the two or more circuit regions comprise a first circuit region [FCR] and a second circuit region [SCR] separated by a gap [G] on the host substrate [S]; the first circuit region being associated with a first reticle size (the outline boundary occupied by [FCR], note that [FCR] is including the STI oxide region), the second circuit region being associated with a second reticle size (the outline boundary occupied by [SCR], note that [SCR] is including a little connection region on the far left), the first reticle size and the second reticle size being different;
a component stack [CS] comprising one or more first stacks [FS], each of the one or more first stacks including one or more electrical components (611-620) on one or more layers, each of the one or more first stacks electrically connected to at least one of the two or more circuit regions (two transistors on the left) on the host substrate [S]; and
an interconnect die [ID] comprising one or more second stacks [SS] providing electrical connections between the two or more circuit regions, the one or more second stacks further providing electrical power (by 6001-6009) to the two or more circuit regions (two transistors on the right), wherein at least some of the second stacks (among [6011-6019/6001-6009]) are positioned to span across the gap [G] between the first [FCR] and second circuit regions [SSR] to provide electrical connections between the first [FCR] and second [SCR] circuit regions, wherein at least some of the second stacks include an insulator wafer [IW] bonded to the interconnect die [ID], the interconnect die further connected to at least one of the two or more circuit regions, the first circuit region [FCR] and the second circuit region [SCR] being positioned between the host substrate and the interconnect die;
wherein at least one of the one or more second stacks includes a first electrical pathway to provide the electrical power (6011-6020/6001-6010) to at least one of the two or more circuit regions, the first electrical pathway including an electrically-conductive via (6011-6020/6001-6010) through the insulator wafer [IW] and at least one of an electrically-conductive via through the interconnect die [ID]; and
wherein the interconnect die of at least one of the one or more second stacks includes one or more second electrical pathways (6011-6020/6001-6010) to provide electrical connections between at least two of the two or more circuit regions (two transistors on the left & right).
Re claim 2, Or-Bach teaches the device of claim 1, wherein the insulator wafer of at least one of the one or more second stacks comprises glass (7014/808, Fig. 27C, [0336]/[0162]).
Re claim 3, Or-Bach, Fig. 22 teaches the device of claim 1, wherein the die of at least one of the one or more second stacks comprises one or more patterned semiconductor layers (N+/P+).
Re claim 4, Or-Bach, Fig. 22 teaches the device of claim 1, wherein the one or more second stacks and the one or more first stacks are electrically connected to the host substrate using direct copper bonds [0155].
Re claim 5, Or-Bach teaches the device of claim 1, wherein the die of at least one of the one or more second stacks comprises passive electrical elements (“resistors and capacitors and inductors”, FIG. 1I, [0162]).
Re claim 6, Or-Bach teaches the device of claim 5, wherein the die of at least one of the one or more second stacks further incudes at least one active electrical element (transistors, FIG. 1I, [0162]).
Re claim 7, Or-Bach teaches the device of claim 1, wherein the host substrate is formed from a monolithic wafer (808, FIG. 1I, [0162]).
Re claim 8, Or-Bach teaches the device of claim 1, wherein the host substrate is formed from a reconstituted wafer including a carrier wafer (808, FIG. 1I, [0162]) and two or more host dies (transistors), wherein the two or more circuit regions are distributed between the two or more host dies.
Re claim 9, Or-Bach teaches the device of claim 1, wherein the capacitor in the die comprises a deep trench capacitor (FIGS. 79A-C).
Re claim 10, Or-Bach teaches the device of claim 1, further comprising:
at least one of a printed circuit board or an interposer (19D06, FIG. 7E, [0182]) located in a secondary plane and connected to faces of at least some of the one or more first stacks (including 19D22) or the one or more second stacks (including 19D22) opposite the host substrate (19D16).
Re claim 11, Or-Bach, Fig. 22 teaches the device of claim 10, further comprising: circuitry in the secondary plane (circuitry of 6022) to provide power to the two or more circuit regions (circuitry of 6024) through at least one of the one or more second stacks.
Response to Arguments
Applicant's arguments filed 01/07/2026 have been fully considered but they are moot due to a new ground [NEW MATCHING ELEMENTS] of rejection as listed above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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/TONY TRAN/Primary Examiner, Art Unit 2893